!_TAG_FILE_FORMAT	2	/extended format; --format=1 will not append ;" to lines/
!_TAG_FILE_SORTED	1	/0=unsorted, 1=sorted, 2=foldcase/
!_TAG_PROGRAM_AUTHOR	Darren Hiebert	/dhiebert@users.sourceforge.net/
!_TAG_PROGRAM_NAME	Exuberant Ctags	//
!_TAG_PROGRAM_URL	http://ctags.sourceforge.net	/official site/
!_TAG_PROGRAM_VERSION	5.6	//
ABORT	include/arpa/telnet.h	62;"	d
ACK	include/arpa/tftp.h	53;"	d
ADDRESS_DECODE	dev/gt96132reg.h	137;"	d
ADDRESS_DECODE_ERROR	dev/gt96132reg.h	136;"	d
AI_CANONNAME	include/netdb.h	142;"	d
AI_EXT	include/netdb.h	144;"	d
AI_NUMERICHOST	include/netdb.h	143;"	d
AI_PASSIVE	include/netdb.h	141;"	d
ALGORITHM_EXPIRE_ONLY	include/arpa/nameser.h	238;"	d
ALGORITHM_MD5RSA	include/arpa/nameser.h	237;"	d
ALGORITHM_PRIVATE_OID	include/arpa/nameser.h	239;"	d
AMD_CMDOFFS	include/pflash.h	118;"	d
AMD_CMDOFFS1	include/pflash.h	119;"	d
AMD_CMDOFFS2	include/pflash.h	120;"	d
AO	include/arpa/telnet.h	55;"	d
ARBITER_CONTROL	dev/gt96132reg.h	210;"	d
ARBITER_CONTROL_0_3	dev/gt64240reg.h	474;"	d
ARBITER_CONTROL_0_3	dev/gt64260reg.h	465;"	d
ARBITER_CONTROL_0_3	dev/gt64420reg.h	394;"	d
ARBITER_CONTROL_0_3	dev/mv64340reg.h	404;"	d
ARBITER_CONTROL_4_7	dev/gt64240reg.h	475;"	d
ARBITER_CONTROL_4_7	dev/gt64260reg.h	466;"	d
ARBITER_CONTROL_4_7	dev/gt64420reg.h	395;"	d
ARBITER_CONTROL_4_7	dev/mv64340reg.h	405;"	d
AUTHTYPE_CNT	include/arpa/telnet.h	286;"	d
AUTHTYPE_KERBEROS_V4	include/arpa/telnet.h	282;"	d
AUTHTYPE_KERBEROS_V5	include/arpa/telnet.h	283;"	d
AUTHTYPE_MINK	include/arpa/telnet.h	285;"	d
AUTHTYPE_NAME	include/arpa/telnet.h	300;"	d
AUTHTYPE_NAME_OK	include/arpa/telnet.h	299;"	d
AUTHTYPE_NULL	include/arpa/telnet.h	281;"	d
AUTHTYPE_SPX	include/arpa/telnet.h	284;"	d
AUTHTYPE_TEST	include/arpa/telnet.h	288;"	d
AUTH_HOW_MASK	include/arpa/telnet.h	279;"	d
AUTH_HOW_MUTUAL	include/arpa/telnet.h	278;"	d
AUTH_HOW_ONE_WAY	include/arpa/telnet.h	277;"	d
AUTH_WHO_CLIENT	include/arpa/telnet.h	270;"	d
AUTH_WHO_MASK	include/arpa/telnet.h	272;"	d
AUTH_WHO_SERVER	include/arpa/telnet.h	271;"	d
AUX_ACK	dev/kbd.h	146;"	d
AUX_BUF_SIZE	dev/kbd.h	148;"	d
AUX_DISABLE_DEV	dev/kbd.h	144;"	d
AUX_ENABLE_DEV	dev/kbd.h	143;"	d
AUX_GET_SCALE	dev/kbd.h	140;"	d
AUX_RESET	dev/kbd.h	145;"	d
AUX_SET_RES	dev/kbd.h	137;"	d
AUX_SET_SAMPLE	dev/kbd.h	142;"	d
AUX_SET_SCALE11	dev/kbd.h	138;"	d
AUX_SET_SCALE21	dev/kbd.h	139;"	d
AUX_SET_STREAM	dev/kbd.h	141;"	d
AUX_STAT_OBF	dev/kbd.h	118;"	d
AYT	include/arpa/telnet.h	54;"	d
Addr	include/stdio.h	/^typedef int *Addr;$/;"	t
B0	dev/ns16550.h	66;"	d
B0	include/termio.h	37;"	d
B110	dev/ns16550.h	69;"	d
B110	include/termio.h	40;"	d
B115200	dev/ns16550.h	87;"	d
B115200	include/termio.h	54;"	d
B1200	dev/ns16550.h	75;"	d
B1200	include/termio.h	46;"	d
B134	dev/ns16550.h	70;"	d
B134	include/termio.h	41;"	d
B14400	dev/ns16550.h	83;"	d
B150	dev/ns16550.h	71;"	d
B150	include/termio.h	42;"	d
B1800	dev/ns16550.h	76;"	d
B1800	include/termio.h	47;"	d
B19200	dev/ns16550.h	80;"	d
B19200	include/termio.h	51;"	d
B200	dev/ns16550.h	72;"	d
B200	include/termio.h	43;"	d
B230400	dev/ns16550.h	88;"	d
B2400	dev/ns16550.h	77;"	d
B2400	include/termio.h	48;"	d
B28800	dev/ns16550.h	84;"	d
B300	dev/ns16550.h	73;"	d
B300	include/termio.h	44;"	d
B38400	dev/ns16550.h	81;"	d
B38400	include/termio.h	52;"	d
B4800	dev/ns16550.h	78;"	d
B4800	include/termio.h	49;"	d
B50	dev/ns16550.h	67;"	d
B50	include/termio.h	38;"	d
B57600	dev/ns16550.h	85;"	d
B57600	include/termio.h	53;"	d
B600	dev/ns16550.h	74;"	d
B600	include/termio.h	45;"	d
B7200	dev/ns16550.h	82;"	d
B75	dev/ns16550.h	68;"	d
B75	include/termio.h	39;"	d
B76800	dev/ns16550.h	86;"	d
B9600	dev/ns16550.h	79;"	d
B9600	include/termio.h	50;"	d
BANCHOR	lib.c	107;"	d	file:
BASE	include/linux/zutil.h	73;"	d
BASE_ADDRESS_ENABLE_REG	dev/gt64420reg.h	180;"	d
BASE_ADDR_ENABLE	dev/mv64360reg.h	138;"	d
BIG_ENDIAN	include/arpa/nameser.h	267;"	d
BLK_BYTECOUNT	include/arpa/ftp.h	110;"	d
BLK_EOF	include/arpa/ftp.h	106;"	d
BLK_EOR	include/arpa/ftp.h	105;"	d
BLK_ERRORS	include/arpa/ftp.h	107;"	d
BLK_RESTART	include/arpa/ftp.h	108;"	d
BONITO	include/tgt/bonito.h	16;"	d
BONITO	include/tgt/bonito.h	9;"	d
BONITO_BONGENCFG	include/tgt/bonito.h	183;"	d
BONITO_BONGENCFG_BUSERREN	include/tgt/bonito.h	201;"	d
BONITO_BONGENCFG_BYTESWAP	include/tgt/bonito.h	192;"	d
BONITO_BONGENCFG_CACHEALG	include/tgt/bonito.h	196;"	d
BONITO_BONGENCFG_CACHEALG_SHIFT	include/tgt/bonito.h	197;"	d
BONITO_BONGENCFG_CACHESTOP	include/tgt/bonito.h	199;"	d
BONITO_BONGENCFG_CPUSELFRESET	include/tgt/bonito.h	187;"	d
BONITO_BONGENCFG_DEBUGMODE	include/tgt/bonito.h	185;"	d
BONITO_BONGENCFG_FORCE_IRQA	include/tgt/bonito.h	189;"	d
BONITO_BONGENCFG_IRQA_FROM_INT1	include/tgt/bonito.h	191;"	d
BONITO_BONGENCFG_IRQA_ISOUT	include/tgt/bonito.h	190;"	d
BONITO_BONGENCFG_MSTRBYTESWAP	include/tgt/bonito.h	200;"	d
BONITO_BONGENCFG_NORETRYTIMEOUT	include/tgt/bonito.h	202;"	d
BONITO_BONGENCFG_OFFSET	include/tgt/bonito.h	182;"	d
BONITO_BONGENCFG_PCIQUEUE	include/tgt/bonito.h	198;"	d
BONITO_BONGENCFG_PREFETCHEN	include/tgt/bonito.h	194;"	d
BONITO_BONGENCFG_SHORTCOPYTIMEOUT	include/tgt/bonito.h	203;"	d
BONITO_BONGENCFG_SNOOPEN	include/tgt/bonito.h	186;"	d
BONITO_BONGENCFG_WBEHINDEN	include/tgt/bonito.h	195;"	d
BONITO_BONITOBASE	include/tgt/bonito.h	269;"	d
BONITO_BONPONCFG	include/tgt/bonito.h	154;"	d
BONITO_BONPONCFG_CONFIG_DIS	include/tgt/bonito.h	177;"	d
BONITO_BONPONCFG_CPUBIGEND	include/tgt/bonito.h	159;"	d
BONITO_BONPONCFG_CPUPARITY	include/tgt/bonito.h	160;"	d
BONITO_BONPONCFG_CPUTYPE	include/tgt/bonito.h	161;"	d
BONITO_BONPONCFG_CPUTYPE_SHIFT	include/tgt/bonito.h	162;"	d
BONITO_BONPONCFG_IS_ARBITER	include/tgt/bonito.h	164;"	d
BONITO_BONPONCFG_PCIRESET_OUT	include/tgt/bonito.h	163;"	d
BONITO_BONPONCFG_ROMBOOT	include/tgt/bonito.h	165;"	d
BONITO_BONPONCFG_ROMBOOT_CPURESET	include/tgt/bonito.h	171;"	d
BONITO_BONPONCFG_ROMBOOT_FLASH	include/tgt/bonito.h	168;"	d
BONITO_BONPONCFG_ROMBOOT_SDRAM	include/tgt/bonito.h	170;"	d
BONITO_BONPONCFG_ROMBOOT_SHIFT	include/tgt/bonito.h	166;"	d
BONITO_BONPONCFG_ROMBOOT_SOCKET	include/tgt/bonito.h	169;"	d
BONITO_BONPONCFG_ROMCS0FAST	include/tgt/bonito.h	175;"	d
BONITO_BONPONCFG_ROMCS0SAMP	include/tgt/bonito.h	158;"	d
BONITO_BONPONCFG_ROMCS0WIDTH	include/tgt/bonito.h	173;"	d
BONITO_BONPONCFG_ROMCS1FAST	include/tgt/bonito.h	176;"	d
BONITO_BONPONCFG_ROMCS1SAMP	include/tgt/bonito.h	157;"	d
BONITO_BONPONCFG_ROMCS1WIDTH	include/tgt/bonito.h	174;"	d
BONITO_BONPONCFG_SYSCONTROLLERRD	include/tgt/bonito.h	156;"	d
BONITO_BOOT_BASE	include/tgt/bonito.h	82;"	d
BONITO_BOOT_BASE	include/tgt/bonito.h	83;"	d
BONITO_BOOT_SIZE	include/tgt/bonito.h	84;"	d
BONITO_BOOT_TOP	include/tgt/bonito.h	85;"	d
BONITO_CONFIGBASE	include/tgt/bonito.h	268;"	d
BONITO_COPBASE	include/tgt/bonito.h	271;"	d
BONITO_COPCTRL	include/tgt/bonito.h	280;"	d
BONITO_COPDADDR	include/tgt/bonito.h	283;"	d
BONITO_COPGO	include/tgt/bonito.h	284;"	d
BONITO_COPPADDR	include/tgt/bonito.h	282;"	d
BONITO_COPSTAT	include/tgt/bonito.h	281;"	d
BONITO_DEV_BASE	include/tgt/bonito.h	95;"	d
BONITO_DEV_SIZE	include/tgt/bonito.h	96;"	d
BONITO_DEV_TOP	include/tgt/bonito.h	97;"	d
BONITO_FLASH_BASE	include/tgt/bonito.h	1;"	d
BONITO_FLASH_BASE	include/tgt/bonito.h	86;"	d
BONITO_FLASH_SIZE	include/tgt/bonito.h	87;"	d
BONITO_FLASH_TOP	include/tgt/bonito.h	88;"	d
BONITO_GPIODATA	include/tgt/bonito.h	224;"	d
BONITO_GPIODATA_OFFSET	include/tgt/bonito.h	223;"	d
BONITO_GPIOIE	include/tgt/bonito.h	225;"	d
BONITO_GPIO_GPINR	include/tgt/bonito.h	372;"	d
BONITO_GPIO_GPINR_SHIFT	include/tgt/bonito.h	373;"	d
BONITO_GPIO_GPIOR	include/tgt/bonito.h	370;"	d
BONITO_GPIO_GPIOR_SHIFT	include/tgt/bonito.h	371;"	d
BONITO_GPIO_GPIOW	include/tgt/bonito.h	368;"	d
BONITO_GPIO_GPIOW_SHIFT	include/tgt/bonito.h	369;"	d
BONITO_GPIO_INR	include/tgt/bonito.h	376;"	d
BONITO_GPIO_IOR	include/tgt/bonito.h	375;"	d
BONITO_GPIO_IOW	include/tgt/bonito.h	374;"	d
BONITO_ICU_COPYEMPTY	include/tgt/bonito.h	384;"	d
BONITO_ICU_COPYERR	include/tgt/bonito.h	385;"	d
BONITO_ICU_COPYRDY	include/tgt/bonito.h	383;"	d
BONITO_ICU_DMAEMPTY	include/tgt/bonito.h	382;"	d
BONITO_ICU_DMARDY	include/tgt/bonito.h	381;"	d
BONITO_ICU_DRAMPERR	include/tgt/bonito.h	389;"	d
BONITO_ICU_GPIN	include/tgt/bonito.h	397;"	d
BONITO_ICU_GPINS	include/tgt/bonito.h	393;"	d
BONITO_ICU_GPINS_SHIFT	include/tgt/bonito.h	394;"	d
BONITO_ICU_GPIO	include/tgt/bonito.h	396;"	d
BONITO_ICU_GPIOS	include/tgt/bonito.h	391;"	d
BONITO_ICU_GPIOS_SHIFT	include/tgt/bonito.h	392;"	d
BONITO_ICU_MASTERERR	include/tgt/bonito.h	387;"	d
BONITO_ICU_MBOX	include/tgt/bonito.h	395;"	d
BONITO_ICU_MBOXES	include/tgt/bonito.h	379;"	d
BONITO_ICU_MBOXES_SHIFT	include/tgt/bonito.h	380;"	d
BONITO_ICU_PCIIRQ	include/tgt/bonito.h	386;"	d
BONITO_ICU_RETRYERR	include/tgt/bonito.h	390;"	d
BONITO_ICU_SYSTEMERR	include/tgt/bonito.h	388;"	d
BONITO_IDECOPCTRL_DMA_RSTBIT	include/tgt/bonito.h	302;"	d
BONITO_IDECOPCTRL_DMA_STARTBIT	include/tgt/bonito.h	301;"	d
BONITO_IDECOPDADDR_DMA_DADDR	include/tgt/bonito.h	291;"	d
BONITO_IDECOPDADDR_DMA_DADDR_SHIFT	include/tgt/bonito.h	292;"	d
BONITO_IDECOPGO_DMAWCOUNT	include/tgt/bonito.h	298;"	d
BONITO_IDECOPGO_DMAWCOUNT_SHIFT	include/tgt/bonito.h	299;"	d
BONITO_IDECOPGO_DMA_SIZE	include/tgt/bonito.h	295;"	d
BONITO_IDECOPGO_DMA_SIZE_SHIFT	include/tgt/bonito.h	296;"	d
BONITO_IDECOPGO_DMA_WRITE	include/tgt/bonito.h	297;"	d
BONITO_IDECOPPADDR_DMA_PADDR	include/tgt/bonito.h	293;"	d
BONITO_IDECOPPADDR_DMA_PADDR_SHIFT	include/tgt/bonito.h	294;"	d
BONITO_INTEDGE	include/tgt/bonito.h	229;"	d
BONITO_INTEN	include/tgt/bonito.h	237;"	d
BONITO_INTENCLR	include/tgt/bonito.h	236;"	d
BONITO_INTENSET	include/tgt/bonito.h	235;"	d
BONITO_INTISR	include/tgt/bonito.h	238;"	d
BONITO_INTPOL	include/tgt/bonito.h	231;"	d
BONITO_INTSTEER	include/tgt/bonito.h	230;"	d
BONITO_IODEVCFG	include/tgt/bonito.h	207;"	d
BONITO_IODEVCFG_BUFFBIT_CS0	include/tgt/bonito.h	341;"	d
BONITO_IODEVCFG_BUFFBIT_CS1	include/tgt/bonito.h	345;"	d
BONITO_IODEVCFG_BUFFBIT_CS2	include/tgt/bonito.h	349;"	d
BONITO_IODEVCFG_BUFFBIT_CS3	include/tgt/bonito.h	353;"	d
BONITO_IODEVCFG_BUFFBIT_IDE	include/tgt/bonito.h	357;"	d
BONITO_IODEVCFG_DMAOFF_IDE	include/tgt/bonito.h	363;"	d
BONITO_IODEVCFG_DMAOFF_IDE_SHIFT	include/tgt/bonito.h	364;"	d
BONITO_IODEVCFG_DMAON_IDE	include/tgt/bonito.h	361;"	d
BONITO_IODEVCFG_DMAON_IDE_SHIFT	include/tgt/bonito.h	362;"	d
BONITO_IODEVCFG_EPROMSPLIT	include/tgt/bonito.h	365;"	d
BONITO_IODEVCFG_MODEBIT_IDE	include/tgt/bonito.h	360;"	d
BONITO_IODEVCFG_MOREABITS_CS0	include/tgt/bonito.h	343;"	d
BONITO_IODEVCFG_MOREABITS_CS1	include/tgt/bonito.h	347;"	d
BONITO_IODEVCFG_MOREABITS_CS2	include/tgt/bonito.h	351;"	d
BONITO_IODEVCFG_MOREABITS_CS3	include/tgt/bonito.h	355;"	d
BONITO_IODEVCFG_SPEEDBIT_CS0	include/tgt/bonito.h	342;"	d
BONITO_IODEVCFG_SPEEDBIT_CS1	include/tgt/bonito.h	346;"	d
BONITO_IODEVCFG_SPEEDBIT_CS2	include/tgt/bonito.h	350;"	d
BONITO_IODEVCFG_SPEEDBIT_CS3	include/tgt/bonito.h	354;"	d
BONITO_IODEVCFG_SPEEDBIT_IDE	include/tgt/bonito.h	358;"	d
BONITO_IODEVCFG_WORDSWAPBIT_IDE	include/tgt/bonito.h	359;"	d
BONITO_LDMAADDR	include/tgt/bonito.h	276;"	d
BONITO_LDMABASE	include/tgt/bonito.h	270;"	d
BONITO_LDMACTRL	include/tgt/bonito.h	274;"	d
BONITO_LDMADATA	include/tgt/bonito.h	278;"	d
BONITO_LDMAGO	include/tgt/bonito.h	277;"	d
BONITO_LDMASTAT	include/tgt/bonito.h	275;"	d
BONITO_PCIBADADDR	include/tgt/bonito.h	257;"	d
BONITO_PCIBASE0	include/tgt/bonito.h	130;"	d
BONITO_PCIBASE1	include/tgt/bonito.h	131;"	d
BONITO_PCIBASE2	include/tgt/bonito.h	132;"	d
BONITO_PCICACHECTRL	include/tgt/bonito.h	254;"	d
BONITO_PCICACHECTRL_CACHECMD	include/tgt/bonito.h	335;"	d
BONITO_PCICACHECTRL_CACHECMDLINE	include/tgt/bonito.h	337;"	d
BONITO_PCICACHECTRL_CACHECMDLINE_SHIFT	include/tgt/bonito.h	338;"	d
BONITO_PCICACHECTRL_CACHECMD_SHIFT	include/tgt/bonito.h	336;"	d
BONITO_PCICACHECTRL_CMDEXEC	include/tgt/bonito.h	339;"	d
BONITO_PCICACHETAG	include/tgt/bonito.h	255;"	d
BONITO_PCICFG_BASE	include/tgt/bonito.h	112;"	d
BONITO_PCICFG_SIZE	include/tgt/bonito.h	113;"	d
BONITO_PCICFG_TOP	include/tgt/bonito.h	114;"	d
BONITO_PCICLASS	include/tgt/bonito.h	128;"	d
BONITO_PCICMD	include/tgt/bonito.h	127;"	d
BONITO_PCICMD_ASTEPEN	include/tgt/bonito.h	143;"	d
BONITO_PCICMD_MABORT_CLR	include/tgt/bonito.h	138;"	d
BONITO_PCICMD_MEMEN	include/tgt/bonito.h	450;"	d
BONITO_PCICMD_MPERR_CLR	include/tgt/bonito.h	141;"	d
BONITO_PCICMD_MSTREN	include/tgt/bonito.h	451;"	d
BONITO_PCICMD_MTABORT_CLR	include/tgt/bonito.h	139;"	d
BONITO_PCICMD_PERRRESPEN	include/tgt/bonito.h	142;"	d
BONITO_PCICMD_PERR_CLR	include/tgt/bonito.h	136;"	d
BONITO_PCICMD_SERREN	include/tgt/bonito.h	144;"	d
BONITO_PCICMD_SERR_CLR	include/tgt/bonito.h	137;"	d
BONITO_PCICMD_TABORT_CLR	include/tgt/bonito.h	140;"	d
BONITO_PCICONFIGBASE	include/tgt/bonito.h	119;"	d
BONITO_PCIDID	include/tgt/bonito.h	126;"	d
BONITO_PCIEXPRBASE	include/tgt/bonito.h	133;"	d
BONITO_PCIHI_BASE	include/tgt/bonito.h	105;"	d
BONITO_PCIHI_SIZE	include/tgt/bonito.h	106;"	d
BONITO_PCIHI_TOP	include/tgt/bonito.h	107;"	d
BONITO_PCIINT	include/tgt/bonito.h	134;"	d
BONITO_PCIIO_BASE	include/tgt/bonito.h	108;"	d
BONITO_PCIIO_BASE_VA	include/tgt/bonito.h	109;"	d
BONITO_PCIIO_SIZE	include/tgt/bonito.h	110;"	d
BONITO_PCIIO_TOP	include/tgt/bonito.h	111;"	d
BONITO_PCILO0_BASE	include/tgt/bonito.h	102;"	d
BONITO_PCILO1_BASE	include/tgt/bonito.h	103;"	d
BONITO_PCILO2_BASE	include/tgt/bonito.h	104;"	d
BONITO_PCILO_BASE	include/tgt/bonito.h	98;"	d
BONITO_PCILO_BASE_VA	include/tgt/bonito.h	99;"	d
BONITO_PCILO_SIZE	include/tgt/bonito.h	100;"	d
BONITO_PCILO_TOP	include/tgt/bonito.h	101;"	d
BONITO_PCILTIMER	include/tgt/bonito.h	129;"	d
BONITO_PCILTIMER_BUSLATENCY	include/tgt/bonito.h	145;"	d
BONITO_PCILTIMER_BUSLATENCY_SHIFT	include/tgt/bonito.h	146;"	d
BONITO_PCIMAIL0	include/tgt/bonito.h	246;"	d
BONITO_PCIMAIL0_OFFSET	include/tgt/bonito.h	242;"	d
BONITO_PCIMAIL1	include/tgt/bonito.h	247;"	d
BONITO_PCIMAIL1_OFFSET	include/tgt/bonito.h	243;"	d
BONITO_PCIMAIL2	include/tgt/bonito.h	248;"	d
BONITO_PCIMAIL2_OFFSET	include/tgt/bonito.h	244;"	d
BONITO_PCIMAIL3	include/tgt/bonito.h	249;"	d
BONITO_PCIMAIL3_OFFSET	include/tgt/bonito.h	245;"	d
BONITO_PCIMAP	include/tgt/bonito.h	215;"	d
BONITO_PCIMAP_CFG	include/tgt/bonito.h	217;"	d
BONITO_PCIMAP_PCIMAP_2	include/tgt/bonito.h	407;"	d
BONITO_PCIMAP_PCIMAP_LO0	include/tgt/bonito.h	401;"	d
BONITO_PCIMAP_PCIMAP_LO0_SHIFT	include/tgt/bonito.h	402;"	d
BONITO_PCIMAP_PCIMAP_LO1	include/tgt/bonito.h	403;"	d
BONITO_PCIMAP_PCIMAP_LO1_SHIFT	include/tgt/bonito.h	404;"	d
BONITO_PCIMAP_PCIMAP_LO2	include/tgt/bonito.h	405;"	d
BONITO_PCIMAP_PCIMAP_LO2_SHIFT	include/tgt/bonito.h	406;"	d
BONITO_PCIMAP_WIN	include/tgt/bonito.h	408;"	d
BONITO_PCIMAP_WINBASE	include/tgt/bonito.h	412;"	d
BONITO_PCIMAP_WINOFFSET	include/tgt/bonito.h	411;"	d
BONITO_PCIMAP_WINSIZE	include/tgt/bonito.h	410;"	d
BONITO_PCIMEMBASECFG	include/tgt/bonito.h	216;"	d
BONITO_PCIMEMBASECFGBASE	include/tgt/bonito.h	434;"	d
BONITO_PCIMEMBASECFGSIZE	include/tgt/bonito.h	433;"	d
BONITO_PCIMEMBASECFG_ADDRMASK	include/tgt/bonito.h	439;"	d
BONITO_PCIMEMBASECFG_ADDRMASK	include/tgt/bonito.h	440;"	d
BONITO_PCIMEMBASECFG_ADDRTRANS	include/tgt/bonito.h	441;"	d
BONITO_PCIMEMBASECFG_AMASK	include/tgt/bonito.h	432;"	d
BONITO_PCIMEMBASECFG_ASHIFT	include/tgt/bonito.h	431;"	d
BONITO_PCIMEMBASECFG_MASK	include/tgt/bonito.h	416;"	d
BONITO_PCIMEMBASECFG_MEMBASE0_CACHED	include/tgt/bonito.h	421;"	d
BONITO_PCIMEMBASECFG_MEMBASE0_IO	include/tgt/bonito.h	422;"	d
BONITO_PCIMEMBASECFG_MEMBASE0_MASK	include/tgt/bonito.h	417;"	d
BONITO_PCIMEMBASECFG_MEMBASE0_MASK_SHIFT	include/tgt/bonito.h	418;"	d
BONITO_PCIMEMBASECFG_MEMBASE0_TRANS	include/tgt/bonito.h	419;"	d
BONITO_PCIMEMBASECFG_MEMBASE0_TRANS_SHIFT	include/tgt/bonito.h	420;"	d
BONITO_PCIMEMBASECFG_MEMBASE1_CACHED	include/tgt/bonito.h	428;"	d
BONITO_PCIMEMBASECFG_MEMBASE1_IO	include/tgt/bonito.h	429;"	d
BONITO_PCIMEMBASECFG_MEMBASE1_MASK	include/tgt/bonito.h	424;"	d
BONITO_PCIMEMBASECFG_MEMBASE1_MASK_SHIFT	include/tgt/bonito.h	425;"	d
BONITO_PCIMEMBASECFG_MEMBASE1_TRANS	include/tgt/bonito.h	426;"	d
BONITO_PCIMEMBASECFG_MEMBASE1_TRANS_SHIFT	include/tgt/bonito.h	427;"	d
BONITO_PCIMEMBASECFG_SIZE	include/tgt/bonito.h	436;"	d
BONITO_PCIMSTAT	include/tgt/bonito.h	258;"	d
BONITO_PCITOPHYS	include/tgt/bonito.h	443;"	d
BONITO_PCI_REG	include/tgt/bonito.h	125;"	d
BONITO_REGBASE	include/tgt/bonito.h	120;"	d
BONITO_REG_BASE	include/tgt/bonito.h	92;"	d
BONITO_REG_BLOCKMASK	include/tgt/bonito.h	272;"	d
BONITO_REG_SIZE	include/tgt/bonito.h	93;"	d
BONITO_REG_TOP	include/tgt/bonito.h	94;"	d
BONITO_SDCFG	include/tgt/bonito.h	211;"	d
BONITO_SDCFG_AABSENT	include/tgt/bonito.h	312;"	d
BONITO_SDCFG_ABANKBIT	include/tgt/bonito.h	310;"	d
BONITO_SDCFG_ACOLBITS	include/tgt/bonito.h	308;"	d
BONITO_SDCFG_ACOLBITS_SHIFT	include/tgt/bonito.h	309;"	d
BONITO_SDCFG_AROWBITS	include/tgt/bonito.h	306;"	d
BONITO_SDCFG_AROWBITS_SHIFT	include/tgt/bonito.h	307;"	d
BONITO_SDCFG_ASIDES	include/tgt/bonito.h	311;"	d
BONITO_SDCFG_AWIDTH64	include/tgt/bonito.h	313;"	d
BONITO_SDCFG_BABSENT	include/tgt/bonito.h	321;"	d
BONITO_SDCFG_BBANKBIT	include/tgt/bonito.h	319;"	d
BONITO_SDCFG_BCOLBITS	include/tgt/bonito.h	317;"	d
BONITO_SDCFG_BCOLBITS_SHIFT	include/tgt/bonito.h	318;"	d
BONITO_SDCFG_BROWBITS	include/tgt/bonito.h	315;"	d
BONITO_SDCFG_BROWBITS_SHIFT	include/tgt/bonito.h	316;"	d
BONITO_SDCFG_BSIDES	include/tgt/bonito.h	320;"	d
BONITO_SDCFG_BWIDTH64	include/tgt/bonito.h	322;"	d
BONITO_SDCFG_DDRTYPE_SHIFT	include/tgt/bonito.h	462;"	d
BONITO_SDCFG_DIMM_MOD_NUM_SHIFT	include/tgt/bonito.h	464;"	d
BONITO_SDCFG_DRAMEXTREGS	include/tgt/bonito.h	330;"	d
BONITO_SDCFG_DRAMPARITY	include/tgt/bonito.h	331;"	d
BONITO_SDCFG_DRAMRESET	include/tgt/bonito.h	329;"	d
BONITO_SDCFG_EXTPRECH	include/tgt/bonito.h	326;"	d
BONITO_SDCFG_EXTRASCAS	include/tgt/bonito.h	325;"	d
BONITO_SDCFG_EXTRASWIDTH	include/tgt/bonito.h	327;"	d
BONITO_SDCFG_EXTRASWIDTH_SHIFT	include/tgt/bonito.h	328;"	d
BONITO_SDCFG_EXTRDDATA	include/tgt/bonito.h	324;"	d
BONITO_SDCFG_ISSEQ_SHIFT	include/tgt/bonito.h	463;"	d
BONITO_SDCFG_TCAS_SHIFT	include/tgt/bonito.h	457;"	d
BONITO_SDCFG_TRAS_SHIFT	include/tgt/bonito.h	458;"	d
BONITO_SDCFG_TRCD_SHIFT	include/tgt/bonito.h	460;"	d
BONITO_SDCFG_TRC_SHIFT	include/tgt/bonito.h	454;"	d
BONITO_SDCFG_TREF_SHIFT	include/tgt/bonito.h	461;"	d
BONITO_SDCFG_TRFC_SHIFT	include/tgt/bonito.h	459;"	d
BONITO_SDCFG_TRP_SHIFT	include/tgt/bonito.h	455;"	d
BONITO_SDCFG_TWR_SHIFT	include/tgt/bonito.h	456;"	d
BONITO_SOCKET_BASE	include/tgt/bonito.h	89;"	d
BONITO_SOCKET_SIZE	include/tgt/bonito.h	90;"	d
BONITO_SOCKET_TOP	include/tgt/bonito.h	91;"	d
BOOTCS_BASE_ADDR	dev/mv64360reg.h	102;"	d
BOOTCS_BASE_ADDRESS	dev/gt64420reg.h	153;"	d
BOOTCS_BASE_ADDRESS	dev/mv64340reg.h	167;"	d
BOOTCS_HIGH_DECODE_ADDRESS	dev/gt64240reg.h	164;"	d
BOOTCS_HIGH_DECODE_ADDRESS	dev/gt64260reg.h	155;"	d
BOOTCS_HIGH_DECODE_ADDRESS	dev/gt96132reg.h	135;"	d
BOOTCS_LOW_DECODE_ADDRESS	dev/gt64240reg.h	163;"	d
BOOTCS_LOW_DECODE_ADDRESS	dev/gt64260reg.h	154;"	d
BOOTCS_LOW_DECODE_ADDRESS	dev/gt96132reg.h	134;"	d
BOOTCS_SIZE	dev/gt64420reg.h	154;"	d
BOOTCS_SIZE	dev/mv64340reg.h	168;"	d
BOOTCS_SIZE	dev/mv64360reg.h	103;"	d
BREAK	include/arpa/telnet.h	57;"	d
BRG0_BAUD_TUNE_REG	dev/gt96132reg.h	776;"	d
BRG0_BAUD_TUNING_REG	dev/gt64240reg.h	1188;"	d
BRG0_BAUD_TUNING_REG	dev/gt64260reg.h	1179;"	d
BRG0_BAUD_TUNING_REG	dev/gt64420reg.h	924;"	d
BRG0_BAUD_TUNING_REG	dev/mv64340reg.h	1038;"	d
BRG0_CFG_REG	dev/gt64240reg.h	1187;"	d
BRG0_CFG_REG	dev/gt64260reg.h	1178;"	d
BRG0_CFG_REG	dev/gt64420reg.h	923;"	d
BRG0_CFG_REG	dev/mv64340reg.h	1037;"	d
BRG0_CONFIG_REG	dev/gt96132reg.h	775;"	d
BRG1_BAUD_TUNE_REG	dev/gt96132reg.h	778;"	d
BRG1_BAUD_TUNING_REG	dev/gt64240reg.h	1193;"	d
BRG1_BAUD_TUNING_REG	dev/gt64260reg.h	1184;"	d
BRG1_BAUD_TUNING_REG	dev/gt64420reg.h	929;"	d
BRG1_BAUD_TUNING_REG	dev/mv64340reg.h	1043;"	d
BRG1_CFG_REG	dev/gt64240reg.h	1192;"	d
BRG1_CFG_REG	dev/gt64260reg.h	1183;"	d
BRG1_CFG_REG	dev/gt64420reg.h	928;"	d
BRG1_CFG_REG	dev/mv64340reg.h	1042;"	d
BRG1_CONFIG_REG	dev/gt96132reg.h	777;"	d
BRG2_BAUD_TUNE_REG	dev/gt96132reg.h	780;"	d
BRG2_BAUD_TUNING_REG	dev/gt64240reg.h	1198;"	d
BRG2_BAUD_TUNING_REG	dev/gt64260reg.h	1189;"	d
BRG2_BAUD_TUNING_REG	dev/gt64420reg.h	934;"	d
BRG2_BAUD_TUNING_REG	dev/mv64340reg.h	1048;"	d
BRG2_CFG_REGISTER	dev/gt64240reg.h	1197;"	d
BRG2_CFG_REGISTER	dev/gt64260reg.h	1188;"	d
BRG2_CFG_REGISTER	dev/gt64420reg.h	933;"	d
BRG2_CFG_REGISTER	dev/mv64340reg.h	1047;"	d
BRG2_CONFIG_REG	dev/gt96132reg.h	779;"	d
BRG3_BAUD_TUNE_REG	dev/gt96132reg.h	782;"	d
BRG3_CONFIG_REG	dev/gt96132reg.h	781;"	d
BRG4_BAUD_TUNE_REG	dev/gt96132reg.h	784;"	d
BRG4_CONFIG_REG	dev/gt96132reg.h	783;"	d
BRG5_BAUD_TUNE_REG	dev/gt96132reg.h	786;"	d
BRG5_CONFIG_REG	dev/gt96132reg.h	785;"	d
BRG6_BAUD_TUNE_REG	dev/gt96132reg.h	788;"	d
BRG6_CONFIG_REG	dev/gt96132reg.h	787;"	d
BRG7_BAUD_TUNE_REG	dev/gt96132reg.h	790;"	d
BRG7_CONFIG_REG	dev/gt96132reg.h	789;"	d
BRG_BAUDE_TUNING_REG	dev/gt64420reg.h	1043;"	d
BRG_BAUDE_TUNING_REG	dev/mv64360reg.h	914;"	d
BRG_CAUSE_REG	dev/gt64420reg.h	1044;"	d
BRG_CAUSE_REG	dev/mv64360reg.h	915;"	d
BRG_CAUSE_REGISTER	dev/gt64240reg.h	1202;"	d
BRG_CAUSE_REGISTER	dev/gt64260reg.h	1193;"	d
BRG_CAUSE_REGISTER	dev/gt64420reg.h	938;"	d
BRG_CAUSE_REGISTER	dev/gt96132reg.h	318;"	d
BRG_CAUSE_REGISTER	dev/mv64340reg.h	1052;"	d
BRG_CONFIG_REG	dev/gt64420reg.h	1042;"	d
BRG_CONFIG_REG	dev/mv64360reg.h	913;"	d
BRG_MASK_REG	dev/gt64420reg.h	1045;"	d
BRG_MASK_REG	dev/mv64360reg.h	916;"	d
BRG_MASK_REGISTER	dev/gt64240reg.h	1203;"	d
BRG_MASK_REGISTER	dev/gt64260reg.h	1194;"	d
BRG_MASK_REGISTER	dev/gt64420reg.h	939;"	d
BRG_MASK_REGISTER	dev/gt96132reg.h	319;"	d
BRG_MASK_REGISTER	dev/mv64340reg.h	1053;"	d
BUS_INTR_DISESTABLISH	include/autoconf.h	90;"	d
BUS_INTR_ESTABLISH	include/autoconf.h	88;"	d
BUS_ISABR	include/autoconf.h	83;"	d
BUS_LOCAL	include/autoconf.h	86;"	d
BUS_MAIN	include/autoconf.h	82;"	d
BUS_MATCHNAME	include/autoconf.h	92;"	d
BUS_PCIBR	include/autoconf.h	84;"	d
BUS_VMEBR	include/autoconf.h	85;"	d
BYTE_ORDER	include/arpa/nameser.h	273;"	d
BYTE_ORDER	include/arpa/nameser.h	283;"	d
Bps	include/pmon.h	/^typedef struct Bps {$/;"	s
Bps	include/pmon.h	/^} Bps;$/;"	t	typeref:struct:Bps
Byte	include/linux/zconf.h	/^typedef unsigned char  Byte;  \/* 8 bits *\/$/;"	t
Bytef	include/linux/zconf.h	/^typedef Byte  FAR Bytef;$/;"	t
CAUSEB_BD	include/ri.h	60;"	d
CAUSEF_BD	include/ri.h	61;"	d
CBREAK	include/termio.h	17;"	d
CFCR_5BITS	dev/ns16550.h	145;"	d
CFCR_6BITS	dev/ns16550.h	144;"	d
CFCR_7BITS	dev/ns16550.h	143;"	d
CFCR_8BITS	dev/ns16550.h	142;"	d
CFCR_DLAB	dev/ns16550.h	134;"	d
CFCR_PENAB	dev/ns16550.h	140;"	d
CFCR_PEVEN	dev/ns16550.h	138;"	d
CFCR_PODD	dev/ns16550.h	139;"	d
CFCR_PONE	dev/ns16550.h	137;"	d
CFCR_PZERO	dev/ns16550.h	136;"	d
CFCR_SBREAK	dev/ns16550.h	135;"	d
CFCR_STOPB	dev/ns16550.h	141;"	d
CHANELS0_3_ERROR_ADDRESS	dev/gt64240reg.h	484;"	d
CHANELS0_3_ERROR_ADDRESS	dev/gt64260reg.h	475;"	d
CHANELS0_3_ERROR_ADDRESS	dev/gt64420reg.h	404;"	d
CHANELS0_3_ERROR_ADDRESS	dev/mv64340reg.h	414;"	d
CHANELS0_3_ERROR_SELECT	dev/gt64240reg.h	485;"	d
CHANELS0_3_ERROR_SELECT	dev/gt64260reg.h	476;"	d
CHANELS0_3_ERROR_SELECT	dev/gt64420reg.h	405;"	d
CHANELS0_3_ERROR_SELECT	dev/mv64340reg.h	415;"	d
CHANELS0_3_INTERRUPT_CAUSE	dev/gt64240reg.h	482;"	d
CHANELS0_3_INTERRUPT_CAUSE	dev/gt64260reg.h	473;"	d
CHANELS0_3_INTERRUPT_CAUSE	dev/gt64420reg.h	402;"	d
CHANELS0_3_INTERRUPT_CAUSE	dev/mv64340reg.h	412;"	d
CHANELS0_3_INTERRUPT_MASK	dev/gt64240reg.h	483;"	d
CHANELS0_3_INTERRUPT_MASK	dev/gt64260reg.h	474;"	d
CHANELS0_3_INTERRUPT_MASK	dev/gt64420reg.h	403;"	d
CHANELS0_3_INTERRUPT_MASK	dev/mv64340reg.h	413;"	d
CHANELS4_7_ERROR_ADDRESS	dev/gt64240reg.h	488;"	d
CHANELS4_7_ERROR_ADDRESS	dev/gt64260reg.h	479;"	d
CHANELS4_7_ERROR_ADDRESS	dev/gt64420reg.h	408;"	d
CHANELS4_7_ERROR_ADDRESS	dev/mv64340reg.h	418;"	d
CHANELS4_7_ERROR_SELECT	dev/gt64240reg.h	489;"	d
CHANELS4_7_ERROR_SELECT	dev/gt64260reg.h	480;"	d
CHANELS4_7_ERROR_SELECT	dev/gt64420reg.h	409;"	d
CHANELS4_7_ERROR_SELECT	dev/mv64340reg.h	419;"	d
CHANELS4_7_INTERRUPT_CAUSE	dev/gt64240reg.h	486;"	d
CHANELS4_7_INTERRUPT_CAUSE	dev/gt64260reg.h	477;"	d
CHANELS4_7_INTERRUPT_CAUSE	dev/gt64420reg.h	406;"	d
CHANELS4_7_INTERRUPT_CAUSE	dev/mv64340reg.h	416;"	d
CHANELS4_7_INTERRUPT_MASK	dev/gt64240reg.h	487;"	d
CHANELS4_7_INTERRUPT_MASK	dev/gt64260reg.h	478;"	d
CHANELS4_7_INTERRUPT_MASK	dev/gt64420reg.h	407;"	d
CHANELS4_7_INTERRUPT_MASK	dev/mv64340reg.h	417;"	d
CHANNEL0CONTROL	dev/gt64240reg.h	451;"	d
CHANNEL0CONTROL	dev/gt64260reg.h	442;"	d
CHANNEL0CONTROL	dev/gt64420reg.h	371;"	d
CHANNEL0CONTROL	dev/gt96132reg.h	201;"	d
CHANNEL0CONTROL	dev/mv64340reg.h	391;"	d
CHANNEL0CONTROL_HIGH	dev/gt64240reg.h	452;"	d
CHANNEL0CONTROL_HIGH	dev/gt64260reg.h	443;"	d
CHANNEL0CONTROL_HIGH	dev/gt64420reg.h	372;"	d
CHANNEL0CONTROL_HIGH	dev/mv64340reg.h	392;"	d
CHANNEL0CURRENT_DESCRIPTOR_POINTER	dev/gt64240reg.h	414;"	d
CHANNEL0CURRENT_DESCRIPTOR_POINTER	dev/gt64260reg.h	405;"	d
CHANNEL0CURRENT_DESCRIPTOR_POINTER	dev/gt64420reg.h	334;"	d
CHANNEL0CURRENT_DESCRIPTOR_POINTER	dev/gt96132reg.h	192;"	d
CHANNEL0CURRENT_DESCRIPTOR_POINTER	dev/mv64340reg.h	382;"	d
CHANNEL0NEXT_RECORD_POINTER	dev/gt64240reg.h	406;"	d
CHANNEL0NEXT_RECORD_POINTER	dev/gt64260reg.h	397;"	d
CHANNEL0NEXT_RECORD_POINTER	dev/gt64420reg.h	326;"	d
CHANNEL0NEXT_RECORD_POINTER	dev/gt96132reg.h	188;"	d
CHANNEL0NEXT_RECORD_POINTER	dev/mv64340reg.h	378;"	d
CHANNEL0_COMMAND_REGISTER	dev/gt64240reg.h	1135;"	d
CHANNEL0_COMMAND_REGISTER	dev/gt64260reg.h	1126;"	d
CHANNEL0_COMMAND_REGISTER	dev/gt64420reg.h	871;"	d
CHANNEL0_COMMAND_REGISTER	dev/mv64340reg.h	985;"	d
CHANNEL0_CONFIGURATION_REGISTER	dev/gt64240reg.h	1134;"	d
CHANNEL0_CONFIGURATION_REGISTER	dev/gt64260reg.h	1125;"	d
CHANNEL0_CONFIGURATION_REGISTER	dev/gt64420reg.h	870;"	d
CHANNEL0_CONFIGURATION_REGISTER	dev/mv64340reg.h	984;"	d
CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER	dev/gt64240reg.h	1140;"	d
CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER	dev/gt64260reg.h	1131;"	d
CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER	dev/gt64420reg.h	876;"	d
CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER	dev/mv64340reg.h	990;"	d
CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER	dev/gt64240reg.h	1145;"	d
CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER	dev/gt64260reg.h	1136;"	d
CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER	dev/gt64420reg.h	881;"	d
CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER	dev/mv64340reg.h	995;"	d
CHANNEL0_DMA_BYTE_COUNT	dev/gt64240reg.h	382;"	d
CHANNEL0_DMA_BYTE_COUNT	dev/gt64260reg.h	373;"	d
CHANNEL0_DMA_BYTE_COUNT	dev/gt64420reg.h	302;"	d
CHANNEL0_DMA_BYTE_COUNT	dev/gt96132reg.h	176;"	d
CHANNEL0_DMA_BYTE_COUNT	dev/mv64340reg.h	366;"	d
CHANNEL0_DMA_DESTINATION_ADDRESS	dev/gt64240reg.h	398;"	d
CHANNEL0_DMA_DESTINATION_ADDRESS	dev/gt64260reg.h	389;"	d
CHANNEL0_DMA_DESTINATION_ADDRESS	dev/gt64420reg.h	318;"	d
CHANNEL0_DMA_DESTINATION_ADDRESS	dev/gt96132reg.h	184;"	d
CHANNEL0_DMA_DESTINATION_ADDRESS	dev/mv64340reg.h	374;"	d
CHANNEL0_DMA_DESTINATION_HIGH_PCI_ADDRESS	dev/gt64240reg.h	430;"	d
CHANNEL0_DMA_DESTINATION_HIGH_PCI_ADDRESS	dev/gt64260reg.h	421;"	d
CHANNEL0_DMA_DESTINATION_HIGH_PCI_ADDRESS	dev/gt64420reg.h	350;"	d
CHANNEL0_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS	dev/gt64240reg.h	438;"	d
CHANNEL0_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS	dev/gt64260reg.h	429;"	d
CHANNEL0_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS	dev/gt64420reg.h	358;"	d
CHANNEL0_DMA_SOURCE_ADDRESS	dev/gt64240reg.h	390;"	d
CHANNEL0_DMA_SOURCE_ADDRESS	dev/gt64260reg.h	381;"	d
CHANNEL0_DMA_SOURCE_ADDRESS	dev/gt64420reg.h	310;"	d
CHANNEL0_DMA_SOURCE_ADDRESS	dev/gt96132reg.h	180;"	d
CHANNEL0_DMA_SOURCE_ADDRESS	dev/mv64340reg.h	370;"	d
CHANNEL0_DMA_SOURCE_HIGH_PCI_ADDRESS	dev/gt64240reg.h	422;"	d
CHANNEL0_DMA_SOURCE_HIGH_PCI_ADDRESS	dev/gt64260reg.h	413;"	d
CHANNEL0_DMA_SOURCE_HIGH_PCI_ADDRESS	dev/gt64420reg.h	342;"	d
CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER	dev/gt64240reg.h	1146;"	d
CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER	dev/gt64260reg.h	1137;"	d
CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER	dev/gt64420reg.h	882;"	d
CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER	dev/mv64340reg.h	996;"	d
CHANNEL0_REGISTER1	dev/gt64240reg.h	1272;"	d
CHANNEL0_REGISTER1	dev/gt64260reg.h	1263;"	d
CHANNEL0_REGISTER1	dev/mv64340reg.h	1122;"	d
CHANNEL0_REGISTER10	dev/gt64240reg.h	1281;"	d
CHANNEL0_REGISTER10	dev/gt64260reg.h	1272;"	d
CHANNEL0_REGISTER10	dev/mv64340reg.h	1131;"	d
CHANNEL0_REGISTER11	dev/gt64240reg.h	1282;"	d
CHANNEL0_REGISTER11	dev/gt64260reg.h	1273;"	d
CHANNEL0_REGISTER11	dev/mv64340reg.h	1132;"	d
CHANNEL0_REGISTER2	dev/gt64240reg.h	1273;"	d
CHANNEL0_REGISTER2	dev/gt64260reg.h	1264;"	d
CHANNEL0_REGISTER2	dev/mv64340reg.h	1123;"	d
CHANNEL0_REGISTER3	dev/gt64240reg.h	1274;"	d
CHANNEL0_REGISTER3	dev/gt64260reg.h	1265;"	d
CHANNEL0_REGISTER3	dev/mv64340reg.h	1124;"	d
CHANNEL0_REGISTER4	dev/gt64240reg.h	1275;"	d
CHANNEL0_REGISTER4	dev/gt64260reg.h	1266;"	d
CHANNEL0_REGISTER4	dev/mv64340reg.h	1125;"	d
CHANNEL0_REGISTER5	dev/gt64240reg.h	1276;"	d
CHANNEL0_REGISTER5	dev/gt64260reg.h	1267;"	d
CHANNEL0_REGISTER5	dev/mv64340reg.h	1126;"	d
CHANNEL0_REGISTER6	dev/gt64240reg.h	1277;"	d
CHANNEL0_REGISTER6	dev/gt64260reg.h	1268;"	d
CHANNEL0_REGISTER6	dev/mv64340reg.h	1127;"	d
CHANNEL0_REGISTER7	dev/gt64240reg.h	1278;"	d
CHANNEL0_REGISTER7	dev/gt64260reg.h	1269;"	d
CHANNEL0_REGISTER7	dev/mv64340reg.h	1128;"	d
CHANNEL0_REGISTER8	dev/gt64240reg.h	1279;"	d
CHANNEL0_REGISTER8	dev/gt64260reg.h	1270;"	d
CHANNEL0_REGISTER8	dev/mv64340reg.h	1129;"	d
CHANNEL0_REGISTER9	dev/gt64240reg.h	1280;"	d
CHANNEL0_REGISTER9	dev/gt64260reg.h	1271;"	d
CHANNEL0_REGISTER9	dev/mv64340reg.h	1130;"	d
CHANNEL0_RX_BUFFER_POINTER	dev/gt64240reg.h	1138;"	d
CHANNEL0_RX_BUFFER_POINTER	dev/gt64260reg.h	1129;"	d
CHANNEL0_RX_BUFFER_POINTER	dev/gt64420reg.h	874;"	d
CHANNEL0_RX_BUFFER_POINTER	dev/mv64340reg.h	988;"	d
CHANNEL0_RX_CMD_STATUS	dev/gt64240reg.h	1136;"	d
CHANNEL0_RX_CMD_STATUS	dev/gt64260reg.h	1127;"	d
CHANNEL0_RX_CMD_STATUS	dev/gt64420reg.h	872;"	d
CHANNEL0_RX_CMD_STATUS	dev/mv64340reg.h	986;"	d
CHANNEL0_RX_NEXT_POINTER	dev/gt64240reg.h	1139;"	d
CHANNEL0_RX_NEXT_POINTER	dev/gt64260reg.h	1130;"	d
CHANNEL0_RX_NEXT_POINTER	dev/gt64420reg.h	875;"	d
CHANNEL0_RX_NEXT_POINTER	dev/mv64340reg.h	989;"	d
CHANNEL0_RX_PACKET_AND_BUFFER_SIZES	dev/gt64240reg.h	1137;"	d
CHANNEL0_RX_PACKET_AND_BUFFER_SIZES	dev/gt64260reg.h	1128;"	d
CHANNEL0_RX_PACKET_AND_BUFFER_SIZES	dev/gt64420reg.h	873;"	d
CHANNEL0_RX_PACKET_AND_BUFFER_SIZES	dev/mv64340reg.h	987;"	d
CHANNEL0_TX_BUFFER_POINTER	dev/gt64240reg.h	1143;"	d
CHANNEL0_TX_BUFFER_POINTER	dev/gt64260reg.h	1134;"	d
CHANNEL0_TX_BUFFER_POINTER	dev/gt64420reg.h	879;"	d
CHANNEL0_TX_BUFFER_POINTER	dev/mv64340reg.h	993;"	d
CHANNEL0_TX_CMD_STATUS	dev/gt64240reg.h	1141;"	d
CHANNEL0_TX_CMD_STATUS	dev/gt64260reg.h	1132;"	d
CHANNEL0_TX_CMD_STATUS	dev/gt64420reg.h	877;"	d
CHANNEL0_TX_CMD_STATUS	dev/mv64340reg.h	991;"	d
CHANNEL0_TX_NEXT_POINTER	dev/gt64240reg.h	1144;"	d
CHANNEL0_TX_NEXT_POINTER	dev/gt64260reg.h	1135;"	d
CHANNEL0_TX_NEXT_POINTER	dev/gt64420reg.h	880;"	d
CHANNEL0_TX_NEXT_POINTER	dev/mv64340reg.h	994;"	d
CHANNEL0_TX_PACKET_SIZE	dev/gt64240reg.h	1142;"	d
CHANNEL0_TX_PACKET_SIZE	dev/gt64260reg.h	1133;"	d
CHANNEL0_TX_PACKET_SIZE	dev/gt64420reg.h	878;"	d
CHANNEL0_TX_PACKET_SIZE	dev/mv64340reg.h	992;"	d
CHANNEL1CONTROL	dev/gt64240reg.h	453;"	d
CHANNEL1CONTROL	dev/gt64260reg.h	444;"	d
CHANNEL1CONTROL	dev/gt64420reg.h	373;"	d
CHANNEL1CONTROL	dev/gt96132reg.h	202;"	d
CHANNEL1CONTROL	dev/mv64340reg.h	393;"	d
CHANNEL1CONTROL_HIGH	dev/gt64240reg.h	454;"	d
CHANNEL1CONTROL_HIGH	dev/gt64260reg.h	445;"	d
CHANNEL1CONTROL_HIGH	dev/gt64420reg.h	374;"	d
CHANNEL1CONTROL_HIGH	dev/mv64340reg.h	394;"	d
CHANNEL1CURRENT_DESCRIPTOR_POINTER	dev/gt64240reg.h	415;"	d
CHANNEL1CURRENT_DESCRIPTOR_POINTER	dev/gt64260reg.h	406;"	d
CHANNEL1CURRENT_DESCRIPTOR_POINTER	dev/gt64420reg.h	335;"	d
CHANNEL1CURRENT_DESCRIPTOR_POINTER	dev/gt96132reg.h	193;"	d
CHANNEL1CURRENT_DESCRIPTOR_POINTER	dev/mv64340reg.h	383;"	d
CHANNEL1NEXT_RECORD_POINTER	dev/gt64240reg.h	407;"	d
CHANNEL1NEXT_RECORD_POINTER	dev/gt64260reg.h	398;"	d
CHANNEL1NEXT_RECORD_POINTER	dev/gt64420reg.h	327;"	d
CHANNEL1NEXT_RECORD_POINTER	dev/gt96132reg.h	189;"	d
CHANNEL1NEXT_RECORD_POINTER	dev/mv64340reg.h	379;"	d
CHANNEL1_COMMAND_REGISTER	dev/gt64240reg.h	1148;"	d
CHANNEL1_COMMAND_REGISTER	dev/gt64260reg.h	1139;"	d
CHANNEL1_COMMAND_REGISTER	dev/gt64420reg.h	884;"	d
CHANNEL1_COMMAND_REGISTER	dev/mv64340reg.h	998;"	d
CHANNEL1_CONFIGURATION_REGISTER	dev/gt64240reg.h	1147;"	d
CHANNEL1_CONFIGURATION_REGISTER	dev/gt64260reg.h	1138;"	d
CHANNEL1_CONFIGURATION_REGISTER	dev/gt64420reg.h	883;"	d
CHANNEL1_CONFIGURATION_REGISTER	dev/mv64340reg.h	997;"	d
CHANNEL1_CURRENT_RX_DESCRIPTOR_POINTER	dev/gt64240reg.h	1157;"	d
CHANNEL1_CURRENT_RX_DESCRIPTOR_POINTER	dev/gt64260reg.h	1148;"	d
CHANNEL1_CURRENT_RX_DESCRIPTOR_POINTER	dev/gt64420reg.h	893;"	d
CHANNEL1_CURRENT_RX_DESCRIPTOR_POINTER	dev/mv64340reg.h	1007;"	d
CHANNEL1_CURRENT_TX_DESCRIPTOR_POINTER	dev/gt64240reg.h	1158;"	d
CHANNEL1_CURRENT_TX_DESCRIPTOR_POINTER	dev/gt64260reg.h	1149;"	d
CHANNEL1_CURRENT_TX_DESCRIPTOR_POINTER	dev/gt64420reg.h	894;"	d
CHANNEL1_CURRENT_TX_DESCRIPTOR_POINTER	dev/mv64340reg.h	1008;"	d
CHANNEL1_DMA_BYTE_COUNT	dev/gt64240reg.h	383;"	d
CHANNEL1_DMA_BYTE_COUNT	dev/gt64260reg.h	374;"	d
CHANNEL1_DMA_BYTE_COUNT	dev/gt64420reg.h	303;"	d
CHANNEL1_DMA_BYTE_COUNT	dev/gt96132reg.h	177;"	d
CHANNEL1_DMA_BYTE_COUNT	dev/mv64340reg.h	367;"	d
CHANNEL1_DMA_DESTINATION_ADDRESS	dev/gt64240reg.h	399;"	d
CHANNEL1_DMA_DESTINATION_ADDRESS	dev/gt64260reg.h	390;"	d
CHANNEL1_DMA_DESTINATION_ADDRESS	dev/gt64420reg.h	319;"	d
CHANNEL1_DMA_DESTINATION_ADDRESS	dev/gt96132reg.h	185;"	d
CHANNEL1_DMA_DESTINATION_ADDRESS	dev/mv64340reg.h	375;"	d
CHANNEL1_DMA_DESTINATION_HIGH_PCI_ADDRESS	dev/gt64240reg.h	431;"	d
CHANNEL1_DMA_DESTINATION_HIGH_PCI_ADDRESS	dev/gt64260reg.h	422;"	d
CHANNEL1_DMA_DESTINATION_HIGH_PCI_ADDRESS	dev/gt64420reg.h	351;"	d
CHANNEL1_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS	dev/gt64240reg.h	439;"	d
CHANNEL1_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS	dev/gt64260reg.h	430;"	d
CHANNEL1_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS	dev/gt64420reg.h	359;"	d
CHANNEL1_DMA_SOURCE_ADDRESS	dev/gt64240reg.h	391;"	d
CHANNEL1_DMA_SOURCE_ADDRESS	dev/gt64260reg.h	382;"	d
CHANNEL1_DMA_SOURCE_ADDRESS	dev/gt64420reg.h	311;"	d
CHANNEL1_DMA_SOURCE_ADDRESS	dev/gt96132reg.h	181;"	d
CHANNEL1_DMA_SOURCE_ADDRESS	dev/mv64340reg.h	371;"	d
CHANNEL1_DMA_SOURCE_HIGH_PCI_ADDRESS	dev/gt64240reg.h	423;"	d
CHANNEL1_DMA_SOURCE_HIGH_PCI_ADDRESS	dev/gt64260reg.h	414;"	d
CHANNEL1_DMA_SOURCE_HIGH_PCI_ADDRESS	dev/gt64420reg.h	343;"	d
CHANNEL1_FIRST_TX_DESCRIPTOR_POINTER	dev/gt64240reg.h	1159;"	d
CHANNEL1_FIRST_TX_DESCRIPTOR_POINTER	dev/gt64260reg.h	1150;"	d
CHANNEL1_FIRST_TX_DESCRIPTOR_POINTER	dev/gt64420reg.h	895;"	d
CHANNEL1_FIRST_TX_DESCRIPTOR_POINTER	dev/mv64340reg.h	1009;"	d
CHANNEL1_REGISTER1	dev/gt64240reg.h	1289;"	d
CHANNEL1_REGISTER1	dev/gt64260reg.h	1280;"	d
CHANNEL1_REGISTER1	dev/mv64340reg.h	1139;"	d
CHANNEL1_REGISTER10	dev/gt64240reg.h	1298;"	d
CHANNEL1_REGISTER10	dev/gt64260reg.h	1289;"	d
CHANNEL1_REGISTER10	dev/mv64340reg.h	1148;"	d
CHANNEL1_REGISTER11	dev/gt64240reg.h	1299;"	d
CHANNEL1_REGISTER11	dev/gt64260reg.h	1290;"	d
CHANNEL1_REGISTER11	dev/mv64340reg.h	1149;"	d
CHANNEL1_REGISTER2	dev/gt64240reg.h	1290;"	d
CHANNEL1_REGISTER2	dev/gt64260reg.h	1281;"	d
CHANNEL1_REGISTER2	dev/mv64340reg.h	1140;"	d
CHANNEL1_REGISTER3	dev/gt64240reg.h	1291;"	d
CHANNEL1_REGISTER3	dev/gt64260reg.h	1282;"	d
CHANNEL1_REGISTER3	dev/mv64340reg.h	1141;"	d
CHANNEL1_REGISTER4	dev/gt64240reg.h	1292;"	d
CHANNEL1_REGISTER4	dev/gt64260reg.h	1283;"	d
CHANNEL1_REGISTER4	dev/mv64340reg.h	1142;"	d
CHANNEL1_REGISTER5	dev/gt64240reg.h	1293;"	d
CHANNEL1_REGISTER5	dev/gt64260reg.h	1284;"	d
CHANNEL1_REGISTER5	dev/mv64340reg.h	1143;"	d
CHANNEL1_REGISTER6	dev/gt64240reg.h	1294;"	d
CHANNEL1_REGISTER6	dev/gt64260reg.h	1285;"	d
CHANNEL1_REGISTER6	dev/mv64340reg.h	1144;"	d
CHANNEL1_REGISTER7	dev/gt64240reg.h	1295;"	d
CHANNEL1_REGISTER7	dev/gt64260reg.h	1286;"	d
CHANNEL1_REGISTER7	dev/mv64340reg.h	1145;"	d
CHANNEL1_REGISTER8	dev/gt64240reg.h	1296;"	d
CHANNEL1_REGISTER8	dev/gt64260reg.h	1287;"	d
CHANNEL1_REGISTER8	dev/mv64340reg.h	1146;"	d
CHANNEL1_REGISTER9	dev/gt64240reg.h	1297;"	d
CHANNEL1_REGISTER9	dev/gt64260reg.h	1288;"	d
CHANNEL1_REGISTER9	dev/mv64340reg.h	1147;"	d
CHANNEL1_RX_BUFFER_POINTER	dev/gt64240reg.h	1151;"	d
CHANNEL1_RX_BUFFER_POINTER	dev/gt64260reg.h	1142;"	d
CHANNEL1_RX_BUFFER_POINTER	dev/gt64420reg.h	887;"	d
CHANNEL1_RX_BUFFER_POINTER	dev/mv64340reg.h	1001;"	d
CHANNEL1_RX_CMD_STATUS	dev/gt64240reg.h	1149;"	d
CHANNEL1_RX_CMD_STATUS	dev/gt64260reg.h	1140;"	d
CHANNEL1_RX_CMD_STATUS	dev/gt64420reg.h	885;"	d
CHANNEL1_RX_CMD_STATUS	dev/mv64340reg.h	999;"	d
CHANNEL1_RX_NEXT_POINTER	dev/gt64240reg.h	1152;"	d
CHANNEL1_RX_NEXT_POINTER	dev/gt64260reg.h	1143;"	d
CHANNEL1_RX_NEXT_POINTER	dev/gt64420reg.h	888;"	d
CHANNEL1_RX_NEXT_POINTER	dev/mv64340reg.h	1002;"	d
CHANNEL1_RX_PACKET_AND_BUFFER_SIZES	dev/gt64240reg.h	1150;"	d
CHANNEL1_RX_PACKET_AND_BUFFER_SIZES	dev/gt64260reg.h	1141;"	d
CHANNEL1_RX_PACKET_AND_BUFFER_SIZES	dev/gt64420reg.h	886;"	d
CHANNEL1_RX_PACKET_AND_BUFFER_SIZES	dev/mv64340reg.h	1000;"	d
CHANNEL1_TX_BUFFER_POINTER	dev/gt64240reg.h	1155;"	d
CHANNEL1_TX_BUFFER_POINTER	dev/gt64260reg.h	1146;"	d
CHANNEL1_TX_BUFFER_POINTER	dev/gt64420reg.h	891;"	d
CHANNEL1_TX_BUFFER_POINTER	dev/mv64340reg.h	1005;"	d
CHANNEL1_TX_CMD_STATUS	dev/gt64240reg.h	1153;"	d
CHANNEL1_TX_CMD_STATUS	dev/gt64260reg.h	1144;"	d
CHANNEL1_TX_CMD_STATUS	dev/gt64420reg.h	889;"	d
CHANNEL1_TX_CMD_STATUS	dev/mv64340reg.h	1003;"	d
CHANNEL1_TX_NEXT_POINTER	dev/gt64240reg.h	1156;"	d
CHANNEL1_TX_NEXT_POINTER	dev/gt64260reg.h	1147;"	d
CHANNEL1_TX_NEXT_POINTER	dev/gt64420reg.h	892;"	d
CHANNEL1_TX_NEXT_POINTER	dev/mv64340reg.h	1006;"	d
CHANNEL1_TX_PACKET_SIZE	dev/gt64240reg.h	1154;"	d
CHANNEL1_TX_PACKET_SIZE	dev/gt64260reg.h	1145;"	d
CHANNEL1_TX_PACKET_SIZE	dev/gt64420reg.h	890;"	d
CHANNEL1_TX_PACKET_SIZE	dev/mv64340reg.h	1004;"	d
CHANNEL2CONTROL	dev/gt64240reg.h	455;"	d
CHANNEL2CONTROL	dev/gt64260reg.h	446;"	d
CHANNEL2CONTROL	dev/gt64420reg.h	375;"	d
CHANNEL2CONTROL	dev/gt96132reg.h	203;"	d
CHANNEL2CONTROL	dev/mv64340reg.h	395;"	d
CHANNEL2CONTROL_HIGH	dev/gt64240reg.h	456;"	d
CHANNEL2CONTROL_HIGH	dev/gt64260reg.h	447;"	d
CHANNEL2CONTROL_HIGH	dev/gt64420reg.h	376;"	d
CHANNEL2CONTROL_HIGH	dev/mv64340reg.h	396;"	d
CHANNEL2CURRENT_DESCRIPTOR_POINTER	dev/gt64240reg.h	416;"	d
CHANNEL2CURRENT_DESCRIPTOR_POINTER	dev/gt64260reg.h	407;"	d
CHANNEL2CURRENT_DESCRIPTOR_POINTER	dev/gt64420reg.h	336;"	d
CHANNEL2CURRENT_DESCRIPTOR_POINTER	dev/gt96132reg.h	194;"	d
CHANNEL2CURRENT_DESCRIPTOR_POINTER	dev/mv64340reg.h	384;"	d
CHANNEL2NEXT_RECORD_POINTER	dev/gt64240reg.h	408;"	d
CHANNEL2NEXT_RECORD_POINTER	dev/gt64260reg.h	399;"	d
CHANNEL2NEXT_RECORD_POINTER	dev/gt64420reg.h	328;"	d
CHANNEL2NEXT_RECORD_POINTER	dev/gt96132reg.h	190;"	d
CHANNEL2NEXT_RECORD_POINTER	dev/mv64340reg.h	380;"	d
CHANNEL2_COMMAND_REGISTER	dev/gt64240reg.h	1161;"	d
CHANNEL2_COMMAND_REGISTER	dev/gt64260reg.h	1152;"	d
CHANNEL2_COMMAND_REGISTER	dev/gt64420reg.h	897;"	d
CHANNEL2_COMMAND_REGISTER	dev/mv64340reg.h	1011;"	d
CHANNEL2_CONFIGURATION_REGISTER	dev/gt64240reg.h	1160;"	d
CHANNEL2_CONFIGURATION_REGISTER	dev/gt64260reg.h	1151;"	d
CHANNEL2_CONFIGURATION_REGISTER	dev/gt64420reg.h	896;"	d
CHANNEL2_CONFIGURATION_REGISTER	dev/mv64340reg.h	1010;"	d
CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER	dev/gt64240reg.h	1166;"	d
CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER	dev/gt64240reg.h	1171;"	d
CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER	dev/gt64260reg.h	1157;"	d
CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER	dev/gt64260reg.h	1162;"	d
CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER	dev/gt64420reg.h	902;"	d
CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER	dev/gt64420reg.h	907;"	d
CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER	dev/mv64340reg.h	1016;"	d
CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER	dev/mv64340reg.h	1021;"	d
CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER	dev/gt64240reg.h	1172;"	d
CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER	dev/gt64260reg.h	1163;"	d
CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER	dev/gt64420reg.h	908;"	d
CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER	dev/mv64340reg.h	1022;"	d
CHANNEL2_DMA_BYTE_COUNT	dev/gt64240reg.h	384;"	d
CHANNEL2_DMA_BYTE_COUNT	dev/gt64260reg.h	375;"	d
CHANNEL2_DMA_BYTE_COUNT	dev/gt64420reg.h	304;"	d
CHANNEL2_DMA_BYTE_COUNT	dev/gt96132reg.h	178;"	d
CHANNEL2_DMA_BYTE_COUNT	dev/mv64340reg.h	368;"	d
CHANNEL2_DMA_DESTINATION_ADDRESS	dev/gt64240reg.h	400;"	d
CHANNEL2_DMA_DESTINATION_ADDRESS	dev/gt64260reg.h	391;"	d
CHANNEL2_DMA_DESTINATION_ADDRESS	dev/gt64420reg.h	320;"	d
CHANNEL2_DMA_DESTINATION_ADDRESS	dev/gt96132reg.h	186;"	d
CHANNEL2_DMA_DESTINATION_ADDRESS	dev/mv64340reg.h	376;"	d
CHANNEL2_DMA_DESTINATION_HIGH_PCI_ADDRESS	dev/gt64240reg.h	432;"	d
CHANNEL2_DMA_DESTINATION_HIGH_PCI_ADDRESS	dev/gt64260reg.h	423;"	d
CHANNEL2_DMA_DESTINATION_HIGH_PCI_ADDRESS	dev/gt64420reg.h	352;"	d
CHANNEL2_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS	dev/gt64240reg.h	440;"	d
CHANNEL2_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS	dev/gt64260reg.h	431;"	d
CHANNEL2_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS	dev/gt64420reg.h	360;"	d
CHANNEL2_DMA_SOURCE_ADDRESS	dev/gt64240reg.h	392;"	d
CHANNEL2_DMA_SOURCE_ADDRESS	dev/gt64260reg.h	383;"	d
CHANNEL2_DMA_SOURCE_ADDRESS	dev/gt64420reg.h	312;"	d
CHANNEL2_DMA_SOURCE_ADDRESS	dev/gt96132reg.h	182;"	d
CHANNEL2_DMA_SOURCE_ADDRESS	dev/mv64340reg.h	372;"	d
CHANNEL2_DMA_SOURCE_HIGH_PCI_ADDRESS	dev/gt64240reg.h	424;"	d
CHANNEL2_DMA_SOURCE_HIGH_PCI_ADDRESS	dev/gt64260reg.h	415;"	d
CHANNEL2_DMA_SOURCE_HIGH_PCI_ADDRESS	dev/gt64420reg.h	344;"	d
CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER	dev/gt64240reg.h	1173;"	d
CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER	dev/gt64260reg.h	1164;"	d
CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER	dev/gt64420reg.h	909;"	d
CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER	dev/mv64340reg.h	1023;"	d
CHANNEL2_REGISTER1	dev/gt64240reg.h	1306;"	d
CHANNEL2_REGISTER1	dev/mv64340reg.h	1156;"	d
CHANNEL2_REGISTER10	dev/gt64240reg.h	1315;"	d
CHANNEL2_REGISTER10	dev/mv64340reg.h	1165;"	d
CHANNEL2_REGISTER11	dev/gt64240reg.h	1316;"	d
CHANNEL2_REGISTER11	dev/mv64340reg.h	1166;"	d
CHANNEL2_REGISTER2	dev/gt64240reg.h	1307;"	d
CHANNEL2_REGISTER2	dev/mv64340reg.h	1157;"	d
CHANNEL2_REGISTER3	dev/gt64240reg.h	1308;"	d
CHANNEL2_REGISTER3	dev/mv64340reg.h	1158;"	d
CHANNEL2_REGISTER4	dev/gt64240reg.h	1309;"	d
CHANNEL2_REGISTER4	dev/mv64340reg.h	1159;"	d
CHANNEL2_REGISTER5	dev/gt64240reg.h	1310;"	d
CHANNEL2_REGISTER5	dev/mv64340reg.h	1160;"	d
CHANNEL2_REGISTER6	dev/gt64240reg.h	1311;"	d
CHANNEL2_REGISTER6	dev/mv64340reg.h	1161;"	d
CHANNEL2_REGISTER7	dev/gt64240reg.h	1312;"	d
CHANNEL2_REGISTER7	dev/mv64340reg.h	1162;"	d
CHANNEL2_REGISTER8	dev/gt64240reg.h	1313;"	d
CHANNEL2_REGISTER8	dev/mv64340reg.h	1163;"	d
CHANNEL2_REGISTER9	dev/gt64240reg.h	1314;"	d
CHANNEL2_REGISTER9	dev/mv64340reg.h	1164;"	d
CHANNEL2_RX_BUFFER_POINTER	dev/gt64240reg.h	1164;"	d
CHANNEL2_RX_BUFFER_POINTER	dev/gt64260reg.h	1155;"	d
CHANNEL2_RX_BUFFER_POINTER	dev/gt64420reg.h	900;"	d
CHANNEL2_RX_BUFFER_POINTER	dev/mv64340reg.h	1014;"	d
CHANNEL2_RX_CMD_STATUS	dev/gt64240reg.h	1162;"	d
CHANNEL2_RX_CMD_STATUS	dev/gt64260reg.h	1153;"	d
CHANNEL2_RX_CMD_STATUS	dev/gt64420reg.h	898;"	d
CHANNEL2_RX_CMD_STATUS	dev/mv64340reg.h	1012;"	d
CHANNEL2_RX_NEXT_POINTER	dev/gt64240reg.h	1165;"	d
CHANNEL2_RX_NEXT_POINTER	dev/gt64260reg.h	1156;"	d
CHANNEL2_RX_NEXT_POINTER	dev/gt64420reg.h	901;"	d
CHANNEL2_RX_NEXT_POINTER	dev/mv64340reg.h	1015;"	d
CHANNEL2_RX_PACKET_AND_BUFFER_SIZES	dev/gt64240reg.h	1163;"	d
CHANNEL2_RX_PACKET_AND_BUFFER_SIZES	dev/gt64260reg.h	1154;"	d
CHANNEL2_RX_PACKET_AND_BUFFER_SIZES	dev/gt64420reg.h	899;"	d
CHANNEL2_RX_PACKET_AND_BUFFER_SIZES	dev/mv64340reg.h	1013;"	d
CHANNEL2_TX_BUFFER_POINTER	dev/gt64240reg.h	1169;"	d
CHANNEL2_TX_BUFFER_POINTER	dev/gt64260reg.h	1160;"	d
CHANNEL2_TX_BUFFER_POINTER	dev/gt64420reg.h	905;"	d
CHANNEL2_TX_BUFFER_POINTER	dev/mv64340reg.h	1019;"	d
CHANNEL2_TX_CMD_STATUS	dev/gt64240reg.h	1167;"	d
CHANNEL2_TX_CMD_STATUS	dev/gt64260reg.h	1158;"	d
CHANNEL2_TX_CMD_STATUS	dev/gt64420reg.h	903;"	d
CHANNEL2_TX_CMD_STATUS	dev/mv64340reg.h	1017;"	d
CHANNEL2_TX_NEXT_POINTER	dev/gt64240reg.h	1170;"	d
CHANNEL2_TX_NEXT_POINTER	dev/gt64260reg.h	1161;"	d
CHANNEL2_TX_NEXT_POINTER	dev/gt64420reg.h	906;"	d
CHANNEL2_TX_NEXT_POINTER	dev/mv64340reg.h	1020;"	d
CHANNEL2_TX_PACKET_SIZE	dev/gt64240reg.h	1168;"	d
CHANNEL2_TX_PACKET_SIZE	dev/gt64260reg.h	1159;"	d
CHANNEL2_TX_PACKET_SIZE	dev/gt64420reg.h	904;"	d
CHANNEL2_TX_PACKET_SIZE	dev/mv64340reg.h	1018;"	d
CHANNEL3CONTROL	dev/gt64240reg.h	457;"	d
CHANNEL3CONTROL	dev/gt64260reg.h	448;"	d
CHANNEL3CONTROL	dev/gt64420reg.h	377;"	d
CHANNEL3CONTROL	dev/gt96132reg.h	204;"	d
CHANNEL3CONTROL	dev/mv64340reg.h	397;"	d
CHANNEL3CONTROL_HIGH	dev/gt64240reg.h	458;"	d
CHANNEL3CONTROL_HIGH	dev/gt64260reg.h	449;"	d
CHANNEL3CONTROL_HIGH	dev/gt64420reg.h	378;"	d
CHANNEL3CONTROL_HIGH	dev/mv64340reg.h	398;"	d
CHANNEL3CURRENT_DESCRIPTOR_POINTER	dev/gt64240reg.h	417;"	d
CHANNEL3CURRENT_DESCRIPTOR_POINTER	dev/gt64260reg.h	408;"	d
CHANNEL3CURRENT_DESCRIPTOR_POINTER	dev/gt64420reg.h	337;"	d
CHANNEL3CURRENT_DESCRIPTOR_POINTER	dev/gt96132reg.h	195;"	d
CHANNEL3CURRENT_DESCRIPTOR_POINTER	dev/mv64340reg.h	385;"	d
CHANNEL3NEXT_RECORD_POINTER	dev/gt64240reg.h	409;"	d
CHANNEL3NEXT_RECORD_POINTER	dev/gt64260reg.h	400;"	d
CHANNEL3NEXT_RECORD_POINTER	dev/gt64420reg.h	329;"	d
CHANNEL3NEXT_RECORD_POINTER	dev/gt96132reg.h	191;"	d
CHANNEL3NEXT_RECORD_POINTER	dev/mv64340reg.h	381;"	d
CHANNEL3_DMA_BYTE_COUNT	dev/gt64240reg.h	385;"	d
CHANNEL3_DMA_BYTE_COUNT	dev/gt64260reg.h	376;"	d
CHANNEL3_DMA_BYTE_COUNT	dev/gt64420reg.h	305;"	d
CHANNEL3_DMA_BYTE_COUNT	dev/gt96132reg.h	179;"	d
CHANNEL3_DMA_BYTE_COUNT	dev/mv64340reg.h	369;"	d
CHANNEL3_DMA_DESTINATION_ADDRESS	dev/gt64240reg.h	401;"	d
CHANNEL3_DMA_DESTINATION_ADDRESS	dev/gt64260reg.h	392;"	d
CHANNEL3_DMA_DESTINATION_ADDRESS	dev/gt64420reg.h	321;"	d
CHANNEL3_DMA_DESTINATION_ADDRESS	dev/gt96132reg.h	187;"	d
CHANNEL3_DMA_DESTINATION_ADDRESS	dev/mv64340reg.h	377;"	d
CHANNEL3_DMA_DESTINATION_HIGH_PCI_ADDRESS	dev/gt64240reg.h	433;"	d
CHANNEL3_DMA_DESTINATION_HIGH_PCI_ADDRESS	dev/gt64260reg.h	424;"	d
CHANNEL3_DMA_DESTINATION_HIGH_PCI_ADDRESS	dev/gt64420reg.h	353;"	d
CHANNEL3_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS	dev/gt64240reg.h	441;"	d
CHANNEL3_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS	dev/gt64260reg.h	432;"	d
CHANNEL3_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS	dev/gt64420reg.h	361;"	d
CHANNEL3_DMA_SOURCE_ADDRESS	dev/gt64240reg.h	393;"	d
CHANNEL3_DMA_SOURCE_ADDRESS	dev/gt64260reg.h	384;"	d
CHANNEL3_DMA_SOURCE_ADDRESS	dev/gt64420reg.h	313;"	d
CHANNEL3_DMA_SOURCE_ADDRESS	dev/gt96132reg.h	183;"	d
CHANNEL3_DMA_SOURCE_ADDRESS	dev/mv64340reg.h	373;"	d
CHANNEL3_DMA_SOURCE_HIGH_PCI_ADDRESS	dev/gt64240reg.h	425;"	d
CHANNEL3_DMA_SOURCE_HIGH_PCI_ADDRESS	dev/gt64260reg.h	416;"	d
CHANNEL3_DMA_SOURCE_HIGH_PCI_ADDRESS	dev/gt64420reg.h	345;"	d
CHANNEL4CONTROL	dev/gt64240reg.h	460;"	d
CHANNEL4CONTROL	dev/gt64260reg.h	451;"	d
CHANNEL4CONTROL	dev/gt64420reg.h	380;"	d
CHANNEL4CONTROL_HIGH	dev/gt64240reg.h	461;"	d
CHANNEL4CONTROL_HIGH	dev/gt64260reg.h	452;"	d
CHANNEL4CONTROL_HIGH	dev/gt64420reg.h	381;"	d
CHANNEL4CURRENT_DESCRIPTOR_POINTER	dev/gt64240reg.h	418;"	d
CHANNEL4CURRENT_DESCRIPTOR_POINTER	dev/gt64260reg.h	409;"	d
CHANNEL4CURRENT_DESCRIPTOR_POINTER	dev/gt64420reg.h	338;"	d
CHANNEL4NEXT_RECORD_POINTER	dev/gt64240reg.h	410;"	d
CHANNEL4NEXT_RECORD_POINTER	dev/gt64260reg.h	401;"	d
CHANNEL4NEXT_RECORD_POINTER	dev/gt64420reg.h	330;"	d
CHANNEL4_DMA_BYTE_COUNT	dev/gt64240reg.h	386;"	d
CHANNEL4_DMA_BYTE_COUNT	dev/gt64260reg.h	377;"	d
CHANNEL4_DMA_BYTE_COUNT	dev/gt64420reg.h	306;"	d
CHANNEL4_DMA_DESTINATION_ADDRESS	dev/gt64240reg.h	402;"	d
CHANNEL4_DMA_DESTINATION_ADDRESS	dev/gt64260reg.h	393;"	d
CHANNEL4_DMA_DESTINATION_ADDRESS	dev/gt64420reg.h	322;"	d
CHANNEL4_DMA_DESTINATION_HIGH_PCI_ADDRESS	dev/gt64240reg.h	434;"	d
CHANNEL4_DMA_DESTINATION_HIGH_PCI_ADDRESS	dev/gt64260reg.h	425;"	d
CHANNEL4_DMA_DESTINATION_HIGH_PCI_ADDRESS	dev/gt64420reg.h	354;"	d
CHANNEL4_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS	dev/gt64240reg.h	442;"	d
CHANNEL4_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS	dev/gt64260reg.h	433;"	d
CHANNEL4_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS	dev/gt64420reg.h	362;"	d
CHANNEL4_DMA_SOURCE_ADDRESS	dev/gt64240reg.h	394;"	d
CHANNEL4_DMA_SOURCE_ADDRESS	dev/gt64260reg.h	385;"	d
CHANNEL4_DMA_SOURCE_ADDRESS	dev/gt64420reg.h	314;"	d
CHANNEL4_DMA_SOURCE_HIGH_PCI_ADDRESS	dev/gt64240reg.h	426;"	d
CHANNEL4_DMA_SOURCE_HIGH_PCI_ADDRESS	dev/gt64260reg.h	417;"	d
CHANNEL4_DMA_SOURCE_HIGH_PCI_ADDRESS	dev/gt64420reg.h	346;"	d
CHANNEL5CONTROL	dev/gt64240reg.h	462;"	d
CHANNEL5CONTROL	dev/gt64260reg.h	453;"	d
CHANNEL5CONTROL	dev/gt64420reg.h	382;"	d
CHANNEL5CONTROL_HIGH	dev/gt64240reg.h	463;"	d
CHANNEL5CONTROL_HIGH	dev/gt64260reg.h	454;"	d
CHANNEL5CONTROL_HIGH	dev/gt64420reg.h	383;"	d
CHANNEL5CURRENT_DESCRIPTOR_POINTER	dev/gt64240reg.h	419;"	d
CHANNEL5CURRENT_DESCRIPTOR_POINTER	dev/gt64260reg.h	410;"	d
CHANNEL5CURRENT_DESCRIPTOR_POINTER	dev/gt64420reg.h	339;"	d
CHANNEL5NEXT_RECORD_POINTER	dev/gt64240reg.h	411;"	d
CHANNEL5NEXT_RECORD_POINTER	dev/gt64260reg.h	402;"	d
CHANNEL5NEXT_RECORD_POINTER	dev/gt64420reg.h	331;"	d
CHANNEL5_DMA_BYTE_COUNT	dev/gt64240reg.h	387;"	d
CHANNEL5_DMA_BYTE_COUNT	dev/gt64260reg.h	378;"	d
CHANNEL5_DMA_BYTE_COUNT	dev/gt64420reg.h	307;"	d
CHANNEL5_DMA_DESTINATION_ADDRESS	dev/gt64240reg.h	403;"	d
CHANNEL5_DMA_DESTINATION_ADDRESS	dev/gt64260reg.h	394;"	d
CHANNEL5_DMA_DESTINATION_ADDRESS	dev/gt64420reg.h	323;"	d
CHANNEL5_DMA_DESTINATION_HIGH_PCI_ADDRESS	dev/gt64240reg.h	435;"	d
CHANNEL5_DMA_DESTINATION_HIGH_PCI_ADDRESS	dev/gt64260reg.h	426;"	d
CHANNEL5_DMA_DESTINATION_HIGH_PCI_ADDRESS	dev/gt64420reg.h	355;"	d
CHANNEL5_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS	dev/gt64240reg.h	443;"	d
CHANNEL5_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS	dev/gt64260reg.h	434;"	d
CHANNEL5_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS	dev/gt64420reg.h	363;"	d
CHANNEL5_DMA_SOURCE_ADDRESS	dev/gt64240reg.h	395;"	d
CHANNEL5_DMA_SOURCE_ADDRESS	dev/gt64260reg.h	386;"	d
CHANNEL5_DMA_SOURCE_ADDRESS	dev/gt64420reg.h	315;"	d
CHANNEL5_DMA_SOURCE_HIGH_PCI_ADDRESS	dev/gt64240reg.h	427;"	d
CHANNEL5_DMA_SOURCE_HIGH_PCI_ADDRESS	dev/gt64260reg.h	418;"	d
CHANNEL5_DMA_SOURCE_HIGH_PCI_ADDRESS	dev/gt64420reg.h	347;"	d
CHANNEL6CONTROL	dev/gt64240reg.h	464;"	d
CHANNEL6CONTROL	dev/gt64260reg.h	455;"	d
CHANNEL6CONTROL	dev/gt64420reg.h	384;"	d
CHANNEL6CONTROL_HIGH	dev/gt64240reg.h	465;"	d
CHANNEL6CONTROL_HIGH	dev/gt64260reg.h	456;"	d
CHANNEL6CONTROL_HIGH	dev/gt64420reg.h	385;"	d
CHANNEL6CURRENT_DESCRIPTOR_POINTER	dev/gt64240reg.h	420;"	d
CHANNEL6CURRENT_DESCRIPTOR_POINTER	dev/gt64260reg.h	411;"	d
CHANNEL6CURRENT_DESCRIPTOR_POINTER	dev/gt64420reg.h	340;"	d
CHANNEL6NEXT_RECORD_POINTER	dev/gt64240reg.h	412;"	d
CHANNEL6NEXT_RECORD_POINTER	dev/gt64260reg.h	403;"	d
CHANNEL6NEXT_RECORD_POINTER	dev/gt64420reg.h	332;"	d
CHANNEL6_DMA_BYTE_COUNT	dev/gt64240reg.h	388;"	d
CHANNEL6_DMA_BYTE_COUNT	dev/gt64260reg.h	379;"	d
CHANNEL6_DMA_BYTE_COUNT	dev/gt64420reg.h	308;"	d
CHANNEL6_DMA_DESTINATION_ADDRESS	dev/gt64240reg.h	404;"	d
CHANNEL6_DMA_DESTINATION_ADDRESS	dev/gt64260reg.h	395;"	d
CHANNEL6_DMA_DESTINATION_ADDRESS	dev/gt64420reg.h	324;"	d
CHANNEL6_DMA_DESTINATION_HIGH_PCI_ADDRESS	dev/gt64240reg.h	436;"	d
CHANNEL6_DMA_DESTINATION_HIGH_PCI_ADDRESS	dev/gt64260reg.h	427;"	d
CHANNEL6_DMA_DESTINATION_HIGH_PCI_ADDRESS	dev/gt64420reg.h	356;"	d
CHANNEL6_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS	dev/gt64240reg.h	444;"	d
CHANNEL6_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS	dev/gt64260reg.h	435;"	d
CHANNEL6_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS	dev/gt64420reg.h	364;"	d
CHANNEL6_DMA_SOURCE_ADDRESS	dev/gt64240reg.h	396;"	d
CHANNEL6_DMA_SOURCE_ADDRESS	dev/gt64260reg.h	387;"	d
CHANNEL6_DMA_SOURCE_ADDRESS	dev/gt64420reg.h	316;"	d
CHANNEL6_DMA_SOURCE_HIGH_PCI_ADDRESS	dev/gt64240reg.h	428;"	d
CHANNEL6_DMA_SOURCE_HIGH_PCI_ADDRESS	dev/gt64260reg.h	419;"	d
CHANNEL6_DMA_SOURCE_HIGH_PCI_ADDRESS	dev/gt64420reg.h	348;"	d
CHANNEL7CONTROL	dev/gt64240reg.h	466;"	d
CHANNEL7CONTROL	dev/gt64260reg.h	457;"	d
CHANNEL7CONTROL	dev/gt64420reg.h	386;"	d
CHANNEL7CONTROL_HIGH	dev/gt64240reg.h	467;"	d
CHANNEL7CONTROL_HIGH	dev/gt64260reg.h	458;"	d
CHANNEL7CONTROL_HIGH	dev/gt64420reg.h	387;"	d
CHANNEL7CURRENT_DESCRIPTOR_POINTER	dev/gt64240reg.h	421;"	d
CHANNEL7CURRENT_DESCRIPTOR_POINTER	dev/gt64260reg.h	412;"	d
CHANNEL7CURRENT_DESCRIPTOR_POINTER	dev/gt64420reg.h	341;"	d
CHANNEL7NEXT_RECORD_POINTER	dev/gt64240reg.h	413;"	d
CHANNEL7NEXT_RECORD_POINTER	dev/gt64260reg.h	404;"	d
CHANNEL7NEXT_RECORD_POINTER	dev/gt64420reg.h	333;"	d
CHANNEL7_DMA_BYTE_COUNT	dev/gt64240reg.h	389;"	d
CHANNEL7_DMA_BYTE_COUNT	dev/gt64260reg.h	380;"	d
CHANNEL7_DMA_BYTE_COUNT	dev/gt64420reg.h	309;"	d
CHANNEL7_DMA_DESTINATION_ADDRESS	dev/gt64240reg.h	405;"	d
CHANNEL7_DMA_DESTINATION_ADDRESS	dev/gt64260reg.h	396;"	d
CHANNEL7_DMA_DESTINATION_ADDRESS	dev/gt64420reg.h	325;"	d
CHANNEL7_DMA_DESTINATION_HIGH_PCI_ADDRESS	dev/gt64240reg.h	437;"	d
CHANNEL7_DMA_DESTINATION_HIGH_PCI_ADDRESS	dev/gt64260reg.h	428;"	d
CHANNEL7_DMA_DESTINATION_HIGH_PCI_ADDRESS	dev/gt64420reg.h	357;"	d
CHANNEL7_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS	dev/gt64240reg.h	445;"	d
CHANNEL7_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS	dev/gt64260reg.h	436;"	d
CHANNEL7_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS	dev/gt64420reg.h	365;"	d
CHANNEL7_DMA_SOURCE_ADDRESS	dev/gt64240reg.h	397;"	d
CHANNEL7_DMA_SOURCE_ADDRESS	dev/gt64260reg.h	388;"	d
CHANNEL7_DMA_SOURCE_ADDRESS	dev/gt64420reg.h	317;"	d
CHANNEL7_DMA_SOURCE_HIGH_PCI_ADDRESS	dev/gt64240reg.h	429;"	d
CHANNEL7_DMA_SOURCE_HIGH_PCI_ADDRESS	dev/gt64260reg.h	420;"	d
CHANNEL7_DMA_SOURCE_HIGH_PCI_ADDRESS	dev/gt64420reg.h	349;"	d
CHKPNT_0MEM	include/progress.h	24;"	d
CHKPNT_AUTO	include/progress.h	27;"	d
CHKPNT_CACH	include/progress.h	13;"	d
CHKPNT_CREG	include/progress.h	19;"	d
CHKPNT_DATA	include/progress.h	15;"	d
CHKPNT_DBGI	include/progress.h	20;"	d
CHKPNT_DEMO	include/progress.h	34;"	d
CHKPNT_DEVI	include/progress.h	30;"	d
CHKPNT_ENVI	include/progress.h	28;"	d
CHKPNT_EXIT	include/progress.h	22;"	d
CHKPNT_FREQ	include/progress.h	23;"	d
CHKPNT_HAND	include/progress.h	17;"	d
CHKPNT_HSTI	include/progress.h	32;"	d
CHKPNT_ITLB	include/progress.h	14;"	d
CHKPNT_LOGO	include/progress.h	37;"	d
CHKPNT_MACH	include/progress.h	35;"	d
CHKPNT_MAIN	include/progress.h	21;"	d
CHKPNT_MAPV	include/progress.h	42;"	d
CHKPNT_NETI	include/progress.h	31;"	d
CHKPNT_PCID	include/progress.h	49;"	d
CHKPNT_PCIH	include/progress.h	45;"	d
CHKPNT_PCIR	include/progress.h	47;"	d
CHKPNT_PCIS	include/progress.h	46;"	d
CHKPNT_PCIW	include/progress.h	48;"	d
CHKPNT_PMON	include/progress.h	39;"	d
CHKPNT_PRAM	include/progress.h	40;"	d
CHKPNT_RDBG	include/progress.h	26;"	d
CHKPNT_RUN	include/progress.h	41;"	d
CHKPNT_SBDD	include/progress.h	29;"	d
CHKPNT_SBDE	include/progress.h	36;"	d
CHKPNT_SBDM	include/progress.h	18;"	d
CHKPNT_SBDR	include/progress.h	12;"	d
CHKPNT_SHRC	include/progress.h	38;"	d
CHKPNT_STDV	include/progress.h	43;"	d
CHKPNT_SYMI	include/progress.h	33;"	d
CHKPNT_WAIT	include/progress.h	25;"	d
CHKPNT_ZBSS	include/progress.h	16;"	d
CK_LALT	dev/key_defs.h	30;"	d
CK_LCTRL	dev/key_defs.h	31;"	d
CK_LSHIFT	dev/key_defs.h	29;"	d
CK_L_CTRL_ALT	dev/key_defs.h	35;"	d
CK_RALT	dev/key_defs.h	33;"	d
CK_RCTRL	dev/key_defs.h	34;"	d
CK_RSHIFT	dev/key_defs.h	32;"	d
CK_R_CTRL_ALT	dev/key_defs.h	36;"	d
CLK_TCK	include/time.h	101;"	d
CLOCKS_PER_SEC	include/time.h	69;"	d
CMD_ALIAS	include/pmon.h	126;"	d
CMD_HIDE	include/pmon.h	125;"	d
CMD_REPEAT	include/pmon.h	124;"	d
CNTRL	include/pmon.h	101;"	d
CNTRL	include/termio.h	93;"	d
COM1_BASE_ADDR	include/tgt/bonito.h	24;"	d
COM2_BASE_ADDR	include/tgt/bonito.h	25;"	d
COM3_BASE_ADDR	include/tgt/bonito.h	26;"	d
COMM_UNIT_ARBITER_CONFIGURATION_REGISTER	dev/gt64240reg.h	1210;"	d
COMM_UNIT_ARBITER_CONFIGURATION_REGISTER	dev/gt64260reg.h	1201;"	d
COMM_UNIT_ARBITER_CONFIGURATION_REGISTER	dev/gt64420reg.h	946;"	d
COMM_UNIT_ARBITER_CONFIGURATION_REGISTER	dev/mv64340reg.h	1060;"	d
COMM_UNIT_ARBITER_CONTROL	dev/gt64240reg.h	1021;"	d
COMM_UNIT_ARBITER_CONTROL	dev/gt64260reg.h	1012;"	d
COMM_UNIT_ARBITER_CONTROL	dev/mv64340reg.h	960;"	d
COMM_UNIT_ARBTR_CONFIG_REG	dev/gt96132reg.h	818;"	d
COMM_UNIT_ARBTR_EXT_REG	dev/gt96132reg.h	819;"	d
COMM_UNIT_CROSS_BAR_TIMEOUT	dev/gt64240reg.h	1022;"	d
COMM_UNIT_CROSS_BAR_TIMEOUT	dev/gt64260reg.h	1013;"	d
COMM_UNIT_CROSS_BAR_TIMEOUT	dev/mv64340reg.h	961;"	d
COMM_UNIT_ERROR_ADDRESS	dev/gt64240reg.h	1025;"	d
COMM_UNIT_ERROR_ADDRESS	dev/gt64260reg.h	1016;"	d
COMM_UNIT_ERROR_ADDRESS	dev/mv64340reg.h	964;"	d
COMM_UNIT_INTERRUPT_CAUSE	dev/gt64240reg.h	1023;"	d
COMM_UNIT_INTERRUPT_CAUSE	dev/gt64260reg.h	1014;"	d
COMM_UNIT_INTERRUPT_CAUSE	dev/mv64340reg.h	962;"	d
COMM_UNIT_INTERRUPT_MASK	dev/gt64240reg.h	1024;"	d
COMM_UNIT_INTERRUPT_MASK	dev/gt64260reg.h	1015;"	d
COMM_UNIT_INTERRUPT_MASK	dev/mv64340reg.h	963;"	d
COMPLETE	include/arpa/ftp.h	48;"	d
CONTINUE	include/arpa/ftp.h	49;"	d
CONV_BADBUFLEN	include/arpa/nameser.h	257;"	d
CONV_BADCKSUM	include/arpa/nameser.h	256;"	d
CONV_BADFMT	include/arpa/nameser.h	255;"	d
CONV_OVERFLOW	include/arpa/nameser.h	254;"	d
CONV_SUCCESS	include/arpa/nameser.h	253;"	d
CPC700_BBIT0	dev/cpc700.h	41;"	d
CPC700_BBIT1	dev/cpc700.h	42;"	d
CPC700_BBIT2	dev/cpc700.h	43;"	d
CPC700_BBIT3	dev/cpc700.h	44;"	d
CPC700_BBIT4	dev/cpc700.h	45;"	d
CPC700_BBIT5	dev/cpc700.h	46;"	d
CPC700_BBIT6	dev/cpc700.h	47;"	d
CPC700_BBIT7	dev/cpc700.h	48;"	d
CPC700_BEAR	dev/cpc700.h	121;"	d
CPC700_BESR	dev/cpc700.h	119;"	d
CPC700_BESRSET	dev/cpc700.h	120;"	d
CPC700_CPRCAPTEVNT	dev/cpc700.h	330;"	d
CPC700_CPRPLLACCESS	dev/cpc700.h	331;"	d
CPC700_CPRPLLTUNE	dev/cpc700.h	332;"	d
CPC700_CPRRESET	dev/cpc700.h	329;"	d
CPC700_CPRSTRAPREAD	dev/cpc700.h	333;"	d
CPC700_CPUERAD	dev/cpc700.h	108;"	d
CPC700_CPUERAT	dev/cpc700.h	109;"	d
CPC700_CRPRMCTRL	dev/cpc700.h	328;"	d
CPC700_DAM	dev/cpc700.h	156;"	d
CPC700_ECCCF	dev/cpc700.h	170;"	d
CPC700_ECCERR	dev/cpc700.h	171;"	d
CPC700_ERRDET1	dev/cpc700.h	106;"	d
CPC700_ERREN1	dev/cpc700.h	107;"	d
CPC700_FWEN	dev/cpc700.h	169;"	d
CPC700_GEAR	dev/cpc700.h	283;"	d
CPC700_GESRRD	dev/cpc700.h	281;"	d
CPC700_GESRWR	dev/cpc700.h	282;"	d
CPC700_GPTCAPT0	dev/cpc700.h	309;"	d
CPC700_GPTCAPT1	dev/cpc700.h	310;"	d
CPC700_GPTCAPT2	dev/cpc700.h	311;"	d
CPC700_GPTCAPT3	dev/cpc700.h	312;"	d
CPC700_GPTCAPT4	dev/cpc700.h	313;"	d
CPC700_GPTCE	dev/cpc700.h	302;"	d
CPC700_GPTCOMP0	dev/cpc700.h	314;"	d
CPC700_GPTCOMP1	dev/cpc700.h	315;"	d
CPC700_GPTCOMP2	dev/cpc700.h	316;"	d
CPC700_GPTCOMP3	dev/cpc700.h	317;"	d
CPC700_GPTCOMP4	dev/cpc700.h	318;"	d
CPC700_GPTEC	dev/cpc700.h	303;"	d
CPC700_GPTIE	dev/cpc700.h	305;"	d
CPC700_GPTIM	dev/cpc700.h	308;"	d
CPC700_GPTIS	dev/cpc700.h	306;"	d
CPC700_GPTISR	dev/cpc700.h	307;"	d
CPC700_GPTMASK0	dev/cpc700.h	319;"	d
CPC700_GPTMASK1	dev/cpc700.h	320;"	d
CPC700_GPTMASK2	dev/cpc700.h	321;"	d
CPC700_GPTMASK3	dev/cpc700.h	322;"	d
CPC700_GPTMASK4	dev/cpc700.h	323;"	d
CPC700_GPTSC	dev/cpc700.h	304;"	d
CPC700_GPTTBC	dev/cpc700.h	301;"	d
CPC700_IIC0	dev/cpc700.h	199;"	d
CPC700_IIC0_CLKDIV	dev/cpc700.h	211;"	d
CPC700_IIC0_CNTL	dev/cpc700.h	205;"	d
CPC700_IIC0_DIRECTCNTL	dev/cpc700.h	215;"	d
CPC700_IIC0_EXTSTS	dev/cpc700.h	208;"	d
CPC700_IIC0_HMADR	dev/cpc700.h	204;"	d
CPC700_IIC0_HSADR	dev/cpc700.h	210;"	d
CPC700_IIC0_INTRMASK	dev/cpc700.h	212;"	d
CPC700_IIC0_LMADR	dev/cpc700.h	203;"	d
CPC700_IIC0_LSADR	dev/cpc700.h	209;"	d
CPC700_IIC0_MDBUF	dev/cpc700.h	201;"	d
CPC700_IIC0_MDCNTL	dev/cpc700.h	206;"	d
CPC700_IIC0_SDBUF	dev/cpc700.h	202;"	d
CPC700_IIC0_STS	dev/cpc700.h	207;"	d
CPC700_IIC0_XFRCNT	dev/cpc700.h	213;"	d
CPC700_IIC0_XTCNTLSS	dev/cpc700.h	214;"	d
CPC700_IIC1	dev/cpc700.h	200;"	d
CPC700_IIC1_CLKDIV	dev/cpc700.h	226;"	d
CPC700_IIC1_CNTL	dev/cpc700.h	220;"	d
CPC700_IIC1_DIRECTCNTL	dev/cpc700.h	230;"	d
CPC700_IIC1_EXTSTS	dev/cpc700.h	223;"	d
CPC700_IIC1_HMADR	dev/cpc700.h	219;"	d
CPC700_IIC1_HSADR	dev/cpc700.h	225;"	d
CPC700_IIC1_INTRMASK	dev/cpc700.h	227;"	d
CPC700_IIC1_LMADR	dev/cpc700.h	218;"	d
CPC700_IIC1_LSADR	dev/cpc700.h	224;"	d
CPC700_IIC1_MDBUF	dev/cpc700.h	216;"	d
CPC700_IIC1_MDCNTL	dev/cpc700.h	221;"	d
CPC700_IIC1_SDBUF	dev/cpc700.h	217;"	d
CPC700_IIC1_STS	dev/cpc700.h	222;"	d
CPC700_IIC1_XFRCNT	dev/cpc700.h	228;"	d
CPC700_IIC1_XTCNTLSS	dev/cpc700.h	229;"	d
CPC700_IIC_CLKDIV	dev/cpc700.h	242;"	d
CPC700_IIC_CNTL	dev/cpc700.h	236;"	d
CPC700_IIC_EXTSTS	dev/cpc700.h	239;"	d
CPC700_IIC_HMADR	dev/cpc700.h	235;"	d
CPC700_IIC_HSADR	dev/cpc700.h	241;"	d
CPC700_IIC_INTRMSK	dev/cpc700.h	243;"	d
CPC700_IIC_LMADR	dev/cpc700.h	234;"	d
CPC700_IIC_LSADR	dev/cpc700.h	240;"	d
CPC700_IIC_MDBUF	dev/cpc700.h	232;"	d
CPC700_IIC_MDCNTL	dev/cpc700.h	237;"	d
CPC700_IIC_SDBUF	dev/cpc700.h	233;"	d
CPC700_IIC_STS	dev/cpc700.h	238;"	d
CPC700_IIC_XFRCNT	dev/cpc700.h	244;"	d
CPC700_IIC_XTCNTLSS	dev/cpc700.h	245;"	d
CPC700_IO_BASE	dev/cpc700.h	347;"	d
CPC700_IO_SIZE	dev/cpc700.h	348;"	d
CPC700_LBIT0	dev/cpc700.h	67;"	d
CPC700_LBIT1	dev/cpc700.h	68;"	d
CPC700_LBIT10	dev/cpc700.h	77;"	d
CPC700_LBIT11	dev/cpc700.h	78;"	d
CPC700_LBIT12	dev/cpc700.h	79;"	d
CPC700_LBIT13	dev/cpc700.h	80;"	d
CPC700_LBIT14	dev/cpc700.h	81;"	d
CPC700_LBIT15	dev/cpc700.h	82;"	d
CPC700_LBIT16	dev/cpc700.h	83;"	d
CPC700_LBIT17	dev/cpc700.h	84;"	d
CPC700_LBIT18	dev/cpc700.h	85;"	d
CPC700_LBIT19	dev/cpc700.h	86;"	d
CPC700_LBIT2	dev/cpc700.h	69;"	d
CPC700_LBIT20	dev/cpc700.h	87;"	d
CPC700_LBIT21	dev/cpc700.h	88;"	d
CPC700_LBIT22	dev/cpc700.h	89;"	d
CPC700_LBIT23	dev/cpc700.h	90;"	d
CPC700_LBIT24	dev/cpc700.h	91;"	d
CPC700_LBIT25	dev/cpc700.h	92;"	d
CPC700_LBIT26	dev/cpc700.h	93;"	d
CPC700_LBIT27	dev/cpc700.h	94;"	d
CPC700_LBIT28	dev/cpc700.h	95;"	d
CPC700_LBIT29	dev/cpc700.h	96;"	d
CPC700_LBIT3	dev/cpc700.h	70;"	d
CPC700_LBIT30	dev/cpc700.h	97;"	d
CPC700_LBIT31	dev/cpc700.h	98;"	d
CPC700_LBIT4	dev/cpc700.h	71;"	d
CPC700_LBIT5	dev/cpc700.h	72;"	d
CPC700_LBIT6	dev/cpc700.h	73;"	d
CPC700_LBIT7	dev/cpc700.h	74;"	d
CPC700_LBIT8	dev/cpc700.h	75;"	d
CPC700_LBIT9	dev/cpc700.h	76;"	d
CPC700_MB0EA	dev/cpc700.h	162;"	d
CPC700_MB0SA	dev/cpc700.h	157;"	d
CPC700_MB1EA	dev/cpc700.h	163;"	d
CPC700_MB1SA	dev/cpc700.h	158;"	d
CPC700_MB2EA	dev/cpc700.h	164;"	d
CPC700_MB2SA	dev/cpc700.h	159;"	d
CPC700_MB3EA	dev/cpc700.h	165;"	d
CPC700_MB3SA	dev/cpc700.h	160;"	d
CPC700_MB4EA	dev/cpc700.h	166;"	d
CPC700_MB4SA	dev/cpc700.h	161;"	d
CPC700_MBEN	dev/cpc700.h	152;"	d
CPC700_MCOPT1	dev/cpc700.h	151;"	d
CPC700_MEMCFGADDR	dev/cpc700.h	149;"	d
CPC700_MEMCFGDATA	dev/cpc700.h	150;"	d
CPC700_MEMTYPE	dev/cpc700.h	153;"	d
CPC700_MEM_RSETUP	dev/cpc700.h	364;"	d
CPC700_MEM_SETUP	dev/cpc700.h	356;"	d
CPC700_PACR	dev/cpc700.h	280;"	d
CPC700_PCIARBCNTL	dev/cpc700.h	137;"	d
CPC700_PCIBRDGOPT1	dev/cpc700.h	140;"	d
CPC700_PCIBRDGOPT2	dev/cpc700.h	144;"	d
CPC700_PCIBUSNUM	dev/cpc700.h	134;"	d
CPC700_PCICFGADDR	dev/cpc700.h	127;"	d
CPC700_PCICFGDATA	dev/cpc700.h	128;"	d
CPC700_PCIDSCCNT	dev/cpc700.h	136;"	d
CPC700_PCIERREN	dev/cpc700.h	138;"	d
CPC700_PCIERRSTS	dev/cpc700.h	139;"	d
CPC700_PCIPTM1BAR	dev/cpc700.h	132;"	d
CPC700_PCIPTM2BAR	dev/cpc700.h	133;"	d
CPC700_PCISUBBUSNUM	dev/cpc700.h	135;"	d
CPC700_PCI_CMD	dev/cpc700.h	129;"	d
CPC700_PCI_IO2_BASE	dev/cpc700.h	344;"	d
CPC700_PCI_IO2_REMAP	dev/cpc700.h	346;"	d
CPC700_PCI_IO2_SIZE	dev/cpc700.h	345;"	d
CPC700_PCI_IO_BASE	dev/cpc700.h	341;"	d
CPC700_PCI_IO_REMAP	dev/cpc700.h	343;"	d
CPC700_PCI_IO_SIZE	dev/cpc700.h	342;"	d
CPC700_PCI_MEM_BASE	dev/cpc700.h	339;"	d
CPC700_PCI_MEM_SIZE	dev/cpc700.h	340;"	d
CPC700_PCI_REV	dev/cpc700.h	131;"	d
CPC700_PCI_STAT	dev/cpc700.h	130;"	d
CPC700_PERRWR	dev/cpc700.h	279;"	d
CPC700_PESRRD	dev/cpc700.h	278;"	d
CPC700_PIFCFGADR	dev/cpc700.h	103;"	d
CPC700_PIFCFGDATA	dev/cpc700.h	104;"	d
CPC700_PLBMIFOPT	dev/cpc700.h	110;"	d
CPC700_PLBMTLEA1	dev/cpc700.h	112;"	d
CPC700_PLBMTLEA2	dev/cpc700.h	114;"	d
CPC700_PLBMTLEA3	dev/cpc700.h	116;"	d
CPC700_PLBMTLSA1	dev/cpc700.h	111;"	d
CPC700_PLBMTLSA2	dev/cpc700.h	113;"	d
CPC700_PLBMTLSA3	dev/cpc700.h	115;"	d
CPC700_PLBSNSEA0	dev/cpc700.h	118;"	d
CPC700_PLBSNSSA0	dev/cpc700.h	117;"	d
CPC700_PLBSWRINT	dev/cpc700.h	122;"	d
CPC700_PMM0ADDR	dev/cpc700.h	179;"	d
CPC700_PMM0HIGH	dev/cpc700.h	182;"	d
CPC700_PMM0LO	dev/cpc700.h	181;"	d
CPC700_PMM0MASK	dev/cpc700.h	180;"	d
CPC700_PMM1ADDR	dev/cpc700.h	183;"	d
CPC700_PMM1HIGH	dev/cpc700.h	186;"	d
CPC700_PMM1LO	dev/cpc700.h	185;"	d
CPC700_PMM1MASK	dev/cpc700.h	184;"	d
CPC700_PMM2ADDR	dev/cpc700.h	187;"	d
CPC700_PMM2HIGH	dev/cpc700.h	190;"	d
CPC700_PMM2LO	dev/cpc700.h	189;"	d
CPC700_PMM2MASK	dev/cpc700.h	188;"	d
CPC700_PRIOPT1	dev/cpc700.h	105;"	d
CPC700_PTM1ADDR	dev/cpc700.h	192;"	d
CPC700_PTM1SIZE	dev/cpc700.h	191;"	d
CPC700_PTM2ADDR	dev/cpc700.h	194;"	d
CPC700_PTM2SIZE	dev/cpc700.h	193;"	d
CPC700_RBW	dev/cpc700.h	168;"	d
CPC700_RPB0P	dev/cpc700.h	172;"	d
CPC700_RPB1P	dev/cpc700.h	173;"	d
CPC700_RPB2P	dev/cpc700.h	174;"	d
CPC700_RPB3P	dev/cpc700.h	175;"	d
CPC700_RPB4P	dev/cpc700.h	176;"	d
CPC700_RTR	dev/cpc700.h	155;"	d
CPC700_RWD	dev/cpc700.h	154;"	d
CPC700_SDTR1	dev/cpc700.h	167;"	d
CPC700_SEAR0	dev/cpc700.h	142;"	d
CPC700_SEAR1	dev/cpc700.h	143;"	d
CPC700_SESR	dev/cpc700.h	141;"	d
CPC700_UART0DLL	dev/cpc700.h	252;"	d
CPC700_UART0DLM	dev/cpc700.h	254;"	d
CPC700_UART0FCR	dev/cpc700.h	256;"	d
CPC700_UART0IER	dev/cpc700.h	253;"	d
CPC700_UART0IIR	dev/cpc700.h	255;"	d
CPC700_UART0LCR	dev/cpc700.h	257;"	d
CPC700_UART0LSR	dev/cpc700.h	259;"	d
CPC700_UART0MCR	dev/cpc700.h	258;"	d
CPC700_UART0MSSR	dev/cpc700.h	260;"	d
CPC700_UART0RBR	dev/cpc700.h	250;"	d
CPC700_UART0SCR	dev/cpc700.h	261;"	d
CPC700_UART0THR	dev/cpc700.h	251;"	d
CPC700_UART1DLL	dev/cpc700.h	264;"	d
CPC700_UART1DLM	dev/cpc700.h	266;"	d
CPC700_UART1FCR	dev/cpc700.h	268;"	d
CPC700_UART1IER	dev/cpc700.h	265;"	d
CPC700_UART1IIR	dev/cpc700.h	267;"	d
CPC700_UART1LCR	dev/cpc700.h	269;"	d
CPC700_UART1LSR	dev/cpc700.h	271;"	d
CPC700_UART1MCR	dev/cpc700.h	270;"	d
CPC700_UART1MSSR	dev/cpc700.h	272;"	d
CPC700_UART1RBR	dev/cpc700.h	262;"	d
CPC700_UART1SCR	dev/cpc700.h	273;"	d
CPC700_UART1THR	dev/cpc700.h	263;"	d
CPC700_UICCR	dev/cpc700.h	291;"	d
CPC700_UICER	dev/cpc700.h	290;"	d
CPC700_UICMSR	dev/cpc700.h	294;"	d
CPC700_UICPR	dev/cpc700.h	292;"	d
CPC700_UICSR	dev/cpc700.h	288;"	d
CPC700_UICSRS	dev/cpc700.h	289;"	d
CPC700_UICTR	dev/cpc700.h	293;"	d
CPC700_UICVCR	dev/cpc700.h	296;"	d
CPC700_UICVR	dev/cpc700.h	295;"	d
CPC700_WBIT0	dev/cpc700.h	50;"	d
CPC700_WBIT1	dev/cpc700.h	51;"	d
CPC700_WBIT10	dev/cpc700.h	60;"	d
CPC700_WBIT11	dev/cpc700.h	61;"	d
CPC700_WBIT12	dev/cpc700.h	62;"	d
CPC700_WBIT13	dev/cpc700.h	63;"	d
CPC700_WBIT14	dev/cpc700.h	64;"	d
CPC700_WBIT15	dev/cpc700.h	65;"	d
CPC700_WBIT2	dev/cpc700.h	52;"	d
CPC700_WBIT3	dev/cpc700.h	53;"	d
CPC700_WBIT4	dev/cpc700.h	54;"	d
CPC700_WBIT5	dev/cpc700.h	55;"	d
CPC700_WBIT6	dev/cpc700.h	56;"	d
CPC700_WBIT7	dev/cpc700.h	57;"	d
CPC700_WBIT8	dev/cpc700.h	58;"	d
CPC700_WBIT9	dev/cpc700.h	59;"	d
CPC710_ABCNTL	dev/cpc710.h	107;"	d
CPC710_ATAS	dev/cpc710.h	118;"	d
CPC710_AVDG	dev/cpc710.h	119;"	d
CPC710_BAR	dev/cpc710.h	138;"	d
CPC710_CNFR	dev/cpc710.h	98;"	d
CPC710_DCR	dev/cpc710.h	136;"	d
CPC710_DID	dev/cpc710.h	137;"	d
CPC710_ERRC	dev/cpc710.h	109;"	d
CPC710_GPDIR	dev/cpc710.h	115;"	d
CPC710_GPIN	dev/cpc710.h	116;"	d
CPC710_GPOUT	dev/cpc710.h	117;"	d
CPC710_MCCR	dev/cpc710.h	120;"	d
CPC710_MCER0	dev/cpc710.h	123;"	d
CPC710_MCER1	dev/cpc710.h	124;"	d
CPC710_MCER2	dev/cpc710.h	125;"	d
CPC710_MCER3	dev/cpc710.h	126;"	d
CPC710_MCER4	dev/cpc710.h	127;"	d
CPC710_MCER5	dev/cpc710.h	128;"	d
CPC710_MCER6	dev/cpc710.h	129;"	d
CPC710_MCER7	dev/cpc710.h	130;"	d
CPC710_MEAR	dev/cpc710.h	122;"	d
CPC710_MESR	dev/cpc710.h	121;"	d
CPC710_MPSR	dev/cpc710.h	105;"	d
CPC710_PCI32_CFGADDR	dev/cpc710.h	43;"	d
CPC710_PCI32_CFGDATA	dev/cpc710.h	44;"	d
CPC710_PCI64_CFGADDR	dev/cpc710.h	45;"	d
CPC710_PCI64_CFGDATA	dev/cpc710.h	46;"	d
CPC710_PCIENB	dev/cpc710.h	142;"	d
CPC710_PCI_BUS	dev/cpc710.h	51;"	d
CPC710_PCI_CMD	dev/cpc710.h	48;"	d
CPC710_PCI_INT	dev/cpc710.h	52;"	d
CPC710_PCI_REV	dev/cpc710.h	50;"	d
CPC710_PCI_STAT	dev/cpc710.h	49;"	d
CPC710_PGCHP	dev/cpc710.h	112;"	d
CPC710_PIDR	dev/cpc710.h	97;"	d
CPC710_RGBAN1	dev/cpc710.h	113;"	d
CPC710_RGBAN2	dev/cpc710.h	114;"	d
CPC710_RSTR	dev/cpc710.h	99;"	d
CPC710_SEAR	dev/cpc710.h	111;"	d
CPC710_SESR	dev/cpc710.h	110;"	d
CPC710_SIOC	dev/cpc710.h	106;"	d
CPC710_SIOR0	dev/cpc710.h	131;"	d
CPC710_SIOR1	dev/cpc710.h	132;"	d
CPC710_SPOR	dev/cpc710.h	100;"	d
CPC710_SRST	dev/cpc710.h	108;"	d
CPC710_UCTL	dev/cpc710.h	104;"	d
CPU40OHM	dev/mpc107reg.h	134;"	d
CPU_0_HIGH_DECODE_ADDRESS	dev/gt64240reg.h	191;"	d
CPU_0_HIGH_DECODE_ADDRESS	dev/gt64260reg.h	182;"	d
CPU_0_LOW_DECODE_ADDRESS	dev/gt64240reg.h	190;"	d
CPU_0_LOW_DECODE_ADDRESS	dev/gt64260reg.h	181;"	d
CPU_0_SYNC_BARRIER_TRIGGER	dev/mv64360reg.h	208;"	d
CPU_0_SYNC_BARRIER_VIRTUAL	dev/mv64360reg.h	209;"	d
CPU_1_HIGH_DECODE_ADDRESS	dev/gt64240reg.h	193;"	d
CPU_1_HIGH_DECODE_ADDRESS	dev/gt64260reg.h	184;"	d
CPU_1_LOW_DECODE_ADDRESS	dev/gt64240reg.h	192;"	d
CPU_1_LOW_DECODE_ADDRESS	dev/gt64260reg.h	183;"	d
CPU_1_SYNC_BARRIER_TRIGGER	dev/mv64360reg.h	210;"	d
CPU_1_SYNC_BARRIER_VIRTUAL	dev/mv64360reg.h	211;"	d
CPU_BASE_ADDRESS_ENABLE	dev/mv64340reg.h	146;"	d
CPU_BUS_ERROR_CAUSE	dev/gt64420reg.h	215;"	d
CPU_BUS_ERROR_HIGH_ADDRESS	dev/gt64240reg.h	264;"	d
CPU_BUS_ERROR_HIGH_ADDRESS	dev/gt64260reg.h	255;"	d
CPU_BUS_ERROR_HIGH_ADDRESS	dev/gt64420reg.h	211;"	d
CPU_BUS_ERROR_HIGH_ADDRESS	dev/gt96132reg.h	100;"	d
CPU_BUS_ERROR_HIGH_ADDRESS	dev/mv64340reg.h	242;"	d
CPU_BUS_ERROR_HIGH_DATA	dev/gt64240reg.h	266;"	d
CPU_BUS_ERROR_HIGH_DATA	dev/gt64260reg.h	257;"	d
CPU_BUS_ERROR_HIGH_DATA	dev/gt64420reg.h	213;"	d
CPU_BUS_ERROR_HIGH_DATA	dev/mv64340reg.h	244;"	d
CPU_BUS_ERROR_HIGH_PARITY	dev/gt64240reg.h	268;"	d
CPU_BUS_ERROR_HIGH_PARITY	dev/gt64260reg.h	259;"	d
CPU_BUS_ERROR_HIGH_PARITY	dev/mv64340reg.h	246;"	d
CPU_BUS_ERROR_LOW_ADDRESS	dev/gt64240reg.h	263;"	d
CPU_BUS_ERROR_LOW_ADDRESS	dev/gt64260reg.h	254;"	d
CPU_BUS_ERROR_LOW_ADDRESS	dev/gt64420reg.h	210;"	d
CPU_BUS_ERROR_LOW_ADDRESS	dev/gt96132reg.h	99;"	d
CPU_BUS_ERROR_LOW_ADDRESS	dev/mv64340reg.h	241;"	d
CPU_BUS_ERROR_LOW_DATA	dev/gt64240reg.h	265;"	d
CPU_BUS_ERROR_LOW_DATA	dev/gt64260reg.h	256;"	d
CPU_BUS_ERROR_LOW_DATA	dev/gt64420reg.h	212;"	d
CPU_BUS_ERROR_LOW_DATA	dev/mv64340reg.h	243;"	d
CPU_BUS_ERROR_LOW_PARITY	dev/gt64240reg.h	267;"	d
CPU_BUS_ERROR_LOW_PARITY	dev/gt64260reg.h	258;"	d
CPU_BUS_ERROR_LOW_PARITY	dev/mv64340reg.h	245;"	d
CPU_BUS_ERROR_MASK	dev/gt64240reg.h	269;"	d
CPU_BUS_ERROR_MASK	dev/gt64260reg.h	260;"	d
CPU_BUS_ERROR_MASK	dev/gt64420reg.h	216;"	d
CPU_BUS_ERROR_MASK	dev/mv64340reg.h	247;"	d
CPU_BUS_ERROR_PARITY	dev/gt64420reg.h	214;"	d
CPU_CONF	dev/gt64240reg.h	91;"	d
CPU_CONF	dev/gt64260reg.h	82;"	d
CPU_CONF	dev/gt64420reg.h	93;"	d
CPU_CONF	dev/gt96132reg.h	71;"	d
CPU_CONF	dev/mv64340reg.h	91;"	d
CPU_CONFIG	dev/gt64240reg.h	112;"	d
CPU_CONFIG	dev/gt64260reg.h	103;"	d
CPU_CONFIG	dev/gt64420reg.h	105;"	d
CPU_CONFIG	dev/mv64340reg.h	112;"	d
CPU_CONFIG	dev/mv64360reg.h	177;"	d
CPU_CROSS_BAR_CONTROL_HIGH	dev/mv64360reg.h	181;"	d
CPU_CROSS_BAR_CONTROL_LOW	dev/mv64360reg.h	180;"	d
CPU_CROSS_BAR_TIMEOUT	dev/mv64360reg.h	182;"	d
CPU_ERROR_ADDR_HIGH	dev/mv64360reg.h	232;"	d
CPU_ERROR_ADDR_LOW	dev/mv64360reg.h	231;"	d
CPU_ERROR_CAUSE	dev/mv64360reg.h	236;"	d
CPU_ERROR_DATA_HIGH	dev/mv64360reg.h	234;"	d
CPU_ERROR_DATA_LOW	dev/mv64360reg.h	233;"	d
CPU_ERROR_MASK	dev/mv64360reg.h	237;"	d
CPU_ERROR_PARITY	dev/mv64360reg.h	235;"	d
CPU_GE_HEADERS_RETARGET_BASE	dev/mv64360reg.h	169;"	d
CPU_GE_HEADERS_RETARGET_CONTROL	dev/mv64360reg.h	168;"	d
CPU_HIGH_INTERRUPT_MASK_REGISTER	dev/gt96132reg.h	278;"	d
CPU_HIGH_PROTECT_ADDRESS_0	dev/gt64240reg.h	229;"	d
CPU_HIGH_PROTECT_ADDRESS_0	dev/gt64260reg.h	220;"	d
CPU_HIGH_PROTECT_ADDRESS_0	dev/mv64340reg.h	229;"	d
CPU_HIGH_PROTECT_ADDRESS_1	dev/gt64240reg.h	231;"	d
CPU_HIGH_PROTECT_ADDRESS_1	dev/gt64260reg.h	222;"	d
CPU_HIGH_PROTECT_ADDRESS_1	dev/mv64340reg.h	231;"	d
CPU_HIGH_PROTECT_ADDRESS_2	dev/gt64240reg.h	233;"	d
CPU_HIGH_PROTECT_ADDRESS_2	dev/gt64260reg.h	224;"	d
CPU_HIGH_PROTECT_ADDRESS_2	dev/mv64340reg.h	233;"	d
CPU_HIGH_PROTECT_ADDRESS_3	dev/gt64240reg.h	235;"	d
CPU_HIGH_PROTECT_ADDRESS_3	dev/gt64260reg.h	226;"	d
CPU_HIGH_PROTECT_ADDRESS_3	dev/mv64340reg.h	235;"	d
CPU_HIGH_PROTECT_ADDRESS_4	dev/gt64240reg.h	237;"	d
CPU_HIGH_PROTECT_ADDRESS_4	dev/gt64260reg.h	228;"	d
CPU_HIGH_PROTECT_ADDRESS_5	dev/gt64240reg.h	239;"	d
CPU_HIGH_PROTECT_ADDRESS_5	dev/gt64260reg.h	230;"	d
CPU_HIGH_PROTECT_ADDRESS_6	dev/gt64240reg.h	241;"	d
CPU_HIGH_PROTECT_ADDRESS_6	dev/gt64260reg.h	232;"	d
CPU_HIGH_PROTECT_ADDRESS_7	dev/gt64240reg.h	243;"	d
CPU_HIGH_PROTECT_ADDRESS_7	dev/gt64260reg.h	234;"	d
CPU_IDMA_HEADERS_RETARGET_BASE	dev/mv64360reg.h	171;"	d
CPU_IDMA_HEADERS_RETARGET_CONTROL	dev/mv64360reg.h	170;"	d
CPU_INTERFACE_CONFIGURATION	dev/gt96132reg.h	70;"	d
CPU_INTERRUPT0_MASK_HIGH	dev/mv64360reg.h	1066;"	d
CPU_INTERRUPT0_MASK_LOW	dev/mv64360reg.h	1065;"	d
CPU_INTERRUPT0_SELECT_CAUSE	dev/mv64360reg.h	1067;"	d
CPU_INTERRUPT1_MASK_HIGH	dev/mv64360reg.h	1069;"	d
CPU_INTERRUPT1_MASK_LOW	dev/mv64360reg.h	1068;"	d
CPU_INTERRUPT1_SELECT_CAUSE	dev/mv64360reg.h	1070;"	d
CPU_INTERRUPT_MASK_REGISTER	dev/gt96132reg.h	277;"	d
CPU_INTERRUPT_MASK_REGISTER_HIGH	dev/gt64240reg.h	912;"	d
CPU_INTERRUPT_MASK_REGISTER_HIGH	dev/gt64260reg.h	903;"	d
CPU_INTERRUPT_MASK_REGISTER_HIGH	dev/gt64420reg.h	607;"	d
CPU_INTERRUPT_MASK_REGISTER_HIGH	dev/mv64340reg.h	736;"	d
CPU_INTERRUPT_MASK_REGISTER_LOW	dev/gt64240reg.h	911;"	d
CPU_INTERRUPT_MASK_REGISTER_LOW	dev/gt64260reg.h	902;"	d
CPU_INTERRUPT_MASK_REGISTER_LOW	dev/gt64420reg.h	606;"	d
CPU_INTERRUPT_MASK_REGISTER_LOW	dev/mv64340reg.h	735;"	d
CPU_INT_0_MASK	dev/gt64240reg.h	920;"	d
CPU_INT_0_MASK	dev/gt64260reg.h	911;"	d
CPU_INT_0_MASK	dev/mv64340reg.h	744;"	d
CPU_INT_1_MASK	dev/gt64240reg.h	921;"	d
CPU_INT_1_MASK	dev/gt64260reg.h	912;"	d
CPU_INT_1_MASK	dev/mv64340reg.h	745;"	d
CPU_INT_2_MASK	dev/gt64240reg.h	922;"	d
CPU_INT_2_MASK	dev/gt64260reg.h	913;"	d
CPU_INT_2_MASK	dev/mv64340reg.h	746;"	d
CPU_INT_3_MASK	dev/gt64240reg.h	923;"	d
CPU_INT_3_MASK	dev/gt64260reg.h	914;"	d
CPU_INT_3_MASK	dev/mv64340reg.h	747;"	d
CPU_LOW_PROTECT_ADDRESS_0	dev/gt64240reg.h	228;"	d
CPU_LOW_PROTECT_ADDRESS_0	dev/gt64260reg.h	219;"	d
CPU_LOW_PROTECT_ADDRESS_0	dev/mv64340reg.h	228;"	d
CPU_LOW_PROTECT_ADDRESS_1	dev/gt64240reg.h	230;"	d
CPU_LOW_PROTECT_ADDRESS_1	dev/gt64260reg.h	221;"	d
CPU_LOW_PROTECT_ADDRESS_1	dev/mv64340reg.h	230;"	d
CPU_LOW_PROTECT_ADDRESS_2	dev/gt64240reg.h	232;"	d
CPU_LOW_PROTECT_ADDRESS_2	dev/gt64260reg.h	223;"	d
CPU_LOW_PROTECT_ADDRESS_2	dev/mv64340reg.h	232;"	d
CPU_LOW_PROTECT_ADDRESS_3	dev/gt64240reg.h	234;"	d
CPU_LOW_PROTECT_ADDRESS_3	dev/gt64260reg.h	225;"	d
CPU_LOW_PROTECT_ADDRESS_3	dev/mv64340reg.h	234;"	d
CPU_LOW_PROTECT_ADDRESS_4	dev/gt64240reg.h	236;"	d
CPU_LOW_PROTECT_ADDRESS_4	dev/gt64260reg.h	227;"	d
CPU_LOW_PROTECT_ADDRESS_5	dev/gt64240reg.h	238;"	d
CPU_LOW_PROTECT_ADDRESS_5	dev/gt64260reg.h	229;"	d
CPU_LOW_PROTECT_ADDRESS_6	dev/gt64240reg.h	240;"	d
CPU_LOW_PROTECT_ADDRESS_6	dev/gt64260reg.h	231;"	d
CPU_LOW_PROTECT_ADDRESS_7	dev/gt64240reg.h	242;"	d
CPU_LOW_PROTECT_ADDRESS_7	dev/gt64260reg.h	233;"	d
CPU_MASTER_CONTROL	dev/mv64360reg.h	179;"	d
CPU_MODE	dev/mv64360reg.h	178;"	d
CPU_PCI_0_HEADERS_RETARGET_BASE	dev/mv64360reg.h	165;"	d
CPU_PCI_0_HEADERS_RETARGET_CONTROL	dev/mv64360reg.h	164;"	d
CPU_PCI_1_HEADERS_RETARGET_BASE	dev/mv64360reg.h	167;"	d
CPU_PCI_1_HEADERS_RETARGET_CONTROL	dev/mv64360reg.h	166;"	d
CPU_PROTECT_BASE_ADDRESS_0	dev/gt64420reg.h	195;"	d
CPU_PROTECT_BASE_ADDRESS_1	dev/gt64420reg.h	197;"	d
CPU_PROTECT_BASE_ADDRESS_2	dev/gt64420reg.h	199;"	d
CPU_PROTECT_BASE_ADDRESS_3	dev/gt64420reg.h	201;"	d
CPU_PROTECT_SIZE_0	dev/gt64420reg.h	196;"	d
CPU_PROTECT_SIZE_1	dev/gt64420reg.h	198;"	d
CPU_PROTECT_SIZE_2	dev/gt64420reg.h	200;"	d
CPU_PROTECT_SIZE_3	dev/gt64420reg.h	202;"	d
CPU_PROTECT_WINDOW_0_BASE_ADDR	dev/mv64360reg.h	217;"	d
CPU_PROTECT_WINDOW_0_SIZE	dev/mv64360reg.h	218;"	d
CPU_PROTECT_WINDOW_1_BASE_ADDR	dev/mv64360reg.h	219;"	d
CPU_PROTECT_WINDOW_1_SIZE	dev/mv64360reg.h	220;"	d
CPU_PROTECT_WINDOW_2_BASE_ADDR	dev/mv64360reg.h	221;"	d
CPU_PROTECT_WINDOW_2_SIZE	dev/mv64360reg.h	222;"	d
CPU_PROTECT_WINDOW_3_BASE_ADDR	dev/mv64360reg.h	223;"	d
CPU_PROTECT_WINDOW_3_SIZE	dev/mv64360reg.h	224;"	d
CPU_SELECT_CAUSE_REGISTER	dev/gt64240reg.h	913;"	d
CPU_SELECT_CAUSE_REGISTER	dev/gt64260reg.h	904;"	d
CPU_SELECT_CAUSE_REGISTER	dev/gt64420reg.h	608;"	d
CPU_SELECT_CAUSE_REGISTER	dev/mv64340reg.h	737;"	d
CPU_SYNC_BARIER_TRIGER_REGISTER	dev/gt64420reg.h	187;"	d
CPU_SYNC_BARIER_VIRTUAL_REGISTER	dev/gt64420reg.h	188;"	d
CS0_BASE	dev/gt64420reg.h	106;"	d
CS0_SIZE	dev/gt64420reg.h	107;"	d
CS1_BASE	dev/gt64420reg.h	110;"	d
CS1_SIZE	dev/gt64420reg.h	111;"	d
CS2_BASE	dev/gt64420reg.h	108;"	d
CS2_SIZE	dev/gt64420reg.h	109;"	d
CS3_BASE	dev/gt64420reg.h	112;"	d
CS3_SIZE	dev/gt64420reg.h	113;"	d
CS_0_BASE_ADDR	dev/mv64360reg.h	83;"	d
CS_0_BASE_ADDRESS	dev/gt64420reg.h	135;"	d
CS_0_BASE_ADDRESS	dev/mv64340reg.h	159;"	d
CS_0_HIGH_DECODE_ADDRESS	dev/gt64240reg.h	156;"	d
CS_0_HIGH_DECODE_ADDRESS	dev/gt64260reg.h	147;"	d
CS_0_HIGH_DECODE_ADDRESS	dev/gt96132reg.h	127;"	d
CS_0_LOW_DECODE_ADDRESS	dev/gt64240reg.h	155;"	d
CS_0_LOW_DECODE_ADDRESS	dev/gt64260reg.h	146;"	d
CS_0_LOW_DECODE_ADDRESS	dev/gt96132reg.h	126;"	d
CS_0_SIZE	dev/gt64420reg.h	136;"	d
CS_0_SIZE	dev/mv64340reg.h	160;"	d
CS_0_SIZE	dev/mv64360reg.h	84;"	d
CS_1_BASE_ADDR	dev/mv64360reg.h	85;"	d
CS_1_BASE_ADDRESS	dev/gt64420reg.h	137;"	d
CS_1_BASE_ADDRESS	dev/mv64340reg.h	161;"	d
CS_1_HIGH_DECODE_ADDRESS	dev/gt64240reg.h	158;"	d
CS_1_HIGH_DECODE_ADDRESS	dev/gt64260reg.h	149;"	d
CS_1_HIGH_DECODE_ADDRESS	dev/gt96132reg.h	129;"	d
CS_1_LOW_DECODE_ADDRESS	dev/gt64240reg.h	157;"	d
CS_1_LOW_DECODE_ADDRESS	dev/gt64260reg.h	148;"	d
CS_1_LOW_DECODE_ADDRESS	dev/gt96132reg.h	128;"	d
CS_1_SIZE	dev/gt64420reg.h	138;"	d
CS_1_SIZE	dev/mv64340reg.h	162;"	d
CS_1_SIZE	dev/mv64360reg.h	86;"	d
CS_2_0_ADDRESS_REMAP	dev/gt96132reg.h	105;"	d
CS_2_0_HIGH_DECODE_ADDRESS	dev/gt96132reg.h	83;"	d
CS_2_0_LOW_DECODE_ADDRESS	dev/gt96132reg.h	82;"	d
CS_2_BASE_ADDR	dev/mv64360reg.h	87;"	d
CS_2_BASE_ADDRESS	dev/gt64420reg.h	139;"	d
CS_2_BASE_ADDRESS	dev/mv64340reg.h	163;"	d
CS_2_HIGH_DECODE_ADDRESS	dev/gt64240reg.h	160;"	d
CS_2_HIGH_DECODE_ADDRESS	dev/gt64260reg.h	151;"	d
CS_2_HIGH_DECODE_ADDRESS	dev/gt96132reg.h	131;"	d
CS_2_LOW_DECODE_ADDRESS	dev/gt64240reg.h	159;"	d
CS_2_LOW_DECODE_ADDRESS	dev/gt64260reg.h	150;"	d
CS_2_LOW_DECODE_ADDRESS	dev/gt96132reg.h	130;"	d
CS_2_SIZE	dev/gt64420reg.h	140;"	d
CS_2_SIZE	dev/mv64340reg.h	164;"	d
CS_2_SIZE	dev/mv64360reg.h	88;"	d
CS_3_BASE_ADDR	dev/mv64360reg.h	89;"	d
CS_3_BASE_ADDRESS	dev/gt64420reg.h	141;"	d
CS_3_BASE_ADDRESS	dev/mv64340reg.h	165;"	d
CS_3_BOOTCS_ADDRESS_REMAP	dev/gt96132reg.h	106;"	d
CS_3_BOOTCS_HIGH_DECODE_ADDRESS	dev/gt96132reg.h	85;"	d
CS_3_BOOTCS_LOW_DECODE_ADDRESS	dev/gt96132reg.h	84;"	d
CS_3_HIGH_DECODE_ADDRESS	dev/gt64240reg.h	162;"	d
CS_3_HIGH_DECODE_ADDRESS	dev/gt64260reg.h	153;"	d
CS_3_HIGH_DECODE_ADDRESS	dev/gt96132reg.h	133;"	d
CS_3_LOW_DECODE_ADDRESS	dev/gt64240reg.h	161;"	d
CS_3_LOW_DECODE_ADDRESS	dev/gt64260reg.h	152;"	d
CS_3_LOW_DECODE_ADDRESS	dev/gt96132reg.h	132;"	d
CS_3_SIZE	dev/gt64420reg.h	142;"	d
CS_3_SIZE	dev/mv64340reg.h	166;"	d
CS_3_SIZE	dev/mv64360reg.h	90;"	d
CTR	include/powerpc.h	39;"	d
CUNIT_ADDRESS	dev/gt64240reg.h	1031;"	d
CUNIT_ADDRESS	dev/gt64260reg.h	1022;"	d
CUNIT_ADDRESS	dev/mv64340reg.h	970;"	d
CUNIT_ARBITER_CONTROL_REG	dev/mv64360reg.h	860;"	d
CUNIT_BASE_ADDR_ENABLE_REG	dev/mv64360reg.h	847;"	d
CUNIT_BASE_ADDR_REG0	dev/mv64360reg.h	837;"	d
CUNIT_BASE_ADDR_REG1	dev/mv64360reg.h	838;"	d
CUNIT_BASE_ADDR_REG2	dev/mv64360reg.h	839;"	d
CUNIT_BASE_ADDR_REG3	dev/mv64360reg.h	840;"	d
CUNIT_COMMAND_AND_ID	dev/gt64240reg.h	1032;"	d
CUNIT_COMMAND_AND_ID	dev/gt64260reg.h	1023;"	d
CUNIT_COMMAND_AND_ID	dev/mv64340reg.h	971;"	d
CUNIT_CONFIG_REG	dev/mv64360reg.h	861;"	d
CUNIT_CRROSBAR_TIMEOUT_REG	dev/mv64360reg.h	862;"	d
CUNIT_DEBUG_HIGH	dev/mv64360reg.h	867;"	d
CUNIT_DEBUG_LOW	dev/mv64360reg.h	866;"	d
CUNIT_ERROR_ADDR	dev/mv64360reg.h	856;"	d
CUNIT_HIGH_ADDR_REMAP_REG0	dev/mv64360reg.h	845;"	d
CUNIT_HIGH_ADDR_REMAP_REG1	dev/mv64360reg.h	846;"	d
CUNIT_INTERNAL_SPACE_BASE_ADDR_REG	dev/mv64360reg.h	850;"	d
CUNIT_INTERRUPT_CAUSE_REG	dev/mv64360reg.h	854;"	d
CUNIT_INTERRUPT_MASK_REG	dev/mv64360reg.h	855;"	d
CUNIT_MMASK	dev/mv64360reg.h	868;"	d
CUNIT_READ_DATA_HIGH	dev/gt64240reg.h	1037;"	d
CUNIT_READ_DATA_HIGH	dev/gt64260reg.h	1028;"	d
CUNIT_READ_DATA_HIGH	dev/mv64340reg.h	976;"	d
CUNIT_READ_DATA_LOW	dev/gt64240reg.h	1036;"	d
CUNIT_READ_DATA_LOW	dev/gt64260reg.h	1027;"	d
CUNIT_READ_DATA_LOW	dev/mv64340reg.h	975;"	d
CUNIT_READ_ID	dev/gt64240reg.h	1038;"	d
CUNIT_READ_ID	dev/gt64260reg.h	1029;"	d
CUNIT_READ_ID	dev/mv64340reg.h	977;"	d
CUNIT_SIZE0	dev/mv64360reg.h	841;"	d
CUNIT_SIZE1	dev/mv64360reg.h	842;"	d
CUNIT_SIZE2	dev/mv64360reg.h	843;"	d
CUNIT_SIZE3	dev/mv64360reg.h	844;"	d
CUNIT_WRITE_BYTE_ENABLE	dev/gt64240reg.h	1035;"	d
CUNIT_WRITE_BYTE_ENABLE	dev/gt64260reg.h	1026;"	d
CUNIT_WRITE_BYTE_ENABLE	dev/mv64340reg.h	974;"	d
CUNIT_WRITE_DATA_HIGH	dev/gt64240reg.h	1034;"	d
CUNIT_WRITE_DATA_HIGH	dev/gt64260reg.h	1025;"	d
CUNIT_WRITE_DATA_HIGH	dev/mv64340reg.h	973;"	d
CUNIT_WRITE_DATA_LOW	dev/gt64240reg.h	1033;"	d
CUNIT_WRITE_DATA_LOW	dev/gt64260reg.h	1024;"	d
CUNIT_WRITE_DATA_LOW	dev/mv64340reg.h	972;"	d
C_ANY	include/arpa/nameser.h	206;"	d
C_CHAOS	include/arpa/nameser.h	203;"	d
C_HS	include/arpa/nameser.h	204;"	d
C_IN	include/arpa/nameser.h	202;"	d
Cmd	include/pmon.h	/^typedef struct Cmd {$/;"	s
Cmd	include/pmon.h	/^} Cmd;$/;"	t	typeref:struct:Cmd
CmdList	cmdtable.c	/^const Cmd *CmdList[100];$/;"	v
Cmds	cmd_env.c	/^static const Cmd Cmds[] = {$/;"	v	file:
Cmds	help.c	/^static const Cmd Cmds[] = {$/;"	v	file:
Cmds	main.c	/^static const Cmd Cmds[] = {$/;"	v	file:
Cmds	program.c	/^static const Cmd Cmds[] = {$/;"	v	file:
ConfigEntry	include/termio.h	/^typedef struct ConfigEntry {$/;"	s
ConfigEntry	include/termio.h	/^} ConfigEntry;$/;"	t	typeref:struct:ConfigEntry
ConvAddr	dev/flash.c	118;"	d	file:
ConvAddr1	dev/flash_st.c	83;"	d	file:
ConvAddr2	dev/flash_st.c	89;"	d	file:
DATA	include/arpa/tftp.h	52;"	d
DBAT_SETUP	include/powerpc.h	147;"	d
DCACHE	include/pmon.h	56;"	d
DEBUG_PORT_MULTIPLEX	dev/gt64240reg.h	1249;"	d
DEBUG_PORT_MULTIPLEX	dev/gt64260reg.h	1240;"	d
DEBUG_PORT_MULTIPLEX	dev/gt64420reg.h	985;"	d
DEF_MEM_LEVEL	include/linux/zutil.h	40;"	d
DEF_MEM_LEVEL	include/linux/zutil.h	42;"	d
DEF_WBITS	include/linux/zutil.h	35;"	d
DEVCS_0_BASE_ADDRESS	dev/gt64420reg.h	145;"	d
DEVCS_0_SIZE	dev/gt64420reg.h	146;"	d
DEVCS_1_BASE_ADDRESS	dev/gt64420reg.h	147;"	d
DEVCS_1_SIZE	dev/gt64420reg.h	148;"	d
DEVCS_2_BASE_ADDRESS	dev/gt64420reg.h	149;"	d
DEVCS_2_SIZE	dev/gt64420reg.h	150;"	d
DEVCS_3_BASE_ADDRESS	dev/gt64420reg.h	151;"	d
DEVCS_3_SIZE	dev/gt64420reg.h	152;"	d
DEVICE_BANK0PARAMETERS	dev/gt64240reg.h	360;"	d
DEVICE_BANK0PARAMETERS	dev/gt64260reg.h	351;"	d
DEVICE_BANK0PARAMETERS	dev/gt64420reg.h	280;"	d
DEVICE_BANK0PARAMETERS	dev/gt96132reg.h	160;"	d
DEVICE_BANK0PARAMETERS	dev/mv64340reg.h	344;"	d
DEVICE_BANK0_PARAMETERS	dev/mv64360reg.h	320;"	d
DEVICE_BANK1PARAMETERS	dev/gt64240reg.h	361;"	d
DEVICE_BANK1PARAMETERS	dev/gt64260reg.h	352;"	d
DEVICE_BANK1PARAMETERS	dev/gt64420reg.h	281;"	d
DEVICE_BANK1PARAMETERS	dev/gt96132reg.h	161;"	d
DEVICE_BANK1PARAMETERS	dev/mv64340reg.h	345;"	d
DEVICE_BANK1_PARAMETERS	dev/mv64360reg.h	321;"	d
DEVICE_BANK2PARAMETERS	dev/gt64240reg.h	362;"	d
DEVICE_BANK2PARAMETERS	dev/gt64260reg.h	353;"	d
DEVICE_BANK2PARAMETERS	dev/gt64420reg.h	282;"	d
DEVICE_BANK2PARAMETERS	dev/gt96132reg.h	162;"	d
DEVICE_BANK2PARAMETERS	dev/mv64340reg.h	346;"	d
DEVICE_BANK2_PARAMETERS	dev/mv64360reg.h	322;"	d
DEVICE_BANK3PARAMETERS	dev/gt64240reg.h	363;"	d
DEVICE_BANK3PARAMETERS	dev/gt64260reg.h	354;"	d
DEVICE_BANK3PARAMETERS	dev/gt64420reg.h	283;"	d
DEVICE_BANK3PARAMETERS	dev/gt96132reg.h	163;"	d
DEVICE_BANK3PARAMETERS	dev/mv64340reg.h	347;"	d
DEVICE_BANK3_PARAMETERS	dev/mv64360reg.h	323;"	d
DEVICE_BOOT_BANK_PARAMETERS	dev/gt64240reg.h	364;"	d
DEVICE_BOOT_BANK_PARAMETERS	dev/gt64260reg.h	355;"	d
DEVICE_BOOT_BANK_PARAMETERS	dev/gt64420reg.h	284;"	d
DEVICE_BOOT_BANK_PARAMETERS	dev/gt96132reg.h	164;"	d
DEVICE_BOOT_BANK_PARAMETERS	dev/mv64340reg.h	348;"	d
DEVICE_BOOT_BANK_PARAMETERS	dev/mv64360reg.h	324;"	d
DEVICE_CONTROL	dev/gt64240reg.h	365;"	d
DEVICE_CONTROL	dev/gt64260reg.h	356;"	d
DEVICE_CONTROL	dev/gt64420reg.h	285;"	d
DEVICE_CONTROL	dev/mv64340reg.h	349;"	d
DEVICE_CROSS_BAR_CONTROL_HIGH	dev/gt64240reg.h	367;"	d
DEVICE_CROSS_BAR_CONTROL_HIGH	dev/gt64260reg.h	358;"	d
DEVICE_CROSS_BAR_CONTROL_HIGH	dev/gt64420reg.h	287;"	d
DEVICE_CROSS_BAR_CONTROL_HIGH	dev/mv64340reg.h	351;"	d
DEVICE_CROSS_BAR_CONTROL_LOW	dev/gt64240reg.h	366;"	d
DEVICE_CROSS_BAR_CONTROL_LOW	dev/gt64260reg.h	357;"	d
DEVICE_CROSS_BAR_CONTROL_LOW	dev/gt64420reg.h	286;"	d
DEVICE_CROSS_BAR_CONTROL_LOW	dev/mv64340reg.h	350;"	d
DEVICE_CROSS_BAR_TIMEOUT	dev/gt64240reg.h	368;"	d
DEVICE_CROSS_BAR_TIMEOUT	dev/gt64260reg.h	359;"	d
DEVICE_CROSS_BAR_TIMEOUT	dev/gt64420reg.h	288;"	d
DEVICE_CROSS_BAR_TIMEOUT	dev/mv64340reg.h	352;"	d
DEVICE_DEBUG_HIGH	dev/mv64360reg.h	345;"	d
DEVICE_DEBUG_LOW	dev/mv64360reg.h	344;"	d
DEVICE_ERROR_ADDR	dev/mv64360reg.h	336;"	d
DEVICE_ERROR_ADDRESS	dev/gt64240reg.h	376;"	d
DEVICE_ERROR_ADDRESS	dev/gt64260reg.h	367;"	d
DEVICE_ERROR_ADDRESS	dev/gt64420reg.h	296;"	d
DEVICE_ERROR_ADDRESS	dev/mv64340reg.h	360;"	d
DEVICE_ERROR_DATA	dev/mv64360reg.h	337;"	d
DEVICE_ERROR_PARITY	dev/mv64360reg.h	338;"	d
DEVICE_INTERFACE_CONTROL	dev/mv64360reg.h	325;"	d
DEVICE_INTERFACE_CROSS_BAR_CONTROL_HIGH	dev/mv64360reg.h	327;"	d
DEVICE_INTERFACE_CROSS_BAR_CONTROL_LOW	dev/mv64360reg.h	326;"	d
DEVICE_INTERFACE_CROSS_BAR_TIMEOUT	dev/mv64360reg.h	328;"	d
DEVICE_INTERRUPT_CAUSE	dev/gt64240reg.h	374;"	d
DEVICE_INTERRUPT_CAUSE	dev/gt64260reg.h	365;"	d
DEVICE_INTERRUPT_CAUSE	dev/gt64420reg.h	294;"	d
DEVICE_INTERRUPT_CAUSE	dev/mv64340reg.h	358;"	d
DEVICE_INTERRUPT_CAUSE	dev/mv64360reg.h	334;"	d
DEVICE_INTERRUPT_MASK	dev/gt64240reg.h	375;"	d
DEVICE_INTERRUPT_MASK	dev/gt64260reg.h	366;"	d
DEVICE_INTERRUPT_MASK	dev/gt64420reg.h	295;"	d
DEVICE_INTERRUPT_MASK	dev/mv64340reg.h	359;"	d
DEVICE_INTERRUPT_MASK	dev/mv64360reg.h	335;"	d
DEV_CS0_BASE_ADDR	dev/mv64360reg.h	94;"	d
DEV_CS0_SIZE	dev/mv64360reg.h	95;"	d
DEV_CS1_BASE_ADDR	dev/mv64360reg.h	96;"	d
DEV_CS1_SIZE	dev/mv64360reg.h	97;"	d
DEV_CS2_BASE_ADDR	dev/mv64360reg.h	98;"	d
DEV_CS2_SIZE	dev/mv64360reg.h	99;"	d
DEV_CS3_BASE_ADDR	dev/mv64360reg.h	100;"	d
DEV_CS3_SIZE	dev/mv64360reg.h	101;"	d
DEV_MAX	include/termio.h	82;"	d
DFCDL_CONFIG0	dev/mv64360reg.h	298;"	d
DFCDL_CONFIG1	dev/mv64360reg.h	299;"	d
DFCDL_CONFIGURATION0	dev/mv64340reg.h	292;"	d
DFCDL_CONFIGURATION1	dev/mv64340reg.h	293;"	d
DFCDL_PROBE	dev/mv64340reg.h	296;"	d
DFCL_PROBE	dev/mv64360reg.h	306;"	d
DLL_READ	dev/mv64360reg.h	301;"	d
DLL_WRITE	dev/mv64360reg.h	300;"	d
DM	include/arpa/telnet.h	58;"	d
DMA_ARBITER_CONTROL	dev/mv64360reg.h	991;"	d
DMA_BASE_ADDR_ENABLE_REG	dev/mv64360reg.h	986;"	d
DMA_BASE_ADDR_REG0	dev/mv64360reg.h	959;"	d
DMA_BASE_ADDR_REG1	dev/mv64360reg.h	960;"	d
DMA_BASE_ADDR_REG2	dev/mv64360reg.h	961;"	d
DMA_BASE_ADDR_REG3	dev/mv64360reg.h	962;"	d
DMA_BASE_ADDR_REG4	dev/mv64360reg.h	963;"	d
DMA_BASE_ADDR_REG5	dev/mv64360reg.h	964;"	d
DMA_BASE_ADDR_REG6	dev/mv64360reg.h	965;"	d
DMA_BASE_ADDR_REG7	dev/mv64360reg.h	966;"	d
DMA_CHANNEL0_ACCESS_PROTECTION_REG	dev/mv64360reg.h	987;"	d
DMA_CHANNEL0_BYTE_COUNT	dev/mv64360reg.h	936;"	d
DMA_CHANNEL0_CONTROL	dev/mv64360reg.h	922;"	d
DMA_CHANNEL0_CONTROL_HIGH	dev/mv64360reg.h	923;"	d
DMA_CHANNEL0_CURRENT_DESCRIPTOR_POINTER	dev/mv64360reg.h	952;"	d
DMA_CHANNEL0_DESTINATION_ADDR	dev/mv64360reg.h	944;"	d
DMA_CHANNEL0_NEXT_DESCRIPTOR_POINTER	dev/mv64360reg.h	948;"	d
DMA_CHANNEL0_SOURCE_ADDR	dev/mv64360reg.h	940;"	d
DMA_CHANNEL1_ACCESS_PROTECTION_REG	dev/mv64360reg.h	988;"	d
DMA_CHANNEL1_BYTE_COUNT	dev/mv64360reg.h	937;"	d
DMA_CHANNEL1_CONTROL	dev/mv64360reg.h	924;"	d
DMA_CHANNEL1_CONTROL_HIGH	dev/mv64360reg.h	925;"	d
DMA_CHANNEL1_CURRENT_DESCRIPTOR_POINTER	dev/mv64360reg.h	953;"	d
DMA_CHANNEL1_DESTINATION_ADDR	dev/mv64360reg.h	945;"	d
DMA_CHANNEL1_NEXT_DESCRIPTOR_POINTER	dev/mv64360reg.h	949;"	d
DMA_CHANNEL1_SOURCE_ADDR	dev/mv64360reg.h	941;"	d
DMA_CHANNEL2_ACCESS_PROTECTION_REG	dev/mv64360reg.h	989;"	d
DMA_CHANNEL2_BYTE_COUNT	dev/mv64360reg.h	938;"	d
DMA_CHANNEL2_CONTROL	dev/mv64360reg.h	926;"	d
DMA_CHANNEL2_CONTROL_HIGH	dev/mv64360reg.h	927;"	d
DMA_CHANNEL2_CURRENT_DESCRIPTOR_POINTER	dev/mv64360reg.h	954;"	d
DMA_CHANNEL2_DESTINATION_ADDR	dev/mv64360reg.h	946;"	d
DMA_CHANNEL2_NEXT_DESCRIPTOR_POINTER	dev/mv64360reg.h	950;"	d
DMA_CHANNEL2_SOURCE_ADDR	dev/mv64360reg.h	942;"	d
DMA_CHANNEL3_ACCESS_PROTECTION_REG	dev/mv64360reg.h	990;"	d
DMA_CHANNEL3_BYTE_COUNT	dev/mv64360reg.h	939;"	d
DMA_CHANNEL3_CONTROL	dev/mv64360reg.h	928;"	d
DMA_CHANNEL3_CONTROL_HIGH	dev/mv64360reg.h	929;"	d
DMA_CHANNEL3_CURRENT_DESCRIPTOR_POINTER	dev/mv64360reg.h	955;"	d
DMA_CHANNEL3_DESTINATION_ADDR	dev/mv64360reg.h	947;"	d
DMA_CHANNEL3_NEXT_DESCRIPTOR_POINTER	dev/mv64360reg.h	951;"	d
DMA_CHANNEL3_SOURCE_ADDR	dev/mv64360reg.h	943;"	d
DMA_CROSS_BAR_TIMEOUT	dev/mv64360reg.h	992;"	d
DMA_DEBUG_HIGH	dev/mv64360reg.h	1009;"	d
DMA_DEBUG_LOW	dev/mv64360reg.h	1008;"	d
DMA_ERROR_ADDR	dev/mv64360reg.h	1003;"	d
DMA_ERROR_SELECT	dev/mv64360reg.h	1004;"	d
DMA_HEADERS_RETARGET_BASE	dev/mv64360reg.h	997;"	d
DMA_HEADERS_RETARGET_CONTROL	dev/mv64360reg.h	996;"	d
DMA_HIGH_ADDR_REMAP_REG0	dev/mv64360reg.h	982;"	d
DMA_HIGH_ADDR_REMAP_REG1	dev/mv64360reg.h	983;"	d
DMA_HIGH_ADDR_REMAP_REG2	dev/mv64360reg.h	984;"	d
DMA_HIGH_ADDR_REMAP_REG3	dev/mv64360reg.h	985;"	d
DMA_INTERRUPT_CAUSE_MASK	dev/mv64360reg.h	1002;"	d
DMA_INTERRUPT_CAUSE_REG	dev/mv64360reg.h	1001;"	d
DMA_SIZE_REG0	dev/mv64360reg.h	970;"	d
DMA_SIZE_REG1	dev/mv64360reg.h	971;"	d
DMA_SIZE_REG2	dev/mv64360reg.h	972;"	d
DMA_SIZE_REG3	dev/mv64360reg.h	973;"	d
DMA_SIZE_REG4	dev/mv64360reg.h	974;"	d
DMA_SIZE_REG5	dev/mv64360reg.h	975;"	d
DMA_SIZE_REG6	dev/mv64360reg.h	976;"	d
DMA_SIZE_REG7	dev/mv64360reg.h	977;"	d
DMA_SPARE	dev/mv64360reg.h	1010;"	d
DMA_X0_ADDRESS	dev/gt64240reg.h	496;"	d
DMA_X0_ADDRESS	dev/gt64260reg.h	487;"	d
DMA_X0_ADDRESS	dev/gt64420reg.h	416;"	d
DMA_X0_ADDRESS	dev/mv64340reg.h	426;"	d
DMA_X0_COMMAND_AND_ID	dev/gt64240reg.h	497;"	d
DMA_X0_COMMAND_AND_ID	dev/gt64260reg.h	488;"	d
DMA_X0_COMMAND_AND_ID	dev/gt64420reg.h	417;"	d
DMA_X0_COMMAND_AND_ID	dev/mv64340reg.h	427;"	d
DMA_X0_READ_DATA_HIGH	dev/gt64240reg.h	502;"	d
DMA_X0_READ_DATA_HIGH	dev/gt64260reg.h	493;"	d
DMA_X0_READ_DATA_HIGH	dev/gt64420reg.h	422;"	d
DMA_X0_READ_DATA_HIGH	dev/mv64340reg.h	432;"	d
DMA_X0_READ_DATA_LOW	dev/gt64240reg.h	501;"	d
DMA_X0_READ_DATA_LOW	dev/gt64260reg.h	492;"	d
DMA_X0_READ_DATA_LOW	dev/gt64420reg.h	421;"	d
DMA_X0_READ_DATA_LOW	dev/mv64340reg.h	431;"	d
DMA_X0_READ_ID	dev/gt64240reg.h	503;"	d
DMA_X0_READ_ID	dev/gt64260reg.h	494;"	d
DMA_X0_READ_ID	dev/gt64420reg.h	423;"	d
DMA_X0_READ_ID	dev/mv64340reg.h	433;"	d
DMA_X0_WRITE_BYTE_ENABLE	dev/gt64240reg.h	500;"	d
DMA_X0_WRITE_BYTE_ENABLE	dev/gt64260reg.h	491;"	d
DMA_X0_WRITE_BYTE_ENABLE	dev/gt64420reg.h	420;"	d
DMA_X0_WRITE_BYTE_ENABLE	dev/mv64340reg.h	430;"	d
DMA_X0_WRITE_DATA_HIGH	dev/gt64240reg.h	499;"	d
DMA_X0_WRITE_DATA_HIGH	dev/gt64260reg.h	490;"	d
DMA_X0_WRITE_DATA_HIGH	dev/gt64420reg.h	419;"	d
DMA_X0_WRITE_DATA_HIGH	dev/mv64340reg.h	429;"	d
DMA_X0_WRITE_DATA_LOW	dev/gt64240reg.h	498;"	d
DMA_X0_WRITE_DATA_LOW	dev/gt64260reg.h	489;"	d
DMA_X0_WRITE_DATA_LOW	dev/gt64420reg.h	418;"	d
DMA_X0_WRITE_DATA_LOW	dev/mv64340reg.h	428;"	d
DMA_X1_ADDRESS	dev/gt64240reg.h	504;"	d
DMA_X1_ADDRESS	dev/gt64260reg.h	495;"	d
DMA_X1_ADDRESS	dev/gt64420reg.h	424;"	d
DMA_X1_ADDRESS	dev/mv64340reg.h	434;"	d
DMA_X1_COMMAND_AND_ID	dev/gt64240reg.h	505;"	d
DMA_X1_COMMAND_AND_ID	dev/gt64260reg.h	496;"	d
DMA_X1_COMMAND_AND_ID	dev/gt64420reg.h	425;"	d
DMA_X1_COMMAND_AND_ID	dev/mv64340reg.h	435;"	d
DMA_X1_READ_DATA_HIGH	dev/gt64240reg.h	510;"	d
DMA_X1_READ_DATA_HIGH	dev/gt64260reg.h	501;"	d
DMA_X1_READ_DATA_HIGH	dev/gt64420reg.h	430;"	d
DMA_X1_READ_DATA_HIGH	dev/mv64340reg.h	440;"	d
DMA_X1_READ_DATA_LOW	dev/gt64240reg.h	509;"	d
DMA_X1_READ_DATA_LOW	dev/gt64260reg.h	500;"	d
DMA_X1_READ_DATA_LOW	dev/gt64420reg.h	429;"	d
DMA_X1_READ_DATA_LOW	dev/mv64340reg.h	439;"	d
DMA_X1_READ_ID	dev/gt64240reg.h	511;"	d
DMA_X1_READ_ID	dev/gt64260reg.h	502;"	d
DMA_X1_READ_ID	dev/gt64420reg.h	431;"	d
DMA_X1_READ_ID	dev/mv64340reg.h	441;"	d
DMA_X1_WRITE_BYTE_ENABLE	dev/gt64240reg.h	508;"	d
DMA_X1_WRITE_BYTE_ENABLE	dev/gt64260reg.h	499;"	d
DMA_X1_WRITE_BYTE_ENABLE	dev/gt64420reg.h	428;"	d
DMA_X1_WRITE_BYTE_ENABLE	dev/mv64340reg.h	438;"	d
DMA_X1_WRITE_DATA_HIGH	dev/gt64240reg.h	507;"	d
DMA_X1_WRITE_DATA_HIGH	dev/gt64260reg.h	498;"	d
DMA_X1_WRITE_DATA_HIGH	dev/gt64420reg.h	427;"	d
DMA_X1_WRITE_DATA_HIGH	dev/mv64340reg.h	437;"	d
DMA_X1_WRITE_DATA_LOW	dev/gt64240reg.h	506;"	d
DMA_X1_WRITE_DATA_LOW	dev/gt64260reg.h	497;"	d
DMA_X1_WRITE_DATA_LOW	dev/gt64420reg.h	426;"	d
DMA_X1_WRITE_DATA_LOW	dev/mv64340reg.h	436;"	d
DO	include/arpa/telnet.h	47;"	d
DO1	include/linux/zutil.h	77;"	d
DO16	include/linux/zutil.h	81;"	d
DO2	include/linux/zutil.h	78;"	d
DO4	include/linux/zutil.h	79;"	d
DO8	include/linux/zutil.h	80;"	d
DONT	include/arpa/telnet.h	46;"	d
DS_CTLA_DV0	dev/mc146818reg.h	64;"	d
DS_CTLA_DV1	dev/mc146818reg.h	65;"	d
DS_CTLA_DV2	dev/mc146818reg.h	66;"	d
DS_CTLA_RS0	dev/mc146818reg.h	60;"	d
DS_CTLA_RS1	dev/mc146818reg.h	61;"	d
DS_CTLA_RS2	dev/mc146818reg.h	62;"	d
DS_CTLA_RS3	dev/mc146818reg.h	63;"	d
DS_CTLA_UIP	dev/mc146818reg.h	67;"	d
DS_CTLB_24	dev/mc146818reg.h	70;"	d
DS_CTLB_AIE	dev/mc146818reg.h	74;"	d
DS_CTLB_DM	dev/mc146818reg.h	71;"	d
DS_CTLB_DSE	dev/mc146818reg.h	69;"	d
DS_CTLB_PIE	dev/mc146818reg.h	75;"	d
DS_CTLB_SET	dev/mc146818reg.h	76;"	d
DS_CTLB_SQWE	dev/mc146818reg.h	72;"	d
DS_CTLB_UIE	dev/mc146818reg.h	73;"	d
DS_EXRAM_DATA	dev/mc146818reg.h	83;"	d
DS_EXRAM_LSB	dev/mc146818reg.h	81;"	d
DS_EXRAM_MSB	dev/mc146818reg.h	82;"	d
DS_MONTH_E32K	dev/mc146818reg.h	57;"	d
DS_MONTH_EOSC	dev/mc146818reg.h	58;"	d
DS_REG_AHOUR	dev/mc146818reg.h	45;"	d
DS_REG_AMIN	dev/mc146818reg.h	43;"	d
DS_REG_ASEC	dev/mc146818reg.h	41;"	d
DS_REG_CTLA	dev/mc146818reg.h	51;"	d
DS_REG_CTLB	dev/mc146818reg.h	52;"	d
DS_REG_CTLC	dev/mc146818reg.h	53;"	d
DS_REG_CTLD	dev/mc146818reg.h	54;"	d
DS_REG_DATE	dev/mc146818reg.h	47;"	d
DS_REG_HOUR	dev/mc146818reg.h	44;"	d
DS_REG_MIN	dev/mc146818reg.h	42;"	d
DS_REG_MONTH	dev/mc146818reg.h	48;"	d
DS_REG_SEC	dev/mc146818reg.h	40;"	d
DS_REG_WDAY	dev/mc146818reg.h	46;"	d
DS_REG_YEAR	dev/mc146818reg.h	49;"	d
DUNIT_CONTROL_HIGH	dev/mv64340reg.h	278;"	d
DUNIT_CONTROL_LOW	dev/mv64340reg.h	277;"	d
DUNIT_DEBUG_HIGH	dev/mv64360reg.h	313;"	d
DUNIT_DEBUG_LOW	dev/mv64360reg.h	312;"	d
DUNIT_MMASK	dev/mv64360reg.h	314;"	d
DYN_TREES	include/linux/zutil.h	48;"	d
D_UNIT_CONTROL_HIGH	dev/mv64360reg.h	268;"	d
D_UNIT_CONTROL_LOW	dev/mv64360reg.h	267;"	d
Demo	include/pmon.h	/^typedef struct Demo {$/;"	s
Demo	include/pmon.h	/^} Demo;$/;"	t	typeref:struct:Demo
DevEntry	include/termio.h	/^typedef struct DevEntry {$/;"	s
DevEntry	include/termio.h	/^} DevEntry;$/;"	t	typeref:struct:DevEntry
DiskFile	include/diskfs.h	/^typedef struct DiskFile {$/;"	s
DiskFile	include/diskfs.h	/^} DiskFile;$/;"	t	typeref:struct:DiskFile
DiskFileSystem	include/diskfs.h	/^typedef struct DiskFileSystem {$/;"	s
DiskFileSystem	include/diskfs.h	/^} DiskFileSystem;$/;"	t	typeref:struct:DiskFileSystem
E0_BREAK	dev/kbd.c	23;"	d	file:
E0_DEL	dev/kbd.c	33;"	d	file:
E0_DO	dev/kbd.c	41;"	d	file:
E0_DOWN	dev/kbd.c	30;"	d	file:
E0_END	dev/kbd.c	29;"	d	file:
E0_F13	dev/kbd.c	38;"	d	file:
E0_F14	dev/kbd.c	39;"	d	file:
E0_F17	dev/kbd.c	42;"	d	file:
E0_HELP	dev/kbd.c	40;"	d	file:
E0_HOME	dev/kbd.c	24;"	d	file:
E0_INS	dev/kbd.c	32;"	d	file:
E0_KPENTER	dev/kbd.c	18;"	d	file:
E0_KPMINPLUS	dev/kbd.c	43;"	d	file:
E0_KPSLASH	dev/kbd.c	20;"	d	file:
E0_LEFT	dev/kbd.c	27;"	d	file:
E0_MACRO	dev/kbd.c	36;"	d	file:
E0_MSLW	dev/kbd.c	55;"	d	file:
E0_MSRW	dev/kbd.c	56;"	d	file:
E0_MSTM	dev/kbd.c	57;"	d	file:
E0_OK	dev/kbd.c	48;"	d	file:
E0_PGDN	dev/kbd.c	31;"	d	file:
E0_PGUP	dev/kbd.c	26;"	d	file:
E0_PRSCR	dev/kbd.c	21;"	d	file:
E0_RALT	dev/kbd.c	22;"	d	file:
E0_RCTRL	dev/kbd.c	19;"	d	file:
E0_RIGHT	dev/kbd.c	28;"	d	file:
E0_UP	dev/kbd.c	25;"	d	file:
E2BIG	include/errno.h	61;"	d
EACCES	include/errno.h	68;"	d
EACCESS	include/arpa/tftp.h	76;"	d
EADDRINUSE	include/errno.h	115;"	d
EADDRNOTAVAIL	include/errno.h	116;"	d
EAFNOSUPPORT	include/errno.h	114;"	d
EAGAIN	include/errno.h	98;"	d
EAI_ADDRFAMILY	include/netdb.h	163;"	d
EAI_AGAIN	include/netdb.h	157;"	d
EAI_BADFLAGS	include/netdb.h	155;"	d
EAI_FAIL	include/netdb.h	158;"	d
EAI_FAMILY	include/netdb.h	160;"	d
EAI_MEMORY	include/netdb.h	164;"	d
EAI_NODATA	include/netdb.h	159;"	d
EAI_NONAME	include/netdb.h	156;"	d
EAI_SERVICE	include/netdb.h	162;"	d
EAI_SOCKTYPE	include/netdb.h	161;"	d
EAI_SYSTEM	include/netdb.h	165;"	d
EALREADY	include/errno.h	102;"	d
EANCHOR	lib.c	108;"	d	file:
EAUTH	include/errno.h	164;"	d
EBADCOOKIE	include/linux/errno.h	17;"	d
EBADF	include/errno.h	63;"	d
EBADHANDLE	include/linux/errno.h	15;"	d
EBADID	include/arpa/tftp.h	79;"	d
EBADOP	include/arpa/tftp.h	78;"	d
EBADRPC	include/errno.h	152;"	d
EBADTYPE	include/linux/errno.h	21;"	d
EBUSY	include/errno.h	73;"	d
EC	include/arpa/telnet.h	53;"	d
ECHILD	include/errno.h	64;"	d
ECHO	include/termio.h	33;"	d
ECHOE	include/termio.h	34;"	d
ECONNABORTED	include/errno.h	122;"	d
ECONNREFUSED	include/errno.h	130;"	d
ECONNRESET	include/errno.h	123;"	d
EDEADLK	include/errno.h	65;"	d
EDESTADDRREQ	include/errno.h	106;"	d
EDOM	include/errno.h	94;"	d
EDQUOT	include/errno.h	147;"	d
EEXIST	include/errno.h	74;"	d
EEXISTS	include/arpa/tftp.h	80;"	d
EFAULT	include/errno.h	69;"	d
EFBIG	include/errno.h	86;"	d
EFTYPE	include/errno.h	163;"	d
EHOSTDOWN	include/errno.h	138;"	d
EHOSTUNREACH	include/errno.h	139;"	d
EINPROGRESS	include/errno.h	101;"	d
EINTR	include/errno.h	58;"	d
EINVAL	include/errno.h	79;"	d
EIO	include/errno.h	59;"	d
EIPSEC	include/errno.h	166;"	d
EISCONN	include/errno.h	125;"	d
EISDIR	include/errno.h	78;"	d
EJUKEBOX	include/linux/errno.h	22;"	d
EJUSTRETURN	include/errno.h	173;"	d
EL	include/arpa/telnet.h	52;"	d
ELAN520_MMCR	dev/elan520.h	37;"	d
ELAN520_MMCR_ADDDECCTL	dev/elan520.h	92;"	d
ELAN520_MMCR_ARBPCICTL	dev/elan520.h	87;"	d
ELAN520_MMCR_BOOTCSCTL	dev/elan520.h	67;"	d
ELAN520_MMCR_CLKSEL	dev/elan520.h	133;"	d
ELAN520_MMCR_CPUCTL	dev/elan520.h	43;"	d
ELAN520_MMCR_CSPFS	dev/elan520.h	132;"	d
ELAN520_MMCR_DBCTL	dev/elan520.h	62;"	d
ELAN520_MMCR_DMABCINTMAP	dev/elan520.h	217;"	d
ELAN520_MMCR_DRCBENDADR	dev/elan520.h	51;"	d
ELAN520_MMCR_DRCCFG	dev/elan520.h	50;"	d
ELAN520_MMCR_DRCCTL	dev/elan520.h	48;"	d
ELAN520_MMCR_DRCTMCTL	dev/elan520.h	49;"	d
ELAN520_MMCR_DSCTL	dev/elan520.h	134;"	d
ELAN520_MMCR_ECCCKBPOS	dev/elan520.h	54;"	d
ELAN520_MMCR_ECCCKTEST	dev/elan520.h	55;"	d
ELAN520_MMCR_ECCCTL	dev/elan520.h	52;"	d
ELAN520_MMCR_ECCMAP	dev/elan520.h	204;"	d
ELAN520_MMCR_ECCMBADD	dev/elan520.h	57;"	d
ELAN520_MMCR_ECCSBADD	dev/elan520.h	56;"	d
ELAN520_MMCR_ECCSTA	dev/elan520.h	53;"	d
ELAN520_MMCR_FERRMAP	dev/elan520.h	223;"	d
ELAN520_MMCR_GP0IMAP	dev/elan520.h	224;"	d
ELAN520_MMCR_GP10IMAP	dev/elan520.h	234;"	d
ELAN520_MMCR_GP1IMAP	dev/elan520.h	225;"	d
ELAN520_MMCR_GP2IMAP	dev/elan520.h	226;"	d
ELAN520_MMCR_GP3IMAP	dev/elan520.h	227;"	d
ELAN520_MMCR_GP4IMAP	dev/elan520.h	228;"	d
ELAN520_MMCR_GP5IMAP	dev/elan520.h	229;"	d
ELAN520_MMCR_GP6IMAP	dev/elan520.h	230;"	d
ELAN520_MMCR_GP7IMAP	dev/elan520.h	231;"	d
ELAN520_MMCR_GP8IMAP	dev/elan520.h	232;"	d
ELAN520_MMCR_GP9IMAP	dev/elan520.h	233;"	d
ELAN520_MMCR_GPALEOFF	dev/elan520.h	125;"	d
ELAN520_MMCR_GPALEW	dev/elan520.h	124;"	d
ELAN520_MMCR_GPCSDW	dev/elan520.h	115;"	d
ELAN520_MMCR_GPCSOFF	dev/elan520.h	119;"	d
ELAN520_MMCR_GPCSPW	dev/elan520.h	118;"	d
ELAN520_MMCR_GPCSQUAL	dev/elan520.h	116;"	d
ELAN520_MMCR_GPCSRT	dev/elan520.h	117;"	d
ELAN520_MMCR_GPDMABCCTL	dev/elan520.h	262;"	d
ELAN520_MMCR_GPDMABCSTA	dev/elan520.h	263;"	d
ELAN520_MMCR_GPDMABCVAL	dev/elan520.h	265;"	d
ELAN520_MMCR_GPDMABSINTENB	dev/elan520.h	264;"	d
ELAN520_MMCR_GPDMACTL	dev/elan520.h	246;"	d
ELAN520_MMCR_GPDMAEXTCHMAPA	dev/elan520.h	248;"	d
ELAN520_MMCR_GPDMAEXTCHMAPB	dev/elan520.h	249;"	d
ELAN520_MMCR_GPDMAEXTPG0	dev/elan520.h	250;"	d
ELAN520_MMCR_GPDMAEXTPG1	dev/elan520.h	251;"	d
ELAN520_MMCR_GPDMAEXTPG2	dev/elan520.h	252;"	d
ELAN520_MMCR_GPDMAEXTPG3	dev/elan520.h	253;"	d
ELAN520_MMCR_GPDMAEXTPG4	dev/elan520.h	254;"	d
ELAN520_MMCR_GPDMAEXTPG5	dev/elan520.h	255;"	d
ELAN520_MMCR_GPDMAEXTPG6	dev/elan520.h	256;"	d
ELAN520_MMCR_GPDMAEXTPG7	dev/elan520.h	257;"	d
ELAN520_MMCR_GPDMAEXTTC3	dev/elan520.h	258;"	d
ELAN520_MMCR_GPDMAEXTTC5	dev/elan520.h	259;"	d
ELAN520_MMCR_GPDMAEXTTC6	dev/elan520.h	260;"	d
ELAN520_MMCR_GPDMAEXTTC7	dev/elan520.h	261;"	d
ELAN520_MMCR_GPDMAMMIO	dev/elan520.h	247;"	d
ELAN520_MMCR_GPDMANXTADDH3	dev/elan520.h	267;"	d
ELAN520_MMCR_GPDMANXTADDH5	dev/elan520.h	269;"	d
ELAN520_MMCR_GPDMANXTADDH6	dev/elan520.h	271;"	d
ELAN520_MMCR_GPDMANXTADDH7	dev/elan520.h	273;"	d
ELAN520_MMCR_GPDMANXTADDL3	dev/elan520.h	266;"	d
ELAN520_MMCR_GPDMANXTADDL5	dev/elan520.h	268;"	d
ELAN520_MMCR_GPDMANXTADDL6	dev/elan520.h	270;"	d
ELAN520_MMCR_GPDMANXTADDL7	dev/elan520.h	272;"	d
ELAN520_MMCR_GPDMANXTTCH3	dev/elan520.h	275;"	d
ELAN520_MMCR_GPDMANXTTCH5	dev/elan520.h	277;"	d
ELAN520_MMCR_GPDMANXTTCH6	dev/elan520.h	279;"	d
ELAN520_MMCR_GPDMANXTTCH7	dev/elan520.h	281;"	d
ELAN520_MMCR_GPDMANXTTCL3	dev/elan520.h	274;"	d
ELAN520_MMCR_GPDMANXTTCL5	dev/elan520.h	276;"	d
ELAN520_MMCR_GPDMANXTTCL6	dev/elan520.h	278;"	d
ELAN520_MMCR_GPDMANXTTCL7	dev/elan520.h	280;"	d
ELAN520_MMCR_GPECHO	dev/elan520.h	114;"	d
ELAN520_MMCR_GPRDOFF	dev/elan520.h	121;"	d
ELAN520_MMCR_GPRDW	dev/elan520.h	120;"	d
ELAN520_MMCR_GPTMR0CNT	dev/elan520.h	156;"	d
ELAN520_MMCR_GPTMR0CTL	dev/elan520.h	155;"	d
ELAN520_MMCR_GPTMR0MAP	dev/elan520.h	205;"	d
ELAN520_MMCR_GPTMR0MAXCMPA	dev/elan520.h	157;"	d
ELAN520_MMCR_GPTMR0MAXCMPB	dev/elan520.h	158;"	d
ELAN520_MMCR_GPTMR1CNT	dev/elan520.h	160;"	d
ELAN520_MMCR_GPTMR1CTL	dev/elan520.h	159;"	d
ELAN520_MMCR_GPTMR1MAP	dev/elan520.h	206;"	d
ELAN520_MMCR_GPTMR1MAXCMPA	dev/elan520.h	161;"	d
ELAN520_MMCR_GPTMR1MAXCMPB	dev/elan520.h	162;"	d
ELAN520_MMCR_GPTMR2CNT	dev/elan520.h	164;"	d
ELAN520_MMCR_GPTMR2CTL	dev/elan520.h	163;"	d
ELAN520_MMCR_GPTMR2MAP	dev/elan520.h	207;"	d
ELAN520_MMCR_GPTMR2MAXCMPA	dev/elan520.h	165;"	d
ELAN520_MMCR_GPTMRSTA	dev/elan520.h	154;"	d
ELAN520_MMCR_GPWROFF	dev/elan520.h	123;"	d
ELAN520_MMCR_GPWRW	dev/elan520.h	122;"	d
ELAN520_MMCR_HBCTL	dev/elan520.h	74;"	d
ELAN520_MMCR_HBMSTIRQCTL	dev/elan520.h	77;"	d
ELAN520_MMCR_HBMSTIRQSTA	dev/elan520.h	78;"	d
ELAN520_MMCR_HBTGTIRQCTL	dev/elan520.h	75;"	d
ELAN520_MMCR_HBTGTIRQSTA	dev/elan520.h	76;"	d
ELAN520_MMCR_ICEMAP	dev/elan520.h	222;"	d
ELAN520_MMCR_INTPINPOL	dev/elan520.h	202;"	d
ELAN520_MMCR_MPICMODE	dev/elan520.h	197;"	d
ELAN520_MMCR_MSTINTADD	dev/elan520.h	79;"	d
ELAN520_MMCR_PAR0	dev/elan520.h	94;"	d
ELAN520_MMCR_PAR1	dev/elan520.h	95;"	d
ELAN520_MMCR_PAR10	dev/elan520.h	104;"	d
ELAN520_MMCR_PAR11	dev/elan520.h	105;"	d
ELAN520_MMCR_PAR12	dev/elan520.h	106;"	d
ELAN520_MMCR_PAR13	dev/elan520.h	107;"	d
ELAN520_MMCR_PAR14	dev/elan520.h	108;"	d
ELAN520_MMCR_PAR15	dev/elan520.h	109;"	d
ELAN520_MMCR_PAR2	dev/elan520.h	96;"	d
ELAN520_MMCR_PAR3	dev/elan520.h	97;"	d
ELAN520_MMCR_PAR4	dev/elan520.h	98;"	d
ELAN520_MMCR_PAR5	dev/elan520.h	99;"	d
ELAN520_MMCR_PAR6	dev/elan520.h	100;"	d
ELAN520_MMCR_PAR7	dev/elan520.h	101;"	d
ELAN520_MMCR_PAR8	dev/elan520.h	102;"	d
ELAN520_MMCR_PAR9	dev/elan520.h	103;"	d
ELAN520_MMCR_PCIARBSTA	dev/elan520.h	85;"	d
ELAN520_MMCR_PCIHOSTMAP	dev/elan520.h	203;"	d
ELAN520_MMCR_PCIINTAMAP	dev/elan520.h	213;"	d
ELAN520_MMCR_PCIINTBMAP	dev/elan520.h	214;"	d
ELAN520_MMCR_PCIINTCMAP	dev/elan520.h	215;"	d
ELAN520_MMCR_PCIINTDMAP	dev/elan520.h	216;"	d
ELAN520_MMCR_PIOCLEAR15_0	dev/elan520.h	141;"	d
ELAN520_MMCR_PIOCLEAR31_16	dev/elan520.h	142;"	d
ELAN520_MMCR_PIODATA15_0	dev/elan520.h	137;"	d
ELAN520_MMCR_PIODATA31_16	dev/elan520.h	138;"	d
ELAN520_MMCR_PIODIR15_0	dev/elan520.h	135;"	d
ELAN520_MMCR_PIODIR31_16	dev/elan520.h	136;"	d
ELAN520_MMCR_PIOPFS15_0	dev/elan520.h	130;"	d
ELAN520_MMCR_PIOPFS31_16	dev/elan520.h	131;"	d
ELAN520_MMCR_PIOSET15_0	dev/elan520.h	139;"	d
ELAN520_MMCR_PIOSET31_16	dev/elan520.h	140;"	d
ELAN520_MMCR_PIT0MAP	dev/elan520.h	208;"	d
ELAN520_MMCR_PIT1MAP	dev/elan520.h	209;"	d
ELAN520_MMCR_PIT2MAP	dev/elan520.h	210;"	d
ELAN520_MMCR_RESCFG	dev/elan520.h	240;"	d
ELAN520_MMCR_RESSTA	dev/elan520.h	241;"	d
ELAN520_MMCR_REVID	dev/elan520.h	42;"	d
ELAN520_MMCR_ROMCS1CTL	dev/elan520.h	68;"	d
ELAN520_MMCR_ROMCS2CTL	dev/elan520.h	69;"	d
ELAN520_MMCR_RTCMAP	dev/elan520.h	220;"	d
ELAN520_MMCR_SL1PICMODE	dev/elan520.h	198;"	d
ELAN520_MMCR_SL2PICMODE	dev/elan520.h	199;"	d
ELAN520_MMCR_SSICMD	dev/elan520.h	189;"	d
ELAN520_MMCR_SSICTL	dev/elan520.h	187;"	d
ELAN520_MMCR_SSIMAP	dev/elan520.h	218;"	d
ELAN520_MMCR_SSIRCV	dev/elan520.h	191;"	d
ELAN520_MMCR_SSISTA	dev/elan520.h	190;"	d
ELAN520_MMCR_SSIXMIT	dev/elan520.h	188;"	d
ELAN520_MMCR_SWINT16_1	dev/elan520.h	200;"	d
ELAN520_MMCR_SWINT22_17	dev/elan520.h	201;"	d
ELAN520_MMCR_SWTMRCFG	dev/elan520.h	149;"	d
ELAN520_MMCR_SWTMRMICRO	dev/elan520.h	148;"	d
ELAN520_MMCR_SWTMRMILLI	dev/elan520.h	147;"	d
ELAN520_MMCR_SYSARBCTL	dev/elan520.h	84;"	d
ELAN520_MMCR_SYSARBMENB	dev/elan520.h	86;"	d
ELAN520_MMCR_SYSINFO	dev/elan520.h	239;"	d
ELAN520_MMCR_UART1CTL	dev/elan520.h	177;"	d
ELAN520_MMCR_UART1FCRSHAD	dev/elan520.h	179;"	d
ELAN520_MMCR_UART1MAP	dev/elan520.h	211;"	d
ELAN520_MMCR_UART1STA	dev/elan520.h	178;"	d
ELAN520_MMCR_UART2CTL	dev/elan520.h	180;"	d
ELAN520_MMCR_UART2FCRSHAD	dev/elan520.h	182;"	d
ELAN520_MMCR_UART2MAP	dev/elan520.h	212;"	d
ELAN520_MMCR_UART2STA	dev/elan520.h	181;"	d
ELAN520_MMCR_WDTMAP	dev/elan520.h	219;"	d
ELAN520_MMCR_WDTMRCNTH	dev/elan520.h	172;"	d
ELAN520_MMCR_WDTMRCNTL	dev/elan520.h	171;"	d
ELAN520_MMCR_WDTMRCTL	dev/elan520.h	170;"	d
ELAN520_MMCR_WPVMAP	dev/elan520.h	221;"	d
ELAN520_MMCR_WPVSTA	dev/elan520.h	93;"	d
ELAN520_MMCR__PICICR	dev/elan520.h	196;"	d
ELAN520_PCICFGADDR	dev/elan520.h	287;"	d
ELAN520_PCICFGDATA	dev/elan520.h	288;"	d
ELAST	include/errno.h	167;"	d
ELOOP	include/errno.h	132;"	d
EMFILE	include/errno.h	81;"	d
EMLINK	include/errno.h	90;"	d
EMSGSIZE	include/errno.h	107;"	d
ENAMETOOLONG	include/errno.h	134;"	d
ENCRYPT_CNT	include/arpa/telnet.h	314;"	d
ENCRYPT_DEC_KEYID	include/arpa/telnet.h	313;"	d
ENCRYPT_ENC_KEYID	include/arpa/telnet.h	312;"	d
ENCRYPT_END	include/arpa/telnet.h	309;"	d
ENCRYPT_IS	include/arpa/telnet.h	305;"	d
ENCRYPT_NAME	include/arpa/telnet.h	338;"	d
ENCRYPT_NAME_OK	include/arpa/telnet.h	337;"	d
ENCRYPT_REPLY	include/arpa/telnet.h	307;"	d
ENCRYPT_REQEND	include/arpa/telnet.h	311;"	d
ENCRYPT_REQSTART	include/arpa/telnet.h	310;"	d
ENCRYPT_START	include/arpa/telnet.h	308;"	d
ENCRYPT_SUPPORT	include/arpa/telnet.h	306;"	d
ENCTYPE_ANY	include/arpa/telnet.h	316;"	d
ENCTYPE_CNT	include/arpa/telnet.h	319;"	d
ENCTYPE_DES_CFB64	include/arpa/telnet.h	317;"	d
ENCTYPE_DES_OFB64	include/arpa/telnet.h	318;"	d
ENCTYPE_NAME	include/arpa/telnet.h	341;"	d
ENCTYPE_NAME_OK	include/arpa/telnet.h	340;"	d
ENEEDAUTH	include/errno.h	165;"	d
ENETDOWN	include/errno.h	119;"	d
ENETRESET	include/errno.h	121;"	d
ENETUNREACH	include/errno.h	120;"	d
ENFILE	include/errno.h	80;"	d
ENOBUFS	include/errno.h	124;"	d
ENODEV	include/errno.h	76;"	d
ENOENT	include/errno.h	56;"	d
ENOEXEC	include/errno.h	62;"	d
ENOIOCTLCMD	include/linux/errno.h	12;"	d
ENOLCK	include/errno.h	159;"	d
ENOMEM	include/errno.h	67;"	d
ENOPROTOOPT	include/errno.h	109;"	d
ENOSPACE	include/arpa/tftp.h	77;"	d
ENOSPC	include/errno.h	87;"	d
ENOSYS	include/errno.h	160;"	d
ENOTBLK	include/errno.h	71;"	d
ENOTCONN	include/errno.h	126;"	d
ENOTDIR	include/errno.h	77;"	d
ENOTEMPTY	include/errno.h	141;"	d
ENOTFOUND	include/arpa/tftp.h	75;"	d
ENOTSOCK	include/errno.h	105;"	d
ENOTSUPP	include/linux/errno.h	18;"	d
ENOTSYNC	include/linux/errno.h	16;"	d
ENOTTY	include/errno.h	82;"	d
ENOUSER	include/arpa/tftp.h	81;"	d
ENV_ESC	include/arpa/telnet.h	260;"	d
ENV_USERVAR	include/arpa/telnet.h	261;"	d
ENXIO	include/errno.h	60;"	d
EOF	include/stdio.h	93;"	d
EOPNOTSUPP	include/errno.h	112;"	d
EOR	include/arpa/telnet.h	61;"	d
EPERM	include/errno.h	55;"	d
EPFNOSUPPORT	include/errno.h	113;"	d
EPIPE	include/errno.h	91;"	d
EPROCLIM	include/errno.h	145;"	d
EPROCUNAVAIL	include/errno.h	156;"	d
EPROGMISMATCH	include/errno.h	155;"	d
EPROGUNAVAIL	include/errno.h	154;"	d
EPROTONOSUPPORT	include/errno.h	110;"	d
EPROTOTYPE	include/errno.h	108;"	d
ERANGE	include/errno.h	95;"	d
EREMOTE	include/errno.h	151;"	d
ERESTART	include/errno.h	172;"	d
ERESTARTNOHAND	include/linux/errno.h	11;"	d
ERESTARTNOINTR	include/linux/errno.h	10;"	d
ERESTARTSYS	include/linux/errno.h	9;"	d
EROFS	include/errno.h	89;"	d
ERPCMISMATCH	include/errno.h	153;"	d
ERROR	include/arpa/ftp.h	51;"	d
ERROR	include/arpa/tftp.h	54;"	d
ESERVERFAULT	include/linux/errno.h	20;"	d
ESHUTDOWN	include/errno.h	127;"	d
ESOCKTNOSUPPORT	include/errno.h	111;"	d
ESPIPE	include/errno.h	88;"	d
ESRCH	include/errno.h	57;"	d
ESTALE	include/errno.h	150;"	d
ETH0_ACCESS_PROTECTION_REG	dev/gt64420reg.h	782;"	d
ETH0_CURRENT_RX_DESC_PTR0	dev/gt64240reg.h	1069;"	d
ETH0_CURRENT_RX_DESC_PTR0	dev/gt64260reg.h	1060;"	d
ETH0_CURRENT_RX_DESC_PTR0	dev/gt64420reg.h	821;"	d
ETH0_CURRENT_RX_DESC_PTR0	dev/gt96132reg.h	452;"	d
ETH0_CURRENT_RX_DESC_PTR1	dev/gt64240reg.h	1070;"	d
ETH0_CURRENT_RX_DESC_PTR1	dev/gt64260reg.h	1061;"	d
ETH0_CURRENT_RX_DESC_PTR1	dev/gt64420reg.h	822;"	d
ETH0_CURRENT_RX_DESC_PTR1	dev/gt96132reg.h	453;"	d
ETH0_CURRENT_RX_DESC_PTR2	dev/gt64240reg.h	1071;"	d
ETH0_CURRENT_RX_DESC_PTR2	dev/gt64260reg.h	1062;"	d
ETH0_CURRENT_RX_DESC_PTR2	dev/gt64420reg.h	823;"	d
ETH0_CURRENT_RX_DESC_PTR2	dev/gt96132reg.h	454;"	d
ETH0_CURRENT_RX_DESC_PTR3	dev/gt64240reg.h	1072;"	d
ETH0_CURRENT_RX_DESC_PTR3	dev/gt64260reg.h	1063;"	d
ETH0_CURRENT_RX_DESC_PTR3	dev/gt64420reg.h	824;"	d
ETH0_CURRENT_RX_DESC_PTR3	dev/gt96132reg.h	455;"	d
ETH0_CURRENT_RX_DESC_PTR4	dev/gt64420reg.h	825;"	d
ETH0_CURRENT_RX_DESC_PTR5	dev/gt64420reg.h	826;"	d
ETH0_CURRENT_RX_DESC_PTR6	dev/gt64420reg.h	827;"	d
ETH0_CURRENT_RX_DESC_PTR7	dev/gt64420reg.h	828;"	d
ETH0_CURRENT_SERVED_TX_DESC_PTR	dev/gt64420reg.h	820;"	d
ETH0_CURRENT_TX_DESC_PTR0	dev/gt64240reg.h	1073;"	d
ETH0_CURRENT_TX_DESC_PTR0	dev/gt64260reg.h	1064;"	d
ETH0_CURRENT_TX_DESC_PTR0	dev/gt64420reg.h	829;"	d
ETH0_CURRENT_TX_DESC_PTR0	dev/gt96132reg.h	456;"	d
ETH0_CURRENT_TX_DESC_PTR1	dev/gt64240reg.h	1074;"	d
ETH0_CURRENT_TX_DESC_PTR1	dev/gt64260reg.h	1065;"	d
ETH0_CURRENT_TX_DESC_PTR1	dev/gt64420reg.h	830;"	d
ETH0_CURRENT_TX_DESC_PTR1	dev/gt96132reg.h	457;"	d
ETH0_CURRENT_TX_DESC_PTR2	dev/gt64420reg.h	831;"	d
ETH0_CURRENT_TX_DESC_PTR3	dev/gt64420reg.h	832;"	d
ETH0_CURRENT_TX_DESC_PTR4	dev/gt64420reg.h	833;"	d
ETH0_CURRENT_TX_DESC_PTR5	dev/gt64420reg.h	834;"	d
ETH0_CURRENT_TX_DESC_PTR6	dev/gt64420reg.h	835;"	d
ETH0_CURRENT_TX_DESC_PTR7	dev/gt64420reg.h	836;"	d
ETH0_DA_FILTER_OTHER_MULTICAST_TABLE_BASE	dev/gt64420reg.h	863;"	d
ETH0_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE	dev/gt64420reg.h	862;"	d
ETH0_DA_FILTER_UNICAST_TABLE_BASE	dev/gt64420reg.h	864;"	d
ETH0_DSCP_0	dev/gt64420reg.h	792;"	d
ETH0_DSCP_1	dev/gt64420reg.h	793;"	d
ETH0_DSCP_2	dev/gt64420reg.h	794;"	d
ETH0_DSCP_3	dev/gt64420reg.h	795;"	d
ETH0_DSCP_4	dev/gt64420reg.h	796;"	d
ETH0_DSCP_5	dev/gt64420reg.h	797;"	d
ETH0_DSCP_6	dev/gt64420reg.h	798;"	d
ETH0_FIRST_RX_DESC_PTR0	dev/gt64240reg.h	1065;"	d
ETH0_FIRST_RX_DESC_PTR0	dev/gt64260reg.h	1056;"	d
ETH0_FIRST_RX_DESC_PTR0	dev/gt96132reg.h	448;"	d
ETH0_FIRST_RX_DESC_PTR1	dev/gt64240reg.h	1066;"	d
ETH0_FIRST_RX_DESC_PTR1	dev/gt64260reg.h	1057;"	d
ETH0_FIRST_RX_DESC_PTR1	dev/gt96132reg.h	449;"	d
ETH0_FIRST_RX_DESC_PTR2	dev/gt64240reg.h	1067;"	d
ETH0_FIRST_RX_DESC_PTR2	dev/gt64260reg.h	1058;"	d
ETH0_FIRST_RX_DESC_PTR2	dev/gt96132reg.h	450;"	d
ETH0_FIRST_RX_DESC_PTR3	dev/gt64240reg.h	1068;"	d
ETH0_FIRST_RX_DESC_PTR3	dev/gt64260reg.h	1059;"	d
ETH0_FIRST_RX_DESC_PTR3	dev/gt96132reg.h	451;"	d
ETH0_FLOW_CNTROL_SOURCE_ADDR_HO	dev/gt96132reg.h	436;"	d
ETH0_FLOW_CNTROL_SOURCE_ADDR_LO	dev/gt96132reg.h	435;"	d
ETH0_FLOW_CONTROL_SOURCE_ADDR_HI	dev/gt64240reg.h	1060;"	d
ETH0_FLOW_CONTROL_SOURCE_ADDR_HI	dev/gt64260reg.h	1051;"	d
ETH0_FLOW_CONTROL_SOURCE_ADDR_LO	dev/gt64240reg.h	1059;"	d
ETH0_FLOW_CONTROL_SOURCE_ADDR_LO	dev/gt64260reg.h	1050;"	d
ETH0_GMII_SERIAL_PARAMETRS_REG	dev/gt64420reg.h	787;"	d
ETH0_HASH_TABLE_PTR_REG	dev/gt64240reg.h	1058;"	d
ETH0_HASH_TABLE_PTR_REG	dev/gt64260reg.h	1049;"	d
ETH0_HASH_TABLE_PTR_REG	dev/gt96132reg.h	434;"	d
ETH0_INTERNAL_USE_REG	dev/gt64420reg.h	818;"	d
ETH0_INTERRUPT_CAUSE_EXTEND_REG	dev/gt64420reg.h	808;"	d
ETH0_INTERRUPT_CAUSE_REG	dev/gt64240reg.h	1063;"	d
ETH0_INTERRUPT_CAUSE_REG	dev/gt64260reg.h	1054;"	d
ETH0_INTERRUPT_CAUSE_REG	dev/gt64420reg.h	807;"	d
ETH0_INTERRUPT_CAUSE_REG	dev/gt96132reg.h	439;"	d
ETH0_INTERRUPT_EXTEND_MASK_REG	dev/gt64420reg.h	810;"	d
ETH0_INTERRUPT_MASK_REG	dev/gt64240reg.h	1064;"	d
ETH0_INTERRUPT_MASK_REG	dev/gt64260reg.h	1055;"	d
ETH0_INTERRUPT_MASK_REG	dev/gt64420reg.h	809;"	d
ETH0_INTERRUPT_MASK_REG	dev/gt96132reg.h	440;"	d
ETH0_MAC_ADDR_HIGH	dev/gt64420reg.h	790;"	d
ETH0_MAC_ADDR_LOW	dev/gt64420reg.h	789;"	d
ETH0_MAXIMUM_TRANSMIT_UNIT	dev/gt64420reg.h	805;"	d
ETH0_MIB_COUNTERS_BASE	dev/gt64420reg.h	783;"	d
ETH0_MIB_COUNTER_BASE	dev/gt64240reg.h	1075;"	d
ETH0_MIB_COUNTER_BASE	dev/gt64260reg.h	1066;"	d
ETH0_MIB_COUNTER_BASE	dev/gt96132reg.h	458;"	d
ETH0_MII_SERIAL_PARAMETRS_REG	dev/gt64420reg.h	786;"	d
ETH0_PORT_COMMAND_REG	dev/gt64240reg.h	1055;"	d
ETH0_PORT_COMMAND_REG	dev/gt64260reg.h	1046;"	d
ETH0_PORT_COMMAND_REG	dev/gt96132reg.h	431;"	d
ETH0_PORT_CONFIG_EXT_REG	dev/gt64240reg.h	1054;"	d
ETH0_PORT_CONFIG_EXT_REG	dev/gt64260reg.h	1045;"	d
ETH0_PORT_CONFIG_EXT_REG	dev/gt64420reg.h	785;"	d
ETH0_PORT_CONFIG_EXT_REG	dev/gt96132reg.h	430;"	d
ETH0_PORT_CONFIG_REG	dev/gt64240reg.h	1053;"	d
ETH0_PORT_CONFIG_REG	dev/gt64260reg.h	1044;"	d
ETH0_PORT_CONFIG_REG	dev/gt64420reg.h	784;"	d
ETH0_PORT_CONFIG_REG	dev/gt96132reg.h	429;"	d
ETH0_PORT_DEBUG_0_REG	dev/gt64420reg.h	815;"	d
ETH0_PORT_DEBUG_1_REG	dev/gt64420reg.h	816;"	d
ETH0_PORT_INTERNAL_ADDR_ERROR_REG	dev/gt64420reg.h	817;"	d
ETH0_PORT_MAXIMUM_TOKEN_BUCKET_SIZE	dev/gt64420reg.h	806;"	d
ETH0_PORT_SERIAL_CONTROL_REG	dev/gt64420reg.h	799;"	d
ETH0_PORT_STATUS_REG	dev/gt64240reg.h	1056;"	d
ETH0_PORT_STATUS_REG	dev/gt64260reg.h	1047;"	d
ETH0_PORT_STATUS_REG	dev/gt64420reg.h	801;"	d
ETH0_PORT_STATUS_REG	dev/gt96132reg.h	432;"	d
ETH0_PORT_TX_TOKEN_BUCKET_COUNT	dev/gt64420reg.h	861;"	d
ETH0_PORT_TX_TOKEN_BUCKET_RATE_CONFIG	dev/gt64420reg.h	804;"	d
ETH0_RECEIVE_QUEUE_COMMAND_REG	dev/gt64420reg.h	819;"	d
ETH0_RX_DISCARDED_FRAMES_COUNTER	dev/gt64420reg.h	814;"	d
ETH0_RX_FIFO_URGENT_THRESHOLD_REG	dev/gt64420reg.h	811;"	d
ETH0_RX_MINIMAL_FRAME_SIZE_REG	dev/gt64420reg.h	813;"	d
ETH0_SDMA_COMMAND_REG	dev/gt64240reg.h	1062;"	d
ETH0_SDMA_COMMAND_REG	dev/gt64260reg.h	1053;"	d
ETH0_SDMA_COMMAND_REG	dev/gt96132reg.h	438;"	d
ETH0_SDMA_CONFIG_REG	dev/gt64240reg.h	1061;"	d
ETH0_SDMA_CONFIG_REG	dev/gt64260reg.h	1052;"	d
ETH0_SDMA_CONFIG_REG	dev/gt64420reg.h	791;"	d
ETH0_SDMA_CONFIG_REG	dev/gt96132reg.h	437;"	d
ETH0_SERIAL_PARAMETRS_REG	dev/gt64240reg.h	1057;"	d
ETH0_SERIAL_PARAMETRS_REG	dev/gt64260reg.h	1048;"	d
ETH0_SERIAL_PARAMETRS_REG	dev/gt96132reg.h	433;"	d
ETH0_TRANSMIT_QUEUE_COMMAND_REG	dev/gt64420reg.h	802;"	d
ETH0_TX_FIFO_URGENT_THRESHOLD_REG	dev/gt64420reg.h	812;"	d
ETH0_TX_QUEUE_0_ARBITER_CONFIG	dev/gt64420reg.h	853;"	d
ETH0_TX_QUEUE_0_TOKEN_BUCKET_CONFIG	dev/gt64420reg.h	845;"	d
ETH0_TX_QUEUE_0_TOKEN_BUCKET_COUNT	dev/gt64420reg.h	837;"	d
ETH0_TX_QUEUE_1_ARBITER_CONFIG	dev/gt64420reg.h	854;"	d
ETH0_TX_QUEUE_1_TOKEN_BUCKET_CONFIG	dev/gt64420reg.h	846;"	d
ETH0_TX_QUEUE_1_TOKEN_BUCKET_COUNT	dev/gt64420reg.h	838;"	d
ETH0_TX_QUEUE_2_ARBITER_CONFIG	dev/gt64420reg.h	855;"	d
ETH0_TX_QUEUE_2_TOKEN_BUCKET_CONFIG	dev/gt64420reg.h	847;"	d
ETH0_TX_QUEUE_2_TOKEN_BUCKET_COUNT	dev/gt64420reg.h	839;"	d
ETH0_TX_QUEUE_3_ARBITER_CONFIG	dev/gt64420reg.h	856;"	d
ETH0_TX_QUEUE_3_TOKEN_BUCKET_CONFIG	dev/gt64420reg.h	848;"	d
ETH0_TX_QUEUE_3_TOKEN_BUCKET_COUNT	dev/gt64420reg.h	840;"	d
ETH0_TX_QUEUE_4_ARBITER_CONFIG	dev/gt64420reg.h	857;"	d
ETH0_TX_QUEUE_4_TOKEN_BUCKET_CONFIG	dev/gt64420reg.h	849;"	d
ETH0_TX_QUEUE_4_TOKEN_BUCKET_COUNT	dev/gt64420reg.h	841;"	d
ETH0_TX_QUEUE_5_ARBITER_CONFIG	dev/gt64420reg.h	858;"	d
ETH0_TX_QUEUE_5_TOKEN_BUCKET_CONFIG	dev/gt64420reg.h	850;"	d
ETH0_TX_QUEUE_5_TOKEN_BUCKET_COUNT	dev/gt64420reg.h	842;"	d
ETH0_TX_QUEUE_6_ARBITER_CONFIG	dev/gt64420reg.h	859;"	d
ETH0_TX_QUEUE_6_TOKEN_BUCKET_CONFIG	dev/gt64420reg.h	851;"	d
ETH0_TX_QUEUE_6_TOKEN_BUCKET_COUNT	dev/gt64420reg.h	843;"	d
ETH0_TX_QUEUE_7_ARBITER_CONFIG	dev/gt64420reg.h	860;"	d
ETH0_TX_QUEUE_7_TOKEN_BUCKET_CONFIG	dev/gt64420reg.h	852;"	d
ETH0_TX_QUEUE_7_TOKEN_BUCKET_COUNT	dev/gt64420reg.h	844;"	d
ETH0_TX_QUEUE_FIXED_PRIORITY	dev/gt64420reg.h	803;"	d
ETH0_VLAN_ETHERTYPE_REG	dev/gt64420reg.h	788;"	d
ETH0_VLAN_PRIORITY_TAG_TO_PRIORITY	dev/gt64420reg.h	800;"	d
ETHER0_TOS_PRIORITY_0_HIGH	dev/gt96132reg.h	443;"	d
ETHER0_TOS_PRIORITY_0_LOW	dev/gt96132reg.h	442;"	d
ETHER0_TOS_PRIORITY_1_HIGH	dev/gt96132reg.h	445;"	d
ETHER0_TOS_PRIORITY_1_LOW	dev/gt96132reg.h	444;"	d
ETHER0_VLAN_TO_PRIORITY	dev/gt96132reg.h	446;"	d
ETHER1_1ST_RX_DESC_PTR0	dev/gt96132reg.h	472;"	d
ETHER1_1ST_RX_DESC_PTR1	dev/gt96132reg.h	473;"	d
ETHER1_1ST_RX_DESC_PTR2	dev/gt96132reg.h	474;"	d
ETHER1_1ST_RX_DESC_PTR3	dev/gt96132reg.h	475;"	d
ETHER1_CURR_RX_DESC_PTR0	dev/gt96132reg.h	476;"	d
ETHER1_CURR_RX_DESC_PTR1	dev/gt96132reg.h	477;"	d
ETHER1_CURR_RX_DESC_PTR2	dev/gt96132reg.h	478;"	d
ETHER1_CURR_RX_DESC_PTR3	dev/gt96132reg.h	479;"	d
ETHER1_CURR_TX_DESC_PTR0	dev/gt96132reg.h	480;"	d
ETHER1_CURR_TX_DESC_PTR1	dev/gt96132reg.h	481;"	d
ETHER1_FLOW_CNTRL_SRC_ADDR_H	dev/gt96132reg.h	467;"	d
ETHER1_FLOW_CNTRL_SRC_ADDR_L	dev/gt96132reg.h	466;"	d
ETHER1_HASH_TBL_PTR_REG	dev/gt96132reg.h	465;"	d
ETHER1_INT_CAUSE_REG	dev/gt96132reg.h	470;"	d
ETHER1_INT_MASK_REG	dev/gt96132reg.h	471;"	d
ETHER1_MIB_COUNT_BASE	dev/gt96132reg.h	482;"	d
ETHER1_PORT_COMM_REG	dev/gt96132reg.h	462;"	d
ETHER1_PORT_CONFIG_EXT_REG	dev/gt96132reg.h	461;"	d
ETHER1_PORT_CONFIG_REG	dev/gt96132reg.h	460;"	d
ETHER1_PORT_STATUS_REG	dev/gt96132reg.h	463;"	d
ETHER1_SDMA_COMM_REG	dev/gt96132reg.h	469;"	d
ETHER1_SDMA_CONFIG_REG	dev/gt96132reg.h	468;"	d
ETHER1_SER_PARAM_REG	dev/gt96132reg.h	464;"	d
ETHERNET0_CAUSE_REGISTER	dev/gt96132reg.h	294;"	d
ETHERNET0_MASK_REGISTER	dev/gt96132reg.h	295;"	d
ETHERNET1_CAUSE_REGISTER	dev/gt96132reg.h	296;"	d
ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER0	dev/gt64240reg.h	1095;"	d
ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER0	dev/gt64260reg.h	1086;"	d
ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER1	dev/gt64240reg.h	1096;"	d
ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER1	dev/gt64260reg.h	1087;"	d
ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER2	dev/gt64240reg.h	1097;"	d
ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER2	dev/gt64260reg.h	1088;"	d
ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER3	dev/gt64240reg.h	1098;"	d
ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER3	dev/gt64260reg.h	1089;"	d
ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER0	dev/gt64240reg.h	1099;"	d
ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER0	dev/gt64260reg.h	1090;"	d
ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER1	dev/gt64240reg.h	1100;"	d
ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER1	dev/gt64260reg.h	1091;"	d
ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER0	dev/gt64240reg.h	1091;"	d
ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER0	dev/gt64260reg.h	1082;"	d
ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER1	dev/gt64240reg.h	1092;"	d
ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER1	dev/gt64260reg.h	1083;"	d
ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER2	dev/gt64240reg.h	1093;"	d
ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER2	dev/gt64260reg.h	1084;"	d
ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER3	dev/gt64240reg.h	1094;"	d
ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER3	dev/gt64260reg.h	1085;"	d
ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_HIGH	dev/gt64240reg.h	1086;"	d
ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_HIGH	dev/gt64260reg.h	1077;"	d
ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_LOW	dev/gt64240reg.h	1085;"	d
ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_LOW	dev/gt64260reg.h	1076;"	d
ETHERNET1_HASH_TABLE_POINTER_REGISTER	dev/gt64240reg.h	1084;"	d
ETHERNET1_HASH_TABLE_POINTER_REGISTER	dev/gt64260reg.h	1075;"	d
ETHERNET1_INTERRUPT_CAUSE_REGISTER	dev/gt64240reg.h	1089;"	d
ETHERNET1_INTERRUPT_CAUSE_REGISTER	dev/gt64260reg.h	1080;"	d
ETHERNET1_INTERRUPT_MASK_REGISTER	dev/gt64240reg.h	1090;"	d
ETHERNET1_INTERRUPT_MASK_REGISTER	dev/gt64260reg.h	1081;"	d
ETHERNET1_MASK_REGISTER	dev/gt96132reg.h	297;"	d
ETHERNET1_MIB_COUNTER_BASE	dev/gt64240reg.h	1101;"	d
ETHERNET1_MIB_COUNTER_BASE	dev/gt64260reg.h	1092;"	d
ETHERNET1_PORT_COMMAND_REGISTER	dev/gt64240reg.h	1081;"	d
ETHERNET1_PORT_COMMAND_REGISTER	dev/gt64260reg.h	1072;"	d
ETHERNET1_PORT_CONFIGURATION_EXTEND_REGISTER	dev/gt64240reg.h	1080;"	d
ETHERNET1_PORT_CONFIGURATION_EXTEND_REGISTER	dev/gt64260reg.h	1071;"	d
ETHERNET1_PORT_CONFIGURATION_REGISTER	dev/gt64240reg.h	1079;"	d
ETHERNET1_PORT_CONFIGURATION_REGISTER	dev/gt64260reg.h	1070;"	d
ETHERNET1_PORT_STATUS_REGISTER	dev/gt64240reg.h	1082;"	d
ETHERNET1_PORT_STATUS_REGISTER	dev/gt64260reg.h	1073;"	d
ETHERNET1_SDMA_COMMAND_REGISTER	dev/gt64240reg.h	1088;"	d
ETHERNET1_SDMA_COMMAND_REGISTER	dev/gt64260reg.h	1079;"	d
ETHERNET1_SDMA_CONFIGURATION_REGISTER	dev/gt64240reg.h	1087;"	d
ETHERNET1_SDMA_CONFIGURATION_REGISTER	dev/gt64260reg.h	1078;"	d
ETHERNET1_SERIAL_PARAMETRS_REGISTER	dev/gt64240reg.h	1083;"	d
ETHERNET1_SERIAL_PARAMETRS_REGISTER	dev/gt64260reg.h	1074;"	d
ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER0	dev/gt64240reg.h	1121;"	d
ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER0	dev/gt64260reg.h	1112;"	d
ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER1	dev/gt64240reg.h	1122;"	d
ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER1	dev/gt64260reg.h	1113;"	d
ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER2	dev/gt64240reg.h	1123;"	d
ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER2	dev/gt64260reg.h	1114;"	d
ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER3	dev/gt64240reg.h	1124;"	d
ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER3	dev/gt64260reg.h	1115;"	d
ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER0	dev/gt64240reg.h	1125;"	d
ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER0	dev/gt64260reg.h	1116;"	d
ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER1	dev/gt64240reg.h	1126;"	d
ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER1	dev/gt64260reg.h	1117;"	d
ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER0	dev/gt64240reg.h	1117;"	d
ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER0	dev/gt64260reg.h	1108;"	d
ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER1	dev/gt64240reg.h	1118;"	d
ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER1	dev/gt64260reg.h	1109;"	d
ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER2	dev/gt64240reg.h	1119;"	d
ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER2	dev/gt64260reg.h	1110;"	d
ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER3	dev/gt64240reg.h	1120;"	d
ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER3	dev/gt64260reg.h	1111;"	d
ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_HIGH	dev/gt64240reg.h	1112;"	d
ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_HIGH	dev/gt64260reg.h	1103;"	d
ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_LOW	dev/gt64240reg.h	1111;"	d
ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_LOW	dev/gt64260reg.h	1102;"	d
ETHERNET2_HASH_TABLE_POINTER_REGISTER	dev/gt64240reg.h	1110;"	d
ETHERNET2_HASH_TABLE_POINTER_REGISTER	dev/gt64260reg.h	1101;"	d
ETHERNET2_INTERRUPT_CAUSE_REGISTER	dev/gt64240reg.h	1115;"	d
ETHERNET2_INTERRUPT_CAUSE_REGISTER	dev/gt64260reg.h	1106;"	d
ETHERNET2_INTERRUPT_MASK_REGISTER	dev/gt64240reg.h	1116;"	d
ETHERNET2_INTERRUPT_MASK_REGISTER	dev/gt64260reg.h	1107;"	d
ETHERNET2_MIB_COUNTER_BASE	dev/gt64240reg.h	1127;"	d
ETHERNET2_MIB_COUNTER_BASE	dev/gt64260reg.h	1118;"	d
ETHERNET2_PORT_COMMAND_REGISTER	dev/gt64240reg.h	1107;"	d
ETHERNET2_PORT_COMMAND_REGISTER	dev/gt64260reg.h	1098;"	d
ETHERNET2_PORT_CONFIGURATION_EXTEND_REGISTER	dev/gt64240reg.h	1106;"	d
ETHERNET2_PORT_CONFIGURATION_EXTEND_REGISTER	dev/gt64260reg.h	1097;"	d
ETHERNET2_PORT_CONFIGURATION_REGISTER	dev/gt64240reg.h	1105;"	d
ETHERNET2_PORT_CONFIGURATION_REGISTER	dev/gt64260reg.h	1096;"	d
ETHERNET2_PORT_STATUS_REGISTER	dev/gt64240reg.h	1108;"	d
ETHERNET2_PORT_STATUS_REGISTER	dev/gt64260reg.h	1099;"	d
ETHERNET2_SDMA_COMMAND_REGISTER	dev/gt64240reg.h	1114;"	d
ETHERNET2_SDMA_COMMAND_REGISTER	dev/gt64260reg.h	1105;"	d
ETHERNET2_SDMA_CONFIGURATION_REGISTER	dev/gt64240reg.h	1113;"	d
ETHERNET2_SDMA_CONFIGURATION_REGISTER	dev/gt64260reg.h	1104;"	d
ETHERNET2_SERIAL_PARAMETRS_REGISTER	dev/gt64240reg.h	1109;"	d
ETHERNET2_SERIAL_PARAMETRS_REGISTER	dev/gt64260reg.h	1100;"	d
ETHERNET_0_ADDRESS_CONTROL_HIGH	dev/gt64240reg.h	980;"	d
ETHERNET_0_ADDRESS_CONTROL_HIGH	dev/gt64260reg.h	971;"	d
ETHERNET_0_ADDRESS_CONTROL_HIGH	dev/mv64340reg.h	919;"	d
ETHERNET_0_ADDRESS_CONTROL_LOW	dev/gt64240reg.h	979;"	d
ETHERNET_0_ADDRESS_CONTROL_LOW	dev/gt64260reg.h	970;"	d
ETHERNET_0_ADDRESS_CONTROL_LOW	dev/mv64340reg.h	918;"	d
ETHERNET_0_HASH_TABLE_PCI_HIGH_ADDRESS	dev/gt64240reg.h	985;"	d
ETHERNET_0_HASH_TABLE_PCI_HIGH_ADDRESS	dev/gt64260reg.h	976;"	d
ETHERNET_0_HASH_TABLE_PCI_HIGH_ADDRESS	dev/mv64340reg.h	924;"	d
ETHERNET_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS	dev/gt64240reg.h	981;"	d
ETHERNET_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS	dev/gt64260reg.h	972;"	d
ETHERNET_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS	dev/mv64340reg.h	920;"	d
ETHERNET_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS	dev/gt64240reg.h	983;"	d
ETHERNET_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS	dev/gt64260reg.h	974;"	d
ETHERNET_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS	dev/mv64340reg.h	922;"	d
ETHERNET_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS	dev/gt64240reg.h	982;"	d
ETHERNET_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS	dev/gt64260reg.h	973;"	d
ETHERNET_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS	dev/mv64340reg.h	921;"	d
ETHERNET_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS	dev/gt64240reg.h	984;"	d
ETHERNET_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS	dev/gt64260reg.h	975;"	d
ETHERNET_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS	dev/mv64340reg.h	923;"	d
ETHERNET_1_ADDRESS_CONTROL_HIGH	dev/gt64240reg.h	987;"	d
ETHERNET_1_ADDRESS_CONTROL_HIGH	dev/gt64260reg.h	978;"	d
ETHERNET_1_ADDRESS_CONTROL_HIGH	dev/mv64340reg.h	926;"	d
ETHERNET_1_ADDRESS_CONTROL_LOW	dev/gt64240reg.h	986;"	d
ETHERNET_1_ADDRESS_CONTROL_LOW	dev/gt64260reg.h	977;"	d
ETHERNET_1_ADDRESS_CONTROL_LOW	dev/mv64340reg.h	925;"	d
ETHERNET_1_HASH_TABLE_PCI_HIGH_ADDRESS	dev/gt64240reg.h	992;"	d
ETHERNET_1_HASH_TABLE_PCI_HIGH_ADDRESS	dev/gt64260reg.h	983;"	d
ETHERNET_1_HASH_TABLE_PCI_HIGH_ADDRESS	dev/mv64340reg.h	931;"	d
ETHERNET_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS	dev/gt64240reg.h	988;"	d
ETHERNET_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS	dev/gt64260reg.h	979;"	d
ETHERNET_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS	dev/mv64340reg.h	927;"	d
ETHERNET_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS	dev/gt64240reg.h	990;"	d
ETHERNET_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS	dev/gt64260reg.h	981;"	d
ETHERNET_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS	dev/mv64340reg.h	929;"	d
ETHERNET_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS	dev/gt64240reg.h	989;"	d
ETHERNET_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS	dev/gt64260reg.h	980;"	d
ETHERNET_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS	dev/mv64340reg.h	928;"	d
ETHERNET_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS	dev/gt64240reg.h	991;"	d
ETHERNET_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS	dev/gt64260reg.h	982;"	d
ETHERNET_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS	dev/mv64340reg.h	930;"	d
ETHERNET_2_ADDRESS_CONTROL_HIGH	dev/gt64240reg.h	994;"	d
ETHERNET_2_ADDRESS_CONTROL_HIGH	dev/gt64260reg.h	985;"	d
ETHERNET_2_ADDRESS_CONTROL_HIGH	dev/mv64340reg.h	933;"	d
ETHERNET_2_ADDRESS_CONTROL_LOW	dev/gt64240reg.h	993;"	d
ETHERNET_2_ADDRESS_CONTROL_LOW	dev/gt64260reg.h	984;"	d
ETHERNET_2_ADDRESS_CONTROL_LOW	dev/mv64340reg.h	932;"	d
ETHERNET_2_HASH_TABLE_PCI_HIGH_ADDRESS	dev/gt64240reg.h	999;"	d
ETHERNET_2_HASH_TABLE_PCI_HIGH_ADDRESS	dev/gt64260reg.h	990;"	d
ETHERNET_2_HASH_TABLE_PCI_HIGH_ADDRESS	dev/mv64340reg.h	938;"	d
ETHERNET_2_RECEIVE_BUFFER_PCI_HIGH_ADDRESS	dev/gt64240reg.h	995;"	d
ETHERNET_2_RECEIVE_BUFFER_PCI_HIGH_ADDRESS	dev/gt64260reg.h	986;"	d
ETHERNET_2_RECEIVE_BUFFER_PCI_HIGH_ADDRESS	dev/mv64340reg.h	934;"	d
ETHERNET_2_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS	dev/gt64240reg.h	997;"	d
ETHERNET_2_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS	dev/gt64260reg.h	988;"	d
ETHERNET_2_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS	dev/mv64340reg.h	936;"	d
ETHERNET_2_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS	dev/gt64240reg.h	996;"	d
ETHERNET_2_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS	dev/gt64260reg.h	987;"	d
ETHERNET_2_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS	dev/mv64340reg.h	935;"	d
ETHERNET_2_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS	dev/gt64240reg.h	998;"	d
ETHERNET_2_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS	dev/gt64260reg.h	989;"	d
ETHERNET_2_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS	dev/mv64340reg.h	937;"	d
ETHERNET_PORTS_DIFFERENCE_OFFSETS	dev/gt64240reg.h	1049;"	d
ETHERNET_PORTS_DIFFERENCE_OFFSETS	dev/gt64260reg.h	1040;"	d
ETHERNET_PORTS_DIFFERENCE_OFFSETS	dev/gt64420reg.h	669;"	d
ETHERNET_PORTS_DIFFERENCE_OFFSETS	dev/gt96132reg.h	427;"	d
ETHER_OFFS	include/tgt/bonito.h	36;"	d
ETHER_OFFS	include/tgt/bonito.h	41;"	d
ETH_ACCESS_PROTECTION_REG	dev/gt64420reg.h	698;"	d
ETH_ACCESS_PROTECTION_REG	dev/mv64340reg.h	830;"	d
ETH_ACCESS_PROTECTION_REG	dev/mv64360reg.h	747;"	d
ETH_BAR_0	dev/gt64420reg.h	679;"	d
ETH_BAR_0	dev/mv64340reg.h	811;"	d
ETH_BAR_0	dev/mv64360reg.h	728;"	d
ETH_BAR_1	dev/gt64420reg.h	680;"	d
ETH_BAR_1	dev/mv64340reg.h	812;"	d
ETH_BAR_1	dev/mv64360reg.h	729;"	d
ETH_BAR_2	dev/gt64420reg.h	681;"	d
ETH_BAR_2	dev/mv64340reg.h	813;"	d
ETH_BAR_2	dev/mv64360reg.h	730;"	d
ETH_BAR_3	dev/gt64420reg.h	682;"	d
ETH_BAR_3	dev/mv64340reg.h	814;"	d
ETH_BAR_3	dev/mv64360reg.h	731;"	d
ETH_BAR_4	dev/gt64420reg.h	683;"	d
ETH_BAR_4	dev/mv64340reg.h	815;"	d
ETH_BAR_4	dev/mv64360reg.h	732;"	d
ETH_BAR_5	dev/gt64420reg.h	684;"	d
ETH_BAR_5	dev/mv64340reg.h	816;"	d
ETH_BAR_5	dev/mv64360reg.h	733;"	d
ETH_BASE_ADDR_ENABLE_REG	dev/gt64420reg.h	697;"	d
ETH_BASE_ADDR_ENABLE_REG	dev/mv64340reg.h	829;"	d
ETH_BASE_ADDR_ENABLE_REG	dev/mv64360reg.h	746;"	d
ETH_CURRENT_SERVED_TX_DESC_PTR	dev/gt64420reg.h	736;"	d
ETH_CURRENT_SERVED_TX_DESC_PTR	dev/mv64340reg.h	868;"	d
ETH_CURRENT_SERVED_TX_DESC_PTR	dev/mv64360reg.h	785;"	d
ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE	dev/gt64420reg.h	779;"	d
ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE	dev/mv64340reg.h	911;"	d
ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE	dev/mv64360reg.h	828;"	d
ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE	dev/gt64420reg.h	778;"	d
ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE	dev/mv64340reg.h	910;"	d
ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE	dev/mv64360reg.h	827;"	d
ETH_DA_FILTER_UNICAST_TABLE_BASE	dev/gt64420reg.h	780;"	d
ETH_DA_FILTER_UNICAST_TABLE_BASE	dev/mv64340reg.h	912;"	d
ETH_DA_FILTER_UNICAST_TABLE_BASE	dev/mv64360reg.h	829;"	d
ETH_DSCP_0	dev/gt64420reg.h	708;"	d
ETH_DSCP_0	dev/mv64340reg.h	840;"	d
ETH_DSCP_0	dev/mv64360reg.h	757;"	d
ETH_DSCP_1	dev/gt64420reg.h	709;"	d
ETH_DSCP_1	dev/mv64340reg.h	841;"	d
ETH_DSCP_1	dev/mv64360reg.h	758;"	d
ETH_DSCP_2	dev/gt64420reg.h	710;"	d
ETH_DSCP_2	dev/mv64340reg.h	842;"	d
ETH_DSCP_2	dev/mv64360reg.h	759;"	d
ETH_DSCP_3	dev/gt64420reg.h	711;"	d
ETH_DSCP_3	dev/mv64340reg.h	843;"	d
ETH_DSCP_3	dev/mv64360reg.h	760;"	d
ETH_DSCP_4	dev/gt64420reg.h	712;"	d
ETH_DSCP_4	dev/mv64340reg.h	844;"	d
ETH_DSCP_4	dev/mv64360reg.h	761;"	d
ETH_DSCP_5	dev/gt64420reg.h	713;"	d
ETH_DSCP_5	dev/mv64340reg.h	845;"	d
ETH_DSCP_5	dev/mv64360reg.h	762;"	d
ETH_DSCP_6	dev/gt64420reg.h	714;"	d
ETH_DSCP_6	dev/mv64340reg.h	846;"	d
ETH_DSCP_6	dev/mv64360reg.h	763;"	d
ETH_GMII_SERIAL_PARAMETRS_REG	dev/gt64420reg.h	703;"	d
ETH_GMII_SERIAL_PARAMETRS_REG	dev/mv64340reg.h	835;"	d
ETH_GMII_SERIAL_PARAMETRS_REG	dev/mv64360reg.h	752;"	d
ETH_HEADERS_RETARGET_BASE_REG	dev/gt64420reg.h	691;"	d
ETH_HEADERS_RETARGET_BASE_REG	dev/mv64340reg.h	823;"	d
ETH_HEADERS_RETARGET_BASE_REG	dev/mv64360reg.h	740;"	d
ETH_HEADERS_RETARGET_CONTROL_REG	dev/gt64420reg.h	692;"	d
ETH_HEADERS_RETARGET_CONTROL_REG	dev/mv64340reg.h	824;"	d
ETH_HEADERS_RETARGET_CONTROL_REG	dev/mv64360reg.h	741;"	d
ETH_HIGH_ADDR_REMAP_REG_0	dev/gt64420reg.h	693;"	d
ETH_HIGH_ADDR_REMAP_REG_0	dev/mv64340reg.h	825;"	d
ETH_HIGH_ADDR_REMAP_REG_0	dev/mv64360reg.h	742;"	d
ETH_HIGH_ADDR_REMAP_REG_1	dev/gt64420reg.h	694;"	d
ETH_HIGH_ADDR_REMAP_REG_1	dev/mv64340reg.h	826;"	d
ETH_HIGH_ADDR_REMAP_REG_1	dev/mv64360reg.h	743;"	d
ETH_HIGH_ADDR_REMAP_REG_2	dev/gt64420reg.h	695;"	d
ETH_HIGH_ADDR_REMAP_REG_2	dev/mv64340reg.h	827;"	d
ETH_HIGH_ADDR_REMAP_REG_2	dev/mv64360reg.h	744;"	d
ETH_HIGH_ADDR_REMAP_REG_3	dev/gt64420reg.h	696;"	d
ETH_HIGH_ADDR_REMAP_REG_3	dev/mv64340reg.h	828;"	d
ETH_HIGH_ADDR_REMAP_REG_3	dev/mv64360reg.h	745;"	d
ETH_INTERNAL_USE_REG	dev/gt64420reg.h	734;"	d
ETH_INTERNAL_USE_REG	dev/mv64340reg.h	866;"	d
ETH_INTERNAL_USE_REG	dev/mv64360reg.h	783;"	d
ETH_INTERRUPT_CAUSE_EXTEND_REG	dev/gt64420reg.h	724;"	d
ETH_INTERRUPT_CAUSE_EXTEND_REG	dev/mv64340reg.h	856;"	d
ETH_INTERRUPT_CAUSE_EXTEND_REG	dev/mv64360reg.h	773;"	d
ETH_INTERRUPT_CAUSE_REG	dev/gt64420reg.h	723;"	d
ETH_INTERRUPT_CAUSE_REG	dev/mv64340reg.h	855;"	d
ETH_INTERRUPT_CAUSE_REG	dev/mv64360reg.h	772;"	d
ETH_INTERRUPT_EXTEND_MASK_REG	dev/gt64420reg.h	726;"	d
ETH_INTERRUPT_EXTEND_MASK_REG	dev/mv64340reg.h	858;"	d
ETH_INTERRUPT_EXTEND_MASK_REG	dev/mv64360reg.h	775;"	d
ETH_INTERRUPT_MASK_REG	dev/gt64420reg.h	725;"	d
ETH_INTERRUPT_MASK_REG	dev/mv64340reg.h	857;"	d
ETH_INTERRUPT_MASK_REG	dev/mv64360reg.h	774;"	d
ETH_MAC_ADDR_HIGH	dev/gt64420reg.h	706;"	d
ETH_MAC_ADDR_HIGH	dev/mv64340reg.h	838;"	d
ETH_MAC_ADDR_HIGH	dev/mv64360reg.h	755;"	d
ETH_MAC_ADDR_LOW	dev/gt64420reg.h	705;"	d
ETH_MAC_ADDR_LOW	dev/mv64340reg.h	837;"	d
ETH_MAC_ADDR_LOW	dev/mv64360reg.h	754;"	d
ETH_MAXIMUM_TRANSMIT_UNIT	dev/gt64420reg.h	721;"	d
ETH_MAXIMUM_TRANSMIT_UNIT	dev/mv64340reg.h	853;"	d
ETH_MAXIMUM_TRANSMIT_UNIT	dev/mv64360reg.h	770;"	d
ETH_MIB_COUNTERS_BASE	dev/gt64420reg.h	699;"	d
ETH_MIB_COUNTERS_BASE	dev/mv64340reg.h	831;"	d
ETH_MIB_COUNTERS_BASE	dev/mv64360reg.h	748;"	d
ETH_MII_SERIAL_PARAMETRS_REG	dev/gt64420reg.h	702;"	d
ETH_MII_SERIAL_PARAMETRS_REG	dev/mv64340reg.h	834;"	d
ETH_MII_SERIAL_PARAMETRS_REG	dev/mv64360reg.h	751;"	d
ETH_PHY_ADDR_REG	dev/gt64240reg.h	1046;"	d
ETH_PHY_ADDR_REG	dev/gt64260reg.h	1037;"	d
ETH_PHY_ADDR_REG	dev/gt64420reg.h	671;"	d
ETH_PHY_ADDR_REG	dev/gt96132reg.h	424;"	d
ETH_PHY_ADDR_REG	dev/mv64340reg.h	803;"	d
ETH_PHY_ADDR_REG	dev/mv64360reg.h	720;"	d
ETH_PORT_CONFIG_EXTEND_REG	dev/gt64420reg.h	701;"	d
ETH_PORT_CONFIG_EXTEND_REG	dev/mv64340reg.h	833;"	d
ETH_PORT_CONFIG_EXTEND_REG	dev/mv64360reg.h	750;"	d
ETH_PORT_CONFIG_REG	dev/gt64420reg.h	700;"	d
ETH_PORT_CONFIG_REG	dev/mv64340reg.h	832;"	d
ETH_PORT_CONFIG_REG	dev/mv64360reg.h	749;"	d
ETH_PORT_DEBUG_0_REG	dev/gt64420reg.h	731;"	d
ETH_PORT_DEBUG_0_REG	dev/mv64340reg.h	863;"	d
ETH_PORT_DEBUG_0_REG	dev/mv64360reg.h	780;"	d
ETH_PORT_DEBUG_1_REG	dev/gt64420reg.h	732;"	d
ETH_PORT_DEBUG_1_REG	dev/mv64340reg.h	864;"	d
ETH_PORT_DEBUG_1_REG	dev/mv64360reg.h	781;"	d
ETH_PORT_INTERNAL_ADDR_ERROR_REG	dev/gt64420reg.h	733;"	d
ETH_PORT_INTERNAL_ADDR_ERROR_REG	dev/mv64340reg.h	865;"	d
ETH_PORT_INTERNAL_ADDR_ERROR_REG	dev/mv64360reg.h	782;"	d
ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE	dev/gt64420reg.h	722;"	d
ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE	dev/mv64340reg.h	854;"	d
ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE	dev/mv64360reg.h	771;"	d
ETH_PORT_SERIAL_CONTROL_REG	dev/gt64420reg.h	715;"	d
ETH_PORT_SERIAL_CONTROL_REG	dev/mv64340reg.h	847;"	d
ETH_PORT_SERIAL_CONTROL_REG	dev/mv64360reg.h	764;"	d
ETH_PORT_STATUS_REG	dev/gt64420reg.h	717;"	d
ETH_PORT_STATUS_REG	dev/mv64340reg.h	849;"	d
ETH_PORT_STATUS_REG	dev/mv64360reg.h	766;"	d
ETH_PORT_TX_TOKEN_BUCKET_COUNT	dev/gt64420reg.h	777;"	d
ETH_PORT_TX_TOKEN_BUCKET_COUNT	dev/mv64340reg.h	909;"	d
ETH_PORT_TX_TOKEN_BUCKET_COUNT	dev/mv64360reg.h	826;"	d
ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG	dev/gt64420reg.h	720;"	d
ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG	dev/mv64340reg.h	852;"	d
ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG	dev/mv64360reg.h	769;"	d
ETH_RECEIVE_QUEUE_COMMAND_REG	dev/gt64420reg.h	735;"	d
ETH_RECEIVE_QUEUE_COMMAND_REG	dev/mv64340reg.h	867;"	d
ETH_RECEIVE_QUEUE_COMMAND_REG	dev/mv64360reg.h	784;"	d
ETH_RX_CURRENT_QUEUE_DESC_PTR_0	dev/gt64420reg.h	737;"	d
ETH_RX_CURRENT_QUEUE_DESC_PTR_0	dev/mv64340reg.h	869;"	d
ETH_RX_CURRENT_QUEUE_DESC_PTR_0	dev/mv64360reg.h	786;"	d
ETH_RX_CURRENT_QUEUE_DESC_PTR_1	dev/gt64420reg.h	738;"	d
ETH_RX_CURRENT_QUEUE_DESC_PTR_1	dev/mv64340reg.h	870;"	d
ETH_RX_CURRENT_QUEUE_DESC_PTR_1	dev/mv64360reg.h	787;"	d
ETH_RX_CURRENT_QUEUE_DESC_PTR_2	dev/gt64420reg.h	739;"	d
ETH_RX_CURRENT_QUEUE_DESC_PTR_2	dev/mv64340reg.h	871;"	d
ETH_RX_CURRENT_QUEUE_DESC_PTR_2	dev/mv64360reg.h	788;"	d
ETH_RX_CURRENT_QUEUE_DESC_PTR_3	dev/gt64420reg.h	740;"	d
ETH_RX_CURRENT_QUEUE_DESC_PTR_3	dev/mv64340reg.h	872;"	d
ETH_RX_CURRENT_QUEUE_DESC_PTR_3	dev/mv64360reg.h	789;"	d
ETH_RX_CURRENT_QUEUE_DESC_PTR_4	dev/gt64420reg.h	741;"	d
ETH_RX_CURRENT_QUEUE_DESC_PTR_4	dev/mv64340reg.h	873;"	d
ETH_RX_CURRENT_QUEUE_DESC_PTR_4	dev/mv64360reg.h	790;"	d
ETH_RX_CURRENT_QUEUE_DESC_PTR_5	dev/gt64420reg.h	742;"	d
ETH_RX_CURRENT_QUEUE_DESC_PTR_5	dev/mv64340reg.h	874;"	d
ETH_RX_CURRENT_QUEUE_DESC_PTR_5	dev/mv64360reg.h	791;"	d
ETH_RX_CURRENT_QUEUE_DESC_PTR_6	dev/gt64420reg.h	743;"	d
ETH_RX_CURRENT_QUEUE_DESC_PTR_6	dev/mv64340reg.h	875;"	d
ETH_RX_CURRENT_QUEUE_DESC_PTR_6	dev/mv64360reg.h	792;"	d
ETH_RX_CURRENT_QUEUE_DESC_PTR_7	dev/gt64420reg.h	744;"	d
ETH_RX_CURRENT_QUEUE_DESC_PTR_7	dev/mv64340reg.h	876;"	d
ETH_RX_CURRENT_QUEUE_DESC_PTR_7	dev/mv64360reg.h	793;"	d
ETH_RX_DISCARDED_FRAMES_COUNTER	dev/gt64420reg.h	730;"	d
ETH_RX_DISCARDED_FRAMES_COUNTER	dev/mv64340reg.h	862;"	d
ETH_RX_DISCARDED_FRAMES_COUNTER	dev/mv64360reg.h	779;"	d
ETH_RX_FIFO_URGENT_THRESHOLD_REG	dev/gt64420reg.h	727;"	d
ETH_RX_FIFO_URGENT_THRESHOLD_REG	dev/mv64340reg.h	859;"	d
ETH_RX_FIFO_URGENT_THRESHOLD_REG	dev/mv64360reg.h	776;"	d
ETH_RX_MINIMAL_FRAME_SIZE_REG	dev/gt64420reg.h	729;"	d
ETH_RX_MINIMAL_FRAME_SIZE_REG	dev/mv64340reg.h	861;"	d
ETH_RX_MINIMAL_FRAME_SIZE_REG	dev/mv64360reg.h	778;"	d
ETH_SDMA_CONFIG_REG	dev/gt64420reg.h	707;"	d
ETH_SDMA_CONFIG_REG	dev/mv64340reg.h	839;"	d
ETH_SDMA_CONFIG_REG	dev/mv64360reg.h	756;"	d
ETH_SIZE_REG_0	dev/gt64420reg.h	685;"	d
ETH_SIZE_REG_0	dev/mv64340reg.h	817;"	d
ETH_SIZE_REG_0	dev/mv64360reg.h	734;"	d
ETH_SIZE_REG_1	dev/gt64420reg.h	686;"	d
ETH_SIZE_REG_1	dev/mv64340reg.h	818;"	d
ETH_SIZE_REG_1	dev/mv64360reg.h	735;"	d
ETH_SIZE_REG_2	dev/gt64420reg.h	687;"	d
ETH_SIZE_REG_2	dev/mv64340reg.h	819;"	d
ETH_SIZE_REG_2	dev/mv64360reg.h	736;"	d
ETH_SIZE_REG_3	dev/gt64420reg.h	688;"	d
ETH_SIZE_REG_3	dev/mv64340reg.h	820;"	d
ETH_SIZE_REG_3	dev/mv64360reg.h	737;"	d
ETH_SIZE_REG_4	dev/gt64420reg.h	689;"	d
ETH_SIZE_REG_4	dev/mv64340reg.h	821;"	d
ETH_SIZE_REG_4	dev/mv64360reg.h	738;"	d
ETH_SIZE_REG_5	dev/gt64420reg.h	690;"	d
ETH_SIZE_REG_5	dev/mv64340reg.h	822;"	d
ETH_SIZE_REG_5	dev/mv64360reg.h	739;"	d
ETH_SMI_REG	dev/gt64240reg.h	1047;"	d
ETH_SMI_REG	dev/gt64260reg.h	1038;"	d
ETH_SMI_REG	dev/gt64420reg.h	672;"	d
ETH_SMI_REG	dev/gt96132reg.h	425;"	d
ETH_SMI_REG	dev/mv64340reg.h	804;"	d
ETH_SMI_REG	dev/mv64360reg.h	721;"	d
ETH_TRANSMIT_QUEUE_COMMAND_REG	dev/gt64420reg.h	718;"	d
ETH_TRANSMIT_QUEUE_COMMAND_REG	dev/mv64340reg.h	850;"	d
ETH_TRANSMIT_QUEUE_COMMAND_REG	dev/mv64360reg.h	767;"	d
ETH_TX_CURRENT_QUEUE_DESC_PTR_0	dev/gt64420reg.h	745;"	d
ETH_TX_CURRENT_QUEUE_DESC_PTR_0	dev/mv64340reg.h	877;"	d
ETH_TX_CURRENT_QUEUE_DESC_PTR_0	dev/mv64360reg.h	794;"	d
ETH_TX_CURRENT_QUEUE_DESC_PTR_1	dev/gt64420reg.h	746;"	d
ETH_TX_CURRENT_QUEUE_DESC_PTR_1	dev/mv64340reg.h	878;"	d
ETH_TX_CURRENT_QUEUE_DESC_PTR_1	dev/mv64360reg.h	795;"	d
ETH_TX_CURRENT_QUEUE_DESC_PTR_2	dev/gt64420reg.h	747;"	d
ETH_TX_CURRENT_QUEUE_DESC_PTR_2	dev/mv64340reg.h	879;"	d
ETH_TX_CURRENT_QUEUE_DESC_PTR_2	dev/mv64360reg.h	796;"	d
ETH_TX_CURRENT_QUEUE_DESC_PTR_3	dev/gt64420reg.h	748;"	d
ETH_TX_CURRENT_QUEUE_DESC_PTR_3	dev/mv64340reg.h	880;"	d
ETH_TX_CURRENT_QUEUE_DESC_PTR_3	dev/mv64360reg.h	797;"	d
ETH_TX_CURRENT_QUEUE_DESC_PTR_4	dev/gt64420reg.h	749;"	d
ETH_TX_CURRENT_QUEUE_DESC_PTR_4	dev/mv64340reg.h	881;"	d
ETH_TX_CURRENT_QUEUE_DESC_PTR_4	dev/mv64360reg.h	798;"	d
ETH_TX_CURRENT_QUEUE_DESC_PTR_5	dev/gt64420reg.h	750;"	d
ETH_TX_CURRENT_QUEUE_DESC_PTR_5	dev/mv64340reg.h	882;"	d
ETH_TX_CURRENT_QUEUE_DESC_PTR_5	dev/mv64360reg.h	799;"	d
ETH_TX_CURRENT_QUEUE_DESC_PTR_6	dev/gt64420reg.h	751;"	d
ETH_TX_CURRENT_QUEUE_DESC_PTR_6	dev/mv64340reg.h	883;"	d
ETH_TX_CURRENT_QUEUE_DESC_PTR_6	dev/mv64360reg.h	800;"	d
ETH_TX_CURRENT_QUEUE_DESC_PTR_7	dev/gt64420reg.h	752;"	d
ETH_TX_CURRENT_QUEUE_DESC_PTR_7	dev/mv64340reg.h	884;"	d
ETH_TX_CURRENT_QUEUE_DESC_PTR_7	dev/mv64360reg.h	801;"	d
ETH_TX_FIFO_URGENT_THRESHOLD_REG	dev/gt64420reg.h	728;"	d
ETH_TX_FIFO_URGENT_THRESHOLD_REG	dev/mv64340reg.h	860;"	d
ETH_TX_FIFO_URGENT_THRESHOLD_REG	dev/mv64360reg.h	777;"	d
ETH_TX_QUEUE_0_ARBITER_CONFIG	dev/gt64420reg.h	769;"	d
ETH_TX_QUEUE_0_ARBITER_CONFIG	dev/mv64340reg.h	901;"	d
ETH_TX_QUEUE_0_ARBITER_CONFIG	dev/mv64360reg.h	818;"	d
ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG	dev/gt64420reg.h	761;"	d
ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG	dev/mv64340reg.h	893;"	d
ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG	dev/mv64360reg.h	810;"	d
ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT	dev/gt64420reg.h	753;"	d
ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT	dev/mv64340reg.h	885;"	d
ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT	dev/mv64360reg.h	802;"	d
ETH_TX_QUEUE_1_ARBITER_CONFIG	dev/gt64420reg.h	770;"	d
ETH_TX_QUEUE_1_ARBITER_CONFIG	dev/mv64340reg.h	902;"	d
ETH_TX_QUEUE_1_ARBITER_CONFIG	dev/mv64360reg.h	819;"	d
ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG	dev/gt64420reg.h	762;"	d
ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG	dev/mv64340reg.h	894;"	d
ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG	dev/mv64360reg.h	811;"	d
ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT	dev/gt64420reg.h	754;"	d
ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT	dev/mv64340reg.h	886;"	d
ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT	dev/mv64360reg.h	803;"	d
ETH_TX_QUEUE_2_ARBITER_CONFIG	dev/gt64420reg.h	771;"	d
ETH_TX_QUEUE_2_ARBITER_CONFIG	dev/mv64340reg.h	903;"	d
ETH_TX_QUEUE_2_ARBITER_CONFIG	dev/mv64360reg.h	820;"	d
ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG	dev/gt64420reg.h	763;"	d
ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG	dev/mv64340reg.h	895;"	d
ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG	dev/mv64360reg.h	812;"	d
ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT	dev/gt64420reg.h	755;"	d
ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT	dev/mv64340reg.h	887;"	d
ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT	dev/mv64360reg.h	804;"	d
ETH_TX_QUEUE_3_ARBITER_CONFIG	dev/gt64420reg.h	772;"	d
ETH_TX_QUEUE_3_ARBITER_CONFIG	dev/mv64340reg.h	904;"	d
ETH_TX_QUEUE_3_ARBITER_CONFIG	dev/mv64360reg.h	821;"	d
ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG	dev/gt64420reg.h	764;"	d
ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG	dev/mv64340reg.h	896;"	d
ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG	dev/mv64360reg.h	813;"	d
ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT	dev/gt64420reg.h	756;"	d
ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT	dev/mv64340reg.h	888;"	d
ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT	dev/mv64360reg.h	805;"	d
ETH_TX_QUEUE_4_ARBITER_CONFIG	dev/gt64420reg.h	773;"	d
ETH_TX_QUEUE_4_ARBITER_CONFIG	dev/mv64340reg.h	905;"	d
ETH_TX_QUEUE_4_ARBITER_CONFIG	dev/mv64360reg.h	822;"	d
ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG	dev/gt64420reg.h	765;"	d
ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG	dev/mv64340reg.h	897;"	d
ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG	dev/mv64360reg.h	814;"	d
ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT	dev/gt64420reg.h	757;"	d
ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT	dev/mv64340reg.h	889;"	d
ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT	dev/mv64360reg.h	806;"	d
ETH_TX_QUEUE_5_ARBITER_CONFIG	dev/gt64420reg.h	774;"	d
ETH_TX_QUEUE_5_ARBITER_CONFIG	dev/mv64340reg.h	906;"	d
ETH_TX_QUEUE_5_ARBITER_CONFIG	dev/mv64360reg.h	823;"	d
ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG	dev/gt64420reg.h	766;"	d
ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG	dev/mv64340reg.h	898;"	d
ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG	dev/mv64360reg.h	815;"	d
ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT	dev/gt64420reg.h	758;"	d
ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT	dev/mv64340reg.h	890;"	d
ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT	dev/mv64360reg.h	807;"	d
ETH_TX_QUEUE_6_ARBITER_CONFIG	dev/gt64420reg.h	775;"	d
ETH_TX_QUEUE_6_ARBITER_CONFIG	dev/mv64340reg.h	907;"	d
ETH_TX_QUEUE_6_ARBITER_CONFIG	dev/mv64360reg.h	824;"	d
ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG	dev/gt64420reg.h	767;"	d
ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG	dev/mv64340reg.h	899;"	d
ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG	dev/mv64360reg.h	816;"	d
ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT	dev/gt64420reg.h	759;"	d
ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT	dev/mv64340reg.h	891;"	d
ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT	dev/mv64360reg.h	808;"	d
ETH_TX_QUEUE_7_ARBITER_CONFIG	dev/gt64420reg.h	776;"	d
ETH_TX_QUEUE_7_ARBITER_CONFIG	dev/mv64340reg.h	908;"	d
ETH_TX_QUEUE_7_ARBITER_CONFIG	dev/mv64360reg.h	825;"	d
ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG	dev/gt64420reg.h	768;"	d
ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG	dev/mv64340reg.h	900;"	d
ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG	dev/mv64360reg.h	817;"	d
ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT	dev/gt64420reg.h	760;"	d
ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT	dev/mv64340reg.h	892;"	d
ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT	dev/mv64360reg.h	809;"	d
ETH_TX_QUEUE_FIXED_PRIORITY	dev/gt64420reg.h	719;"	d
ETH_TX_QUEUE_FIXED_PRIORITY	dev/mv64340reg.h	851;"	d
ETH_TX_QUEUE_FIXED_PRIORITY	dev/mv64360reg.h	768;"	d
ETH_UNIT_DEFAULTID_REG	dev/gt64420reg.h	674;"	d
ETH_UNIT_DEFAULTID_REG	dev/mv64340reg.h	806;"	d
ETH_UNIT_DEFAULTID_REG	dev/mv64360reg.h	723;"	d
ETH_UNIT_DEFAULT_ADDR_REG	dev/gt64420reg.h	673;"	d
ETH_UNIT_DEFAULT_ADDR_REG	dev/mv64340reg.h	805;"	d
ETH_UNIT_DEFAULT_ADDR_REG	dev/mv64360reg.h	722;"	d
ETH_UNIT_ERROR_ADDR_REG	dev/gt64420reg.h	678;"	d
ETH_UNIT_ERROR_ADDR_REG	dev/mv64340reg.h	810;"	d
ETH_UNIT_ERROR_ADDR_REG	dev/mv64360reg.h	727;"	d
ETH_UNIT_INTERNAL_USE_REG	dev/gt64420reg.h	677;"	d
ETH_UNIT_INTERNAL_USE_REG	dev/mv64340reg.h	809;"	d
ETH_UNIT_INTERNAL_USE_REG	dev/mv64360reg.h	726;"	d
ETH_UNIT_INTERRUPT_CAUSE_REG	dev/gt64420reg.h	675;"	d
ETH_UNIT_INTERRUPT_CAUSE_REG	dev/mv64340reg.h	807;"	d
ETH_UNIT_INTERRUPT_CAUSE_REG	dev/mv64360reg.h	724;"	d
ETH_UNIT_INTERRUPT_MASK_REG	dev/gt64420reg.h	676;"	d
ETH_UNIT_INTERRUPT_MASK_REG	dev/mv64340reg.h	808;"	d
ETH_UNIT_INTERRUPT_MASK_REG	dev/mv64360reg.h	725;"	d
ETH_VLAN_ETHERTYPE_REG	dev/gt64420reg.h	704;"	d
ETH_VLAN_ETHERTYPE_REG	dev/mv64340reg.h	836;"	d
ETH_VLAN_ETHERTYPE_REG	dev/mv64360reg.h	753;"	d
ETH_VLAN_PRIORITY_TAG_TO_PRIORITY	dev/gt64420reg.h	716;"	d
ETH_VLAN_PRIORITY_TAG_TO_PRIORITY	dev/mv64340reg.h	848;"	d
ETH_VLAN_PRIORITY_TAG_TO_PRIORITY	dev/mv64360reg.h	765;"	d
ETIMEDOUT	include/errno.h	129;"	d
ETOOMANYREFS	include/errno.h	128;"	d
ETOOSMALL	include/linux/errno.h	19;"	d
ETXTBSY	include/errno.h	84;"	d
EUNDEF	include/arpa/tftp.h	74;"	d
EUSERS	include/errno.h	146;"	d
EWOULDBLOCK	include/errno.h	100;"	d
EXC_BAD	include/pmon.h	94;"	d
EXC_BPT	include/pmon.h	96;"	d
EXC_INT	include/pmon.h	95;"	d
EXC_RES	include/pmon.h	99;"	d
EXC_TRC	include/pmon.h	97;"	d
EXC_WTCH	include/pmon.h	98;"	d
EXDEV	include/errno.h	75;"	d
EXECFLAGS_NOAUTO	include/exec.h	46;"	d
EXECFLAGS_NONE	include/exec.h	45;"	d
EXIT_FAILURE	include/stdlib.h	83;"	d
EXIT_SUCCESS	include/stdlib.h	84;"	d
EXPANSION_ROM_BASE_ADDRESS_REGISTER	dev/gt96132reg.h	350;"	d
EXPECTED_DEVICE	dev/flash_st.c	79;"	d	file:
EXPERT	include/pmon.h	396;"	d
EXPERT	tgt_env.c	9;"	d	file:
EXPORT_SYMBOL	include/linux/module.h	1;"	d
EXTENDED_DRAM_MODE	dev/mv64360reg.h	275;"	d
ExecId	include/exec.h	/^typedef unsigned long ExecId;$/;"	t
ExecType	include/exec.h	/^typedef struct ExecType {$/;"	s
ExecType	include/exec.h	/^} ExecType;$/;"	t	typeref:struct:ExecType
FALSE	include/tgt/bonito.h	4;"	d
FAR	include/linux/zconf.h	70;"	d
FD_CLR	include/types.h	206;"	d
FD_COPY	include/types.h	209;"	d
FD_COPY	include/types.h	212;"	d
FD_ISSET	include/types.h	207;"	d
FD_SET	include/types.h	205;"	d
FD_SETSIZE	include/types.h	195;"	d
FD_ZERO	include/types.h	210;"	d
FD_ZERO	include/types.h	213;"	d
FIFO_DMA_MODE	dev/ns16550.h	127;"	d
FIFO_ENABLE	dev/ns16550.h	124;"	d
FIFO_RCV_RST	dev/ns16550.h	125;"	d
FIFO_TRIGGER_1	dev/ns16550.h	128;"	d
FIFO_TRIGGER_14	dev/ns16550.h	131;"	d
FIFO_TRIGGER_4	dev/ns16550.h	129;"	d
FIFO_TRIGGER_8	dev/ns16550.h	130;"	d
FIFO_XMT_RST	dev/ns16550.h	126;"	d
FILE	include/stdio.h	/^typedef struct FILE {$/;"	s
FILE	include/stdio.h	/^} FILE;$/;"	t	typeref:struct:FILE
FILENAMESIZE	include/url.h	43;"	d
FLASH_SIZE	dev/flash_st.c	80;"	d	file:
FLEXTDM_AUX_CHANNELA_RX_REGISTER	dev/gt64240reg.h	1225;"	d
FLEXTDM_AUX_CHANNELA_RX_REGISTER	dev/gt64260reg.h	1216;"	d
FLEXTDM_AUX_CHANNELA_RX_REGISTER	dev/gt64420reg.h	961;"	d
FLEXTDM_AUX_CHANNELA_RX_REGISTER	dev/mv64340reg.h	1075;"	d
FLEXTDM_AUX_CHANNELA_TX_REGISTER	dev/gt64240reg.h	1224;"	d
FLEXTDM_AUX_CHANNELA_TX_REGISTER	dev/gt64260reg.h	1215;"	d
FLEXTDM_AUX_CHANNELA_TX_REGISTER	dev/gt64420reg.h	960;"	d
FLEXTDM_AUX_CHANNELA_TX_REGISTER	dev/mv64340reg.h	1074;"	d
FLEXTDM_AUX_CHANNELB_RX_REGISTER	dev/gt64240reg.h	1227;"	d
FLEXTDM_AUX_CHANNELB_RX_REGISTER	dev/gt64260reg.h	1218;"	d
FLEXTDM_AUX_CHANNELB_RX_REGISTER	dev/gt64420reg.h	963;"	d
FLEXTDM_AUX_CHANNELB_RX_REGISTER	dev/mv64340reg.h	1077;"	d
FLEXTDM_AUX_CHANNELB_TX_REGISTER	dev/gt64240reg.h	1226;"	d
FLEXTDM_AUX_CHANNELB_TX_REGISTER	dev/gt64260reg.h	1217;"	d
FLEXTDM_AUX_CHANNELB_TX_REGISTER	dev/gt64420reg.h	962;"	d
FLEXTDM_AUX_CHANNELB_TX_REGISTER	dev/mv64340reg.h	1076;"	d
FLEXTDM_CONFIGURATION_REGISTER	dev/gt64240reg.h	1223;"	d
FLEXTDM_CONFIGURATION_REGISTER	dev/gt64260reg.h	1214;"	d
FLEXTDM_CONFIGURATION_REGISTER	dev/gt64420reg.h	959;"	d
FLEXTDM_CONFIGURATION_REGISTER	dev/mv64340reg.h	1073;"	d
FLEXTDM_RECEIVE_READ_POINTER	dev/gt64240reg.h	1222;"	d
FLEXTDM_RECEIVE_READ_POINTER	dev/gt64260reg.h	1213;"	d
FLEXTDM_RECEIVE_READ_POINTER	dev/gt64420reg.h	958;"	d
FLEXTDM_RECEIVE_READ_POINTER	dev/mv64340reg.h	1072;"	d
FLEXTDM_TRANSMIT_READ_POINTER	dev/gt64240reg.h	1221;"	d
FLEXTDM_TRANSMIT_READ_POINTER	dev/gt64260reg.h	1212;"	d
FLEXTDM_TRANSMIT_READ_POINTER	dev/gt64420reg.h	957;"	d
FLEXTDM_TRANSMIT_READ_POINTER	dev/mv64340reg.h	1071;"	d
FLEX_TDM_CAUSE_REGISTER	dev/gt96132reg.h	316;"	d
FLEX_TDM_MASK_REGISTER	dev/gt96132reg.h	317;"	d
FLTDM1_AUX_CHANB_RX_REG	dev/gt96132reg.h	743;"	d
FLTDM1_AUX_CHANB_TX_REG	dev/gt96132reg.h	742;"	d
FLTDM2_AUX_CHANA_RX_REG	dev/gt96132reg.h	756;"	d
FLTDM2_AUX_CHANA_TX_REG	dev/gt96132reg.h	755;"	d
FLTDM2_AUX_CHANB_RX_REG	dev/gt96132reg.h	758;"	d
FLTDM2_AUX_CHANB_TX_REG	dev/gt96132reg.h	757;"	d
FLTDM2_CONFIG_REG	dev/gt96132reg.h	754;"	d
FLTDM2_RDPR2_BLK0_BASE	dev/gt96132reg.h	748;"	d
FLTDM2_RDPR2_BLK1_BASE	dev/gt96132reg.h	749;"	d
FLTDM2_RDPR2_BLK2_BASE	dev/gt96132reg.h	750;"	d
FLTDM2_RDPR2_BLK3_BASE	dev/gt96132reg.h	751;"	d
FLTDM2_RX_READ_PTR	dev/gt96132reg.h	753;"	d
FLTDM2_TDPR2_BLK0_BASE	dev/gt96132reg.h	744;"	d
FLTDM2_TDPR2_BLK1_BASE	dev/gt96132reg.h	745;"	d
FLTDM2_TDPR2_BLK2_BASE	dev/gt96132reg.h	746;"	d
FLTDM2_TDPR2_BLK3_BASE	dev/gt96132reg.h	747;"	d
FLTDM2_TX_READ_PTR	dev/gt96132reg.h	752;"	d
FLTDM3_TDPR3_BLK0_BASE	dev/gt96132reg.h	759;"	d
FLTDM3_TDPR3_BLK1_BASE	dev/gt96132reg.h	760;"	d
FLTDM3_TDPR3_BLK2_BASE	dev/gt96132reg.h	761;"	d
FLTDM3_TDPR3_BLK3_BASE	dev/gt96132reg.h	762;"	d
FL_AUTOSEL	include/pflash.h	109;"	d
FL_BUS_16	include/pflash.h	78;"	d
FL_BUS_16_ON_64	include/pflash.h	82;"	d
FL_BUS_32	include/pflash.h	79;"	d
FL_BUS_64	include/pflash.h	80;"	d
FL_BUS_8	include/pflash.h	77;"	d
FL_BUS_8_ON_64	include/pflash.h	81;"	d
FL_CAP_A7	include/pflash.h	62;"	d
FL_CAP_DE	include/pflash.h	61;"	d
FL_CHIP	include/pflash.h	113;"	d
FL_ERASE	include/pflash.h	111;"	d
FL_ERASE_CHIP	include/pflash.h	112;"	d
FL_INT_BE	include/pflash.h	132;"	d
FL_INT_BUSY	include/pflash.h	134;"	d
FL_INT_CLR	include/pflash.h	135;"	d
FL_INT_CNF	include/pflash.h	133;"	d
FL_INT_FCE	include/pflash.h	130;"	d
FL_INT_FCE_A7	include/pflash.h	131;"	d
FL_INT_PGM	include/pflash.h	137;"	d
FL_INT_READ	include/pflash.h	136;"	d
FL_PGM	include/pflash.h	115;"	d
FL_PROTO_AMD	include/pflash.h	56;"	d
FL_PROTO_INT	include/pflash.h	55;"	d
FL_PROTO_SST	include/pflash.h	57;"	d
FL_PROTO_ST	include/pflash.h	58;"	d
FL_PROTO_WINBOND	include/pflash.h	59;"	d
FL_RESET	include/pflash.h	110;"	d
FL_RESUME	include/pflash.h	117;"	d
FL_SECT	include/pflash.h	114;"	d
FL_SUSPEND	include/pflash.h	116;"	d
FMT_CENTER	include/string.h	111;"	d
FMT_LJUST	include/string.h	109;"	d
FMT_RJUST	include/string.h	108;"	d
FMT_RJUST0	include/string.h	110;"	d
FORMERR	include/arpa/nameser.h	142;"	d
FORM_C	include/arpa/ftp.h	70;"	d
FORM_N	include/arpa/ftp.h	68;"	d
FORM_T	include/arpa/ftp.h	69;"	d
FROMBCD	dev/mc146818.c	65;"	d	file:
FS_DEV	include/file.h	55;"	d
FS_FILE	include/file.h	57;"	d
FS_MEM	include/file.h	56;"	d
FS_NET	include/file.h	53;"	d
FS_NULL	include/file.h	51;"	d
FS_SOCK	include/file.h	54;"	d
FS_TTY	include/file.h	52;"	d
FTDM_CAUSE_REGISTER	dev/gt64240reg.h	1231;"	d
FTDM_CAUSE_REGISTER	dev/gt64260reg.h	1222;"	d
FTDM_CAUSE_REGISTER	dev/gt64420reg.h	967;"	d
FTDM_CAUSE_REGISTER	dev/mv64340reg.h	1081;"	d
FTDM_MASK_REGISTER	dev/gt64240reg.h	1232;"	d
FTDM_MASK_REGISTER	dev/gt64260reg.h	1223;"	d
FTDM_MASK_REGISTER	dev/gt64420reg.h	968;"	d
FTDM_MASK_REGISTER	dev/mv64340reg.h	1082;"	d
FXTDM0_AUX_CHANA_RX_REG	dev/gt96132reg.h	726;"	d
FXTDM0_AUX_CHANA_TX_REG	dev/gt96132reg.h	725;"	d
FXTDM0_AUX_CHANB_RX_REG	dev/gt96132reg.h	728;"	d
FXTDM0_AUX_CHANB_TX_REG	dev/gt96132reg.h	727;"	d
FXTDM0_CONFIG_REG	dev/gt96132reg.h	724;"	d
FXTDM0_RDPR0_BLK0_BASE	dev/gt96132reg.h	718;"	d
FXTDM0_RDPR0_BLK1_BASE	dev/gt96132reg.h	719;"	d
FXTDM0_RDPR0_BLK2_BASE	dev/gt96132reg.h	720;"	d
FXTDM0_RDPR0_BLK3_BASE	dev/gt96132reg.h	721;"	d
FXTDM0_RX_READ_PTR	dev/gt96132reg.h	723;"	d
FXTDM0_TDPR0_BLK0_BASE	dev/gt96132reg.h	714;"	d
FXTDM0_TDPR0_BLK1_BASE	dev/gt96132reg.h	715;"	d
FXTDM0_TDPR0_BLK2_BASE	dev/gt96132reg.h	716;"	d
FXTDM0_TDPR0_BLK3_BASE	dev/gt96132reg.h	717;"	d
FXTDM0_TX_READ_PTR	dev/gt96132reg.h	722;"	d
FXTDM1_AUX	dev/gt96132reg.h	741;"	d
FXTDM1_AUX_CHANA_TX_REG	dev/gt96132reg.h	740;"	d
FXTDM1_CONFIG_REG	dev/gt96132reg.h	739;"	d
FXTDM1_RDPR1_BLK0_BASE	dev/gt96132reg.h	733;"	d
FXTDM1_RDPR1_BLK1_BASE	dev/gt96132reg.h	734;"	d
FXTDM1_RDPR1_BLK2_BASE	dev/gt96132reg.h	735;"	d
FXTDM1_RDPR1_BLK3_BASE	dev/gt96132reg.h	736;"	d
FXTDM1_RX_READ_PTR	dev/gt96132reg.h	738;"	d
FXTDM1_TDPR1_BLK0_BASE	dev/gt96132reg.h	729;"	d
FXTDM1_TDPR1_BLK1_BASE	dev/gt96132reg.h	730;"	d
FXTDM1_TDPR1_BLK2_BASE	dev/gt96132reg.h	731;"	d
FXTDM1_TDPR1_BLK3_BASE	dev/gt96132reg.h	732;"	d
FXTDM1_TX_READ_PTR	dev/gt96132reg.h	737;"	d
FXTDM3_AUX_CHANA_RX_REG	dev/gt96132reg.h	771;"	d
FXTDM3_AUX_CHANA_TX_REG	dev/gt96132reg.h	770;"	d
FXTDM3_AUX_CHANB_RX_REG	dev/gt96132reg.h	773;"	d
FXTDM3_AUX_CHANB_TX_REG	dev/gt96132reg.h	772;"	d
FXTDM3_CONFIG_REG	dev/gt96132reg.h	769;"	d
FXTDM3_RDPR3_BLK0_BASE	dev/gt96132reg.h	763;"	d
FXTDM3_RDPR3_BLK1_BASE	dev/gt96132reg.h	764;"	d
FXTDM3_RDPR3_BLK2_BASE	dev/gt96132reg.h	765;"	d
FXTDM3_RDPR3_BLK3_BASE	dev/gt96132reg.h	766;"	d
FXTDM3_RX_READ_PTR	dev/gt96132reg.h	768;"	d
FXTDM3_TX_READ_PTR	dev/gt96132reg.h	767;"	d
F_LOCK	include/unistd.h	203;"	d
F_TEST	include/unistd.h	205;"	d
F_TLOCK	include/unistd.h	204;"	d
F_ULOCK	include/unistd.h	202;"	d
File	include/file.h	/^typedef struct File {$/;"	s
File	include/file.h	/^} File;$/;"	t	typeref:struct:File
FileSystem	include/file.h	/^typedef struct FileSystem {$/;"	s
FileSystem	include/file.h	/^} FileSystem;$/;"	t	typeref:struct:FileSystem
Func	include/pmon.h	/^typedef int     Func __P((void));$/;"	t
GA	include/arpa/telnet.h	51;"	d
GETHID1	include/powerpc.h	126;"	d
GETINTR	include/termio.h	13;"	d
GETLONG	include/arpa/nameser.h	366;"	d
GETSHORT	include/arpa/nameser.h	358;"	d
GETTERM	include/termio.h	14;"	d
GPP0_CAUSE_REGISTER	dev/gt96132reg.h	320;"	d
GPP0_MASK_REGISTER	dev/gt96132reg.h	321;"	d
GPP1_CAUSE_REGISTER	dev/gt96132reg.h	322;"	d
GPP1_MASK_REGISTER	dev/gt96132reg.h	323;"	d
GPP2_CAUSE_REGISTER	dev/gt96132reg.h	324;"	d
GPP2_MASK_REGISTER	dev/gt96132reg.h	325;"	d
GPP3_CAUSE_REGISTER	dev/gt96132reg.h	326;"	d
GPP3_MASK_REGISTER	dev/gt96132reg.h	327;"	d
GPP_CONFIG0	dev/gt96132reg.h	797;"	d
GPP_CONFIG1	dev/gt96132reg.h	798;"	d
GPP_CONFIG2	dev/gt96132reg.h	799;"	d
GPP_CONFIG3	dev/gt96132reg.h	800;"	d
GPP_DATA0	dev/gt96132reg.h	805;"	d
GPP_DATA1	dev/gt96132reg.h	806;"	d
GPP_DATA2	dev/gt96132reg.h	807;"	d
GPP_DATA3	dev/gt96132reg.h	808;"	d
GPP_INTERRUPT_CAUSE	dev/gt64240reg.h	1242;"	d
GPP_INTERRUPT_CAUSE	dev/gt64260reg.h	1233;"	d
GPP_INTERRUPT_CAUSE	dev/gt64420reg.h	978;"	d
GPP_INTERRUPT_CAUSE	dev/mv64340reg.h	1094;"	d
GPP_INTERRUPT_CAUSE	dev/mv64360reg.h	1049;"	d
GPP_INTERRUPT_MASK	dev/gt64240reg.h	1243;"	d
GPP_INTERRUPT_MASK	dev/gt64260reg.h	1234;"	d
GPP_INTERRUPT_MASK	dev/gt64420reg.h	979;"	d
GPP_INTERRUPT_MASK	dev/mv64340reg.h	1095;"	d
GPP_INTERRUPT_MASK0	dev/mv64360reg.h	1050;"	d
GPP_INTERRUPT_MASK1	dev/mv64360reg.h	1051;"	d
GPP_IO0	dev/gt96132reg.h	801;"	d
GPP_IO1	dev/gt96132reg.h	802;"	d
GPP_IO2	dev/gt96132reg.h	803;"	d
GPP_IO3	dev/gt96132reg.h	804;"	d
GPP_IO_CONTROL	dev/gt64240reg.h	1239;"	d
GPP_IO_CONTROL	dev/gt64260reg.h	1230;"	d
GPP_IO_CONTROL	dev/gt64420reg.h	975;"	d
GPP_IO_CONTROL	dev/mv64340reg.h	1091;"	d
GPP_IO_CONTROL	dev/mv64360reg.h	1046;"	d
GPP_LEVEL0	dev/gt96132reg.h	809;"	d
GPP_LEVEL1	dev/gt96132reg.h	810;"	d
GPP_LEVEL2	dev/gt96132reg.h	811;"	d
GPP_LEVEL3	dev/gt96132reg.h	812;"	d
GPP_LEVEL_CNTRL	dev/gt64240reg.h	138;"	d
GPP_LEVEL_CNTRL	dev/gt64260reg.h	129;"	d
GPP_LEVEL_CNTRL	dev/gt64420reg.h	122;"	d
GPP_LEVEL_CONTROL	dev/gt64240reg.h	1240;"	d
GPP_LEVEL_CONTROL	dev/gt64260reg.h	1231;"	d
GPP_LEVEL_CONTROL	dev/gt64420reg.h	976;"	d
GPP_LEVEL_CONTROL	dev/mv64340reg.h	1092;"	d
GPP_LEVEL_CONTROL	dev/mv64360reg.h	1047;"	d
GPP_VALUE	dev/gt64240reg.h	1241;"	d
GPP_VALUE	dev/gt64260reg.h	1232;"	d
GPP_VALUE	dev/gt64420reg.h	977;"	d
GPP_VALUE	dev/mv64340reg.h	1093;"	d
GPP_VALUE	dev/mv64360reg.h	1048;"	d
GPP_VALUE_CLEAR	dev/mv64360reg.h	1053;"	d
GPP_VALUE_SET	dev/mv64360reg.h	1052;"	d
GT64120	dev/gt64120reg.h	47;"	d
GT64120	dev/gt64120reg.h	49;"	d
GT64120_BASE_DEFAULT	dev/gt64120reg.h	41;"	d
GT96132	dev/gt96132reg.h	41;"	d
GT_BASE_ADDR	dev/gt64240reg.h	62;"	d
GT_BASE_ADDR	dev/gt64260reg.h	54;"	d
GT_BASE_ADDR	dev/gt64260reg.h	56;"	d
GT_BASE_ADDR	dev/gt64420reg.h	62;"	d
GT_BASE_ADDR	dev/gt64420reg.h	66;"	d
GT_BASE_ADDR	dev/gt96132reg.h	60;"	d
GT_BASE_ADDR	dev/gt96132reg.h	62;"	d
GT_BASE_ADDR	dev/mv64340reg.h	56;"	d
GT_BASE_ADDR	dev/mv64360reg.h	51;"	d
GT_BASE_ADDR_DEFAULT	dev/gt64240reg.h	65;"	d
GT_BASE_ADDR_DEFAULT	dev/gt64260reg.h	60;"	d
GT_BASE_ADDR_DEFAULT	dev/gt64420reg.h	69;"	d
GT_BASE_ADDR_DEFAULT	dev/gt96132reg.h	64;"	d
GT_BASE_ADDR_DEFAULT	dev/mv64340reg.h	57;"	d
GT_BASE_ADDR_DEFAULT	dev/mv64360reg.h	52;"	d
GT_BOOT_PAR	dev/gt64240reg.h	101;"	d
GT_BOOT_PAR	dev/gt64260reg.h	92;"	d
GT_BOOT_PAR	dev/gt64420reg.h	99;"	d
GT_BOOT_PAR	dev/gt96132reg.h	170;"	d
GT_BOOT_PAR	dev/mv64340reg.h	101;"	d
GT_BOOT_PAR	dev/mv64360reg.h	75;"	d
GT_CPU_CFG	dev/gt64120reg.h	56;"	d
GT_CPU_CFG_CPUWrRate	dev/gt64120reg.h	66;"	d
GT_CPU_CFG_CacheOpMap	dev/gt64120reg.h	58;"	d
GT_CPU_CFG_CachePres	dev/gt64120reg.h	59;"	d
GT_CPU_CFG_Endianess	dev/gt64120reg.h	62;"	d
GT_CPU_CFG_ExtHitDLY	dev/gt64120reg.h	65;"	d
GT_CPU_CFG_ExtL2Pres	dev/gt64120reg.h	64;"	d
GT_CPU_CFG_IntRegEnd	dev/gt64120reg.h	63;"	d
GT_CPU_CFG_MultiGT	dev/gt64120reg.h	68;"	d
GT_CPU_CFG_StopRetry	dev/gt64120reg.h	67;"	d
GT_CPU_CFG_SysADCVld	dev/gt64120reg.h	69;"	d
GT_CPU_CFG_VRXMode	dev/gt64120reg.h	60;"	d
GT_CPU_CFG_WriteMode	dev/gt64120reg.h	61;"	d
GT_DDAS_BOOTCSHI	dev/gt64120reg.h	143;"	d
GT_DDAS_BOOTCSLO	dev/gt64120reg.h	142;"	d
GT_DDAS_CS0HI	dev/gt64120reg.h	135;"	d
GT_DDAS_CS0LO	dev/gt64120reg.h	134;"	d
GT_DDAS_CS1HI	dev/gt64120reg.h	137;"	d
GT_DDAS_CS1LO	dev/gt64120reg.h	136;"	d
GT_DDAS_CS2HI	dev/gt64120reg.h	139;"	d
GT_DDAS_CS2LO	dev/gt64120reg.h	138;"	d
GT_DDAS_CS3HI	dev/gt64120reg.h	141;"	d
GT_DDAS_CS3LO	dev/gt64120reg.h	140;"	d
GT_DDAS_ERROR	dev/gt64120reg.h	144;"	d
GT_DDAS_HIMASK_High	dev/gt64120reg.h	148;"	d
GT_DDAS_HISHIFT_High	dev/gt64120reg.h	149;"	d
GT_DDAS_LOMASK_Low	dev/gt64120reg.h	146;"	d
GT_DDAS_LOSHIFT_Low	dev/gt64120reg.h	147;"	d
GT_DDAS_RAS0HI	dev/gt64120reg.h	127;"	d
GT_DDAS_RAS0LO	dev/gt64120reg.h	126;"	d
GT_DDAS_RAS1HI	dev/gt64120reg.h	129;"	d
GT_DDAS_RAS1LO	dev/gt64120reg.h	128;"	d
GT_DDAS_RAS2HI	dev/gt64120reg.h	131;"	d
GT_DDAS_RAS2LO	dev/gt64120reg.h	130;"	d
GT_DDAS_RAS3HI	dev/gt64120reg.h	133;"	d
GT_DDAS_RAS3LO	dev/gt64120reg.h	132;"	d
GT_DEV0_PAR	dev/gt64240reg.h	97;"	d
GT_DEV0_PAR	dev/gt64260reg.h	88;"	d
GT_DEV0_PAR	dev/gt64420reg.h	95;"	d
GT_DEV0_PAR	dev/gt96132reg.h	166;"	d
GT_DEV0_PAR	dev/mv64340reg.h	97;"	d
GT_DEV1_PAR	dev/gt64240reg.h	98;"	d
GT_DEV1_PAR	dev/gt64260reg.h	89;"	d
GT_DEV1_PAR	dev/gt64420reg.h	96;"	d
GT_DEV1_PAR	dev/gt96132reg.h	167;"	d
GT_DEV1_PAR	dev/mv64340reg.h	98;"	d
GT_DEV2_PAR	dev/gt64240reg.h	99;"	d
GT_DEV2_PAR	dev/gt64260reg.h	90;"	d
GT_DEV2_PAR	dev/gt64420reg.h	97;"	d
GT_DEV2_PAR	dev/gt96132reg.h	168;"	d
GT_DEV2_PAR	dev/mv64340reg.h	99;"	d
GT_DEV3_PAR	dev/gt64240reg.h	100;"	d
GT_DEV3_PAR	dev/gt64260reg.h	91;"	d
GT_DEV3_PAR	dev/gt64420reg.h	98;"	d
GT_DEV3_PAR	dev/gt96132reg.h	169;"	d
GT_DEV3_PAR	dev/mv64340reg.h	100;"	d
GT_DEVPAR_ALEtoWr	dev/gt64120reg.h	265;"	d
GT_DEVPAR_ALEtoWr	dev/gt64240reg.h	72;"	d
GT_DEVPAR_ALEtoWr	dev/gt64420reg.h	76;"	d
GT_DEVPAR_ALEtoWr	dev/mv64340reg.h	64;"	d
GT_DEVPAR_ALEtoWrMASK	dev/gt64120reg.h	263;"	d
GT_DEVPAR_ALEtoWrSHIFT	dev/gt64120reg.h	264;"	d
GT_DEVPAR_AccToFirst	dev/gt64120reg.h	259;"	d
GT_DEVPAR_AccToFirst	dev/gt64240reg.h	70;"	d
GT_DEVPAR_AccToFirst	dev/gt64420reg.h	74;"	d
GT_DEVPAR_AccToFirst	dev/mv64340reg.h	62;"	d
GT_DEVPAR_AccToFirstMASK	dev/gt64120reg.h	257;"	d
GT_DEVPAR_AccToFirstSHIFT	dev/gt64120reg.h	258;"	d
GT_DEVPAR_AccToNext	dev/gt64120reg.h	262;"	d
GT_DEVPAR_AccToNext	dev/gt64240reg.h	71;"	d
GT_DEVPAR_AccToNext	dev/gt64420reg.h	75;"	d
GT_DEVPAR_AccToNext	dev/mv64340reg.h	63;"	d
GT_DEVPAR_AccToNextMASK	dev/gt64120reg.h	260;"	d
GT_DEVPAR_AccToNextSHIFT	dev/gt64120reg.h	261;"	d
GT_DEVPAR_BANK0	dev/gt64120reg.h	248;"	d
GT_DEVPAR_BANK1	dev/gt64120reg.h	249;"	d
GT_DEVPAR_BANK2	dev/gt64120reg.h	250;"	d
GT_DEVPAR_BANK3	dev/gt64120reg.h	251;"	d
GT_DEVPAR_BOOT	dev/gt64120reg.h	252;"	d
GT_DEVPAR_BaddrSkew0	dev/mv64340reg.h	71;"	d
GT_DEVPAR_BaddrSkew1	dev/mv64340reg.h	72;"	d
GT_DEVPAR_BaddrSkew2	dev/mv64340reg.h	73;"	d
GT_DEVPAR_BaddrSkewMASK	dev/mv64340reg.h	74;"	d
GT_DEVPAR_DMAFlyBy_BCS	dev/gt64120reg.h	291;"	d
GT_DEVPAR_DMAFlyBy_CS	dev/gt64120reg.h	292;"	d
GT_DEVPAR_DPEnDisable	dev/mv64340reg.h	75;"	d
GT_DEVPAR_DPEnEnable	dev/mv64340reg.h	76;"	d
GT_DEVPAR_DevLoc	dev/gt64120reg.h	278;"	d
GT_DEVPAR_DevLocEven	dev/gt64120reg.h	279;"	d
GT_DEVPAR_DevLocOdd	dev/gt64120reg.h	280;"	d
GT_DEVPAR_DevWidth16	dev/gt64120reg.h	275;"	d
GT_DEVPAR_DevWidth16	dev/gt64240reg.h	76;"	d
GT_DEVPAR_DevWidth16	dev/gt64420reg.h	80;"	d
GT_DEVPAR_DevWidth16	dev/mv64340reg.h	68;"	d
GT_DEVPAR_DevWidth32	dev/gt64120reg.h	276;"	d
GT_DEVPAR_DevWidth32	dev/gt64240reg.h	77;"	d
GT_DEVPAR_DevWidth32	dev/gt64420reg.h	81;"	d
GT_DEVPAR_DevWidth32	dev/mv64340reg.h	69;"	d
GT_DEVPAR_DevWidth64	dev/gt64120reg.h	277;"	d
GT_DEVPAR_DevWidth64	dev/gt64240reg.h	78;"	d
GT_DEVPAR_DevWidth64	dev/gt64420reg.h	82;"	d
GT_DEVPAR_DevWidth8	dev/gt64120reg.h	274;"	d
GT_DEVPAR_DevWidth8	dev/gt64240reg.h	75;"	d
GT_DEVPAR_DevWidth8	dev/gt64260reg.h	75;"	d
GT_DEVPAR_DevWidth8	dev/gt64420reg.h	79;"	d
GT_DEVPAR_DevWidth8	dev/mv64340reg.h	67;"	d
GT_DEVPAR_DevWidthMASK	dev/gt64120reg.h	272;"	d
GT_DEVPAR_DevWidthMASK	dev/gt64240reg.h	79;"	d
GT_DEVPAR_DevWidthMASK	dev/gt64260reg.h	74;"	d
GT_DEVPAR_DevWidthMASK	dev/gt64420reg.h	83;"	d
GT_DEVPAR_DevWidthMASK	dev/mv64340reg.h	70;"	d
GT_DEVPAR_DevWidthSHIFT	dev/gt64120reg.h	273;"	d
GT_DEVPAR_LatchFunct	dev/gt64120reg.h	281;"	d
GT_DEVPAR_LatchFunctEnable	dev/gt64120reg.h	283;"	d
GT_DEVPAR_LatchFunctTransparent	dev/gt64120reg.h	282;"	d
GT_DEVPAR_Parity	dev/gt64120reg.h	284;"	d
GT_DEVPAR_ParityDisable	dev/gt64120reg.h	285;"	d
GT_DEVPAR_ParityEnable	dev/gt64120reg.h	286;"	d
GT_DEVPAR_Reserved	dev/gt64120reg.h	288;"	d
GT_DEVPAR_Reserved	dev/gt64240reg.h	81;"	d
GT_DEVPAR_Reserved	dev/gt64420reg.h	85;"	d
GT_DEVPAR_Reserved	dev/mv64340reg.h	78;"	d
GT_DEVPAR_ReservedMASK	dev/gt64120reg.h	287;"	d
GT_DEVPAR_ReservedMASK	dev/gt64240reg.h	80;"	d
GT_DEVPAR_ReservedMASK	dev/gt64420reg.h	84;"	d
GT_DEVPAR_ReservedMASK	dev/mv64340reg.h	77;"	d
GT_DEVPAR_TurnOff	dev/gt64120reg.h	256;"	d
GT_DEVPAR_TurnOff	dev/gt64240reg.h	69;"	d
GT_DEVPAR_TurnOff	dev/gt64420reg.h	73;"	d
GT_DEVPAR_TurnOff	dev/mv64340reg.h	61;"	d
GT_DEVPAR_TurnOffMASK	dev/gt64120reg.h	254;"	d
GT_DEVPAR_TurnOffSHIFT	dev/gt64120reg.h	255;"	d
GT_DEVPAR_WrActive	dev/gt64120reg.h	268;"	d
GT_DEVPAR_WrActive	dev/gt64240reg.h	73;"	d
GT_DEVPAR_WrActive	dev/gt64420reg.h	77;"	d
GT_DEVPAR_WrActive	dev/mv64340reg.h	65;"	d
GT_DEVPAR_WrActiveMASK	dev/gt64120reg.h	266;"	d
GT_DEVPAR_WrActiveSHIFT	dev/gt64120reg.h	267;"	d
GT_DEVPAR_WrHigh	dev/gt64120reg.h	271;"	d
GT_DEVPAR_WrHigh	dev/gt64240reg.h	74;"	d
GT_DEVPAR_WrHigh	dev/gt64420reg.h	78;"	d
GT_DEVPAR_WrHigh	dev/mv64340reg.h	66;"	d
GT_DEVPAR_WrHighMASK	dev/gt64120reg.h	269;"	d
GT_DEVPAR_WrHighSHIFT	dev/gt64120reg.h	270;"	d
GT_DRAMPAR_64bitInt	dev/gt64120reg.h	218;"	d
GT_DRAMPAR_64bitInt2	dev/gt64120reg.h	219;"	d
GT_DRAMPAR_64bitInt4	dev/gt64120reg.h	220;"	d
GT_DRAMPAR_BANK0	dev/gt64120reg.h	203;"	d
GT_DRAMPAR_BANK1	dev/gt64120reg.h	204;"	d
GT_DRAMPAR_BANK2	dev/gt64120reg.h	205;"	d
GT_DRAMPAR_BANK3	dev/gt64120reg.h	206;"	d
GT_DRAMPAR_BankLoc	dev/gt64120reg.h	224;"	d
GT_DRAMPAR_BankLocEven	dev/gt64120reg.h	225;"	d
GT_DRAMPAR_BankLocOdd	dev/gt64120reg.h	226;"	d
GT_DRAMPAR_BankWidth	dev/gt64120reg.h	221;"	d
GT_DRAMPAR_BankWidth32	dev/gt64120reg.h	222;"	d
GT_DRAMPAR_BankWidth64	dev/gt64120reg.h	223;"	d
GT_DRAMPAR_BrstLen	dev/gt64120reg.h	242;"	d
GT_DRAMPAR_BrstLen4	dev/gt64120reg.h	244;"	d
GT_DRAMPAR_BrstLen8	dev/gt64120reg.h	243;"	d
GT_DRAMPAR_ByPass	dev/gt64120reg.h	230;"	d
GT_DRAMPAR_ByPassNo	dev/gt64120reg.h	231;"	d
GT_DRAMPAR_ByPassYes	dev/gt64120reg.h	232;"	d
GT_DRAMPAR_CASLat2	dev/gt64120reg.h	210;"	d
GT_DRAMPAR_CASLat3	dev/gt64120reg.h	211;"	d
GT_DRAMPAR_CASLatMASK	dev/gt64120reg.h	209;"	d
GT_DRAMPAR_CASLatSHIFT	dev/gt64120reg.h	208;"	d
GT_DRAMPAR_ExtParity	dev/gt64120reg.h	239;"	d
GT_DRAMPAR_ExtParityNo	dev/gt64120reg.h	240;"	d
GT_DRAMPAR_ExtParitySi	dev/gt64120reg.h	241;"	d
GT_DRAMPAR_Parity	dev/gt64120reg.h	227;"	d
GT_DRAMPAR_ParityDisable	dev/gt64120reg.h	228;"	d
GT_DRAMPAR_ParityEnable	dev/gt64120reg.h	229;"	d
GT_DRAMPAR_RASPrchg	dev/gt64120reg.h	215;"	d
GT_DRAMPAR_RASPrchg1	dev/gt64120reg.h	216;"	d
GT_DRAMPAR_RASPrchg2	dev/gt64120reg.h	217;"	d
GT_DRAMPAR_SDRAMSize	dev/gt64120reg.h	236;"	d
GT_DRAMPAR_SDRAMSize16MB	dev/gt64120reg.h	237;"	d
GT_DRAMPAR_SDRAMSize64MB	dev/gt64120reg.h	238;"	d
GT_DRAMPAR_SRAStoSCAS	dev/gt64120reg.h	233;"	d
GT_DRAMPAR_SRAStoSCAS2	dev/gt64120reg.h	234;"	d
GT_DRAMPAR_SRAStoSCAS3	dev/gt64120reg.h	235;"	d
GT_DRAMPAR_Sample	dev/gt64120reg.h	212;"	d
GT_DRAMPAR_Sample1	dev/gt64120reg.h	213;"	d
GT_DRAMPAR_SampleNo	dev/gt64120reg.h	214;"	d
GT_DRAM_ADecode	dev/gt64120reg.h	197;"	d
GT_DRAM_ADecode_MASK	dev/gt64120reg.h	199;"	d
GT_DRAM_ADecode_SHIFT	dev/gt64120reg.h	200;"	d
GT_DRAM_CFG	dev/gt64120reg.h	152;"	d
GT_DRAM_CFG_CPUtoDRAMErr	dev/gt64120reg.h	167;"	d
GT_DRAM_CFG_CPUtoDRAMErrOff	dev/gt64120reg.h	169;"	d
GT_DRAM_CFG_CPUtoDRAMErrOn	dev/gt64120reg.h	168;"	d
GT_DRAM_CFG_DAdr12	dev/gt64120reg.h	188;"	d
GT_DRAM_CFG_DAdr12ADP	dev/gt64120reg.h	189;"	d
GT_DRAM_CFG_DAdr12DMA	dev/gt64120reg.h	190;"	d
GT_DRAM_CFG_DupBA	dev/gt64120reg.h	176;"	d
GT_DRAM_CFG_DupBAOff	dev/gt64120reg.h	177;"	d
GT_DRAM_CFG_DupBAOn	dev/gt64120reg.h	178;"	d
GT_DRAM_CFG_DupCntOn	dev/gt64120reg.h	175;"	d
GT_DRAM_CFG_DupCntl	dev/gt64120reg.h	173;"	d
GT_DRAM_CFG_DupCntlOff	dev/gt64120reg.h	174;"	d
GT_DRAM_CFG_DupEOT0	dev/gt64120reg.h	179;"	d
GT_DRAM_CFG_DupEOT0Off	dev/gt64120reg.h	180;"	d
GT_DRAM_CFG_DupEOT0On	dev/gt64120reg.h	181;"	d
GT_DRAM_CFG_DupEOT1	dev/gt64120reg.h	182;"	d
GT_DRAM_CFG_DupEOT1Off	dev/gt64120reg.h	183;"	d
GT_DRAM_CFG_DupEOT1On	dev/gt64120reg.h	184;"	d
GT_DRAM_CFG_ECCInt	dev/gt64120reg.h	170;"	d
GT_DRAM_CFG_ECCIntOn1	dev/gt64120reg.h	171;"	d
GT_DRAM_CFG_ECCIntOn2	dev/gt64120reg.h	172;"	d
GT_DRAM_CFG_Interleave	dev/gt64120reg.h	158;"	d
GT_DRAM_CFG_InterleaveOff	dev/gt64120reg.h	160;"	d
GT_DRAM_CFG_InterleaveOn	dev/gt64120reg.h	159;"	d
GT_DRAM_CFG_RdModWrt	dev/gt64120reg.h	161;"	d
GT_DRAM_CFG_RdModWrtOff	dev/gt64120reg.h	162;"	d
GT_DRAM_CFG_RdModWrtOn	dev/gt64120reg.h	163;"	d
GT_DRAM_CFG_RefIntCnt	dev/gt64120reg.h	156;"	d
GT_DRAM_CFG_RefIntCntMASK	dev/gt64120reg.h	154;"	d
GT_DRAM_CFG_RefIntCntSHIFT	dev/gt64120reg.h	155;"	d
GT_DRAM_CFG_RegSDRAM	dev/gt64120reg.h	185;"	d
GT_DRAM_CFG_RegSDRAMOff	dev/gt64120reg.h	187;"	d
GT_DRAM_CFG_RegSDRAMOn	dev/gt64120reg.h	186;"	d
GT_DRAM_CFG_StagRef	dev/gt64120reg.h	164;"	d
GT_DRAM_CFG_StagRefAll	dev/gt64120reg.h	166;"	d
GT_DRAM_CFG_StagRefOn	dev/gt64120reg.h	165;"	d
GT_DRAM_OpMode	dev/gt64120reg.h	192;"	d
GT_DRAM_OpMode_MASK	dev/gt64120reg.h	194;"	d
GT_DRAM_OpMode_SHIFT	dev/gt64120reg.h	195;"	d
GT_IPCI_BAREN_Cs20Dis	dev/gt64120reg.h	344;"	d
GT_IPCI_BAREN_Cs3BootDis	dev/gt64120reg.h	343;"	d
GT_IPCI_BAREN_IntIODis	dev/gt64120reg.h	341;"	d
GT_IPCI_BAREN_IntMemDis	dev/gt64120reg.h	342;"	d
GT_IPCI_BAREN_Ras10Dis	dev/gt64120reg.h	346;"	d
GT_IPCI_BAREN_Ras32Dis	dev/gt64120reg.h	345;"	d
GT_IPCI_BAREN_SwCs3BootDis	dev/gt64120reg.h	338;"	d
GT_IPCI_BAREN_SwRas10Dis	dev/gt64120reg.h	340;"	d
GT_IPCI_BAREN_SwRas32Dis	dev/gt64120reg.h	339;"	d
GT_IPCI_CFGADDR_BusNum	dev/gt64120reg.h	392;"	d
GT_IPCI_CFGADDR_BusNumMASK	dev/gt64120reg.h	390;"	d
GT_IPCI_CFGADDR_BusNumSHIFT	dev/gt64120reg.h	391;"	d
GT_IPCI_CFGADDR_ConfigEn	dev/gt64120reg.h	393;"	d
GT_IPCI_CFGADDR_ConfigEn	dev/gt64240reg.h	88;"	d
GT_IPCI_CFGADDR_ConfigEn	dev/gt64260reg.h	76;"	d
GT_IPCI_CFGADDR_ConfigEn	dev/gt64420reg.h	90;"	d
GT_IPCI_CFGADDR_ConfigEn	dev/mv64340reg.h	88;"	d
GT_IPCI_CFGADDR_ConfigEn	dev/mv64360reg.h	71;"	d
GT_IPCI_CFGADDR_DevNum	dev/gt64120reg.h	389;"	d
GT_IPCI_CFGADDR_DevNumMASK	dev/gt64120reg.h	387;"	d
GT_IPCI_CFGADDR_DevNumSHIFT	dev/gt64120reg.h	388;"	d
GT_IPCI_CFGADDR_FunctNum	dev/gt64120reg.h	386;"	d
GT_IPCI_CFGADDR_FunctNumMASK	dev/gt64120reg.h	384;"	d
GT_IPCI_CFGADDR_FunctNumSHIFT	dev/gt64120reg.h	385;"	d
GT_IPCI_CFGADDR_RegNum	dev/gt64120reg.h	383;"	d
GT_IPCI_CFGADDR_RegNumMASK	dev/gt64120reg.h	381;"	d
GT_IPCI_CFGADDR_RegNumSHIFT	dev/gt64120reg.h	382;"	d
GT_IPCI_CMD_ByteSwap	dev/gt64120reg.h	299;"	d
GT_IPCI_CMD_ByteSwapOff	dev/gt64120reg.h	301;"	d
GT_IPCI_CMD_ByteSwapOn	dev/gt64120reg.h	300;"	d
GT_IPCI_CMD_SyncMode1	dev/gt64120reg.h	305;"	d
GT_IPCI_CMD_SyncMode2	dev/gt64120reg.h	306;"	d
GT_IPCI_CMD_SyncMode5	dev/gt64120reg.h	307;"	d
GT_IPCI_CMD_SyncMode6	dev/gt64120reg.h	308;"	d
GT_IPCI_CMD_SyncModeMASK	dev/gt64120reg.h	302;"	d
GT_IPCI_CMD_SyncModeSHIFT	dev/gt64120reg.h	303;"	d
GT_IPCI_CMD_SyncModeStd	dev/gt64120reg.h	304;"	d
GT_IPCI_PMBS_Cs20MBL	dev/gt64120reg.h	353;"	d
GT_IPCI_PMBS_Cs3BootMBL	dev/gt64120reg.h	354;"	d
GT_IPCI_PMBS_Ras10MBL	dev/gt64120reg.h	351;"	d
GT_IPCI_PMBS_Ras32MBL	dev/gt64120reg.h	352;"	d
GT_IPCI_PMBS_RdLnPREF	dev/gt64120reg.h	356;"	d
GT_IPCI_PMBS_RdMenPREF	dev/gt64120reg.h	355;"	d
GT_IPCI_PMBS_RdMuliPREF	dev/gt64120reg.h	357;"	d
GT_IPCI_SIZE_BankSizeMASK	dev/gt64120reg.h	332;"	d
GT_IPCI_SIZE_BankSizeSHIFT	dev/gt64120reg.h	333;"	d
GT_IPCI_TOR_RetryCtr	dev/gt64120reg.h	321;"	d
GT_IPCI_TOR_RetryCtrMASK	dev/gt64120reg.h	319;"	d
GT_IPCI_TOR_RetryCtrSHIFT	dev/gt64120reg.h	320;"	d
GT_IPCI_TOR_Timeout0	dev/gt64120reg.h	315;"	d
GT_IPCI_TOR_Timeout0MASK	dev/gt64120reg.h	313;"	d
GT_IPCI_TOR_Timeout0SHIFT	dev/gt64120reg.h	314;"	d
GT_IPCI_TOR_Timeout1	dev/gt64120reg.h	318;"	d
GT_IPCI_TOR_Timeout1MASK	dev/gt64120reg.h	316;"	d
GT_IPCI_TOR_Timeout1SHIFT	dev/gt64120reg.h	317;"	d
GT_PAS_BUSERRHI	dev/gt64120reg.h	97;"	d
GT_PAS_BUSERRLO	dev/gt64120reg.h	96;"	d
GT_PAS_CS20HI	dev/gt64120reg.h	77;"	d
GT_PAS_CS20LO	dev/gt64120reg.h	76;"	d
GT_PAS_CS3BOOTHI	dev/gt64120reg.h	79;"	d
GT_PAS_CS3BOOTLO	dev/gt64120reg.h	78;"	d
GT_PAS_Cas20Rmap	dev/gt64120reg.h	108;"	d
GT_PAS_Cas3BootRmap	dev/gt64120reg.h	109;"	d
GT_PAS_HIMASK_High	dev/gt64120reg.h	101;"	d
GT_PAS_HISHIFT_High	dev/gt64120reg.h	102;"	d
GT_PAS_INTDEC	dev/gt64120reg.h	95;"	d
GT_PAS_LOMASK_Low	dev/gt64120reg.h	99;"	d
GT_PAS_LOSHIFT_Low	dev/gt64120reg.h	100;"	d
GT_PAS_MGTActMask	dev/gt64120reg.h	123;"	d
GT_PAS_MGTActive	dev/gt64120reg.h	121;"	d
GT_PAS_PCI0IOHI	dev/gt64120reg.h	82;"	d
GT_PAS_PCI0IOLO	dev/gt64120reg.h	81;"	d
GT_PAS_PCI0IORmap	dev/gt64120reg.h	110;"	d
GT_PAS_PCI0MEM0HI	dev/gt64120reg.h	84;"	d
GT_PAS_PCI0MEM0LO	dev/gt64120reg.h	83;"	d
GT_PAS_PCI0MEM0Rmap	dev/gt64120reg.h	111;"	d
GT_PAS_PCI0MEM1HI	dev/gt64120reg.h	86;"	d
GT_PAS_PCI0MEM1LO	dev/gt64120reg.h	85;"	d
GT_PAS_PCI0MEM1Rmap	dev/gt64120reg.h	112;"	d
GT_PAS_PCI0SBVR	dev/gt64120reg.h	104;"	d
GT_PAS_PCI1IOHI	dev/gt64120reg.h	89;"	d
GT_PAS_PCI1IOLO	dev/gt64120reg.h	88;"	d
GT_PAS_PCI1IORmap	dev/gt64120reg.h	113;"	d
GT_PAS_PCI1MEM0HI	dev/gt64120reg.h	91;"	d
GT_PAS_PCI1MEM0LO	dev/gt64120reg.h	90;"	d
GT_PAS_PCI1MEM0Rmap	dev/gt64120reg.h	114;"	d
GT_PAS_PCI1MEM1HI	dev/gt64120reg.h	93;"	d
GT_PAS_PCI1MEM1LO	dev/gt64120reg.h	92;"	d
GT_PAS_PCI1MEM1Rmap	dev/gt64120reg.h	115;"	d
GT_PAS_PCI1SBVR	dev/gt64120reg.h	105;"	d
GT_PAS_RAS10HI	dev/gt64120reg.h	73;"	d
GT_PAS_RAS10LO	dev/gt64120reg.h	72;"	d
GT_PAS_RAS32HI	dev/gt64120reg.h	75;"	d
GT_PAS_RAS32LO	dev/gt64120reg.h	74;"	d
GT_PAS_Ras10Rmap	dev/gt64120reg.h	106;"	d
GT_PAS_Ras32Rmap	dev/gt64120reg.h	107;"	d
GT_PAS_RmapMASK	dev/gt64120reg.h	117;"	d
GT_PAS_RmapSHIFT	dev/gt64120reg.h	118;"	d
GT_PCI0_BAREN	dev/gt64120reg.h	335;"	d
GT_PCI0_CFGADDR	dev/gt64120reg.h	375;"	d
GT_PCI0_CFGDATA	dev/gt64120reg.h	376;"	d
GT_PCI0_CMD	dev/gt64120reg.h	296;"	d
GT_PCI0_CS20SIZE	dev/gt64120reg.h	325;"	d
GT_PCI0_CS3BOOTSIZE	dev/gt64120reg.h	326;"	d
GT_PCI0_Cs20BARO	dev/gt64120reg.h	363;"	d
GT_PCI0_Cs3BootBeARO	dev/gt64120reg.h	364;"	d
GT_PCI0_MAP10	dev/gt64120reg.h	398;"	d
GT_PCI0_MAP10	dev/gt64240reg.h	83;"	d
GT_PCI0_MAP10	dev/gt64260reg.h	78;"	d
GT_PCI0_MAP10	dev/gt64420reg.h	87;"	d
GT_PCI0_MAP10	dev/mv64340reg.h	83;"	d
GT_PCI0_MAP14	dev/gt64120reg.h	399;"	d
GT_PCI0_MAP14	dev/gt64240reg.h	84;"	d
GT_PCI0_MAP14	dev/gt64260reg.h	79;"	d
GT_PCI0_MAP14	dev/gt64420reg.h	88;"	d
GT_PCI0_MAP14	dev/mv64340reg.h	84;"	d
GT_PCI0_MAP20	dev/gt64120reg.h	400;"	d
GT_PCI0_PMBS	dev/gt64120reg.h	348;"	d
GT_PCI0_RAS10SIZE	dev/gt64120reg.h	323;"	d
GT_PCI0_RAS32SIZE	dev/gt64120reg.h	324;"	d
GT_PCI0_Ras10BARO	dev/gt64120reg.h	359;"	d
GT_PCI0_Ras32BARO	dev/gt64120reg.h	361;"	d
GT_PCI0_SwapCs3Boot	dev/gt64120reg.h	365;"	d
GT_PCI0_SwapRAS10	dev/gt64120reg.h	360;"	d
GT_PCI0_SwapRAS32	dev/gt64120reg.h	362;"	d
GT_PCI0_TOR	dev/gt64120reg.h	310;"	d
GT_PCI1_BAREN	dev/gt64120reg.h	336;"	d
GT_PCI1_CFGADDR	dev/gt64120reg.h	377;"	d
GT_PCI1_CFGDATA	dev/gt64120reg.h	378;"	d
GT_PCI1_CMD	dev/gt64120reg.h	297;"	d
GT_PCI1_CS20SIZE	dev/gt64120reg.h	329;"	d
GT_PCI1_CS3BOOTSIZE	dev/gt64120reg.h	330;"	d
GT_PCI1_Cs20BARO	dev/gt64120reg.h	370;"	d
GT_PCI1_Cs3BootBeARO	dev/gt64120reg.h	371;"	d
GT_PCI1_MAP10	dev/gt64120reg.h	401;"	d
GT_PCI1_MAP10	dev/gt64240reg.h	85;"	d
GT_PCI1_MAP10	dev/gt64260reg.h	80;"	d
GT_PCI1_MAP10	dev/mv64340reg.h	85;"	d
GT_PCI1_MAP14	dev/gt64120reg.h	402;"	d
GT_PCI1_MAP14	dev/gt64240reg.h	86;"	d
GT_PCI1_MAP14	dev/gt64260reg.h	81;"	d
GT_PCI1_MAP14	dev/mv64340reg.h	86;"	d
GT_PCI1_MAP20	dev/gt64120reg.h	403;"	d
GT_PCI1_PMBS	dev/gt64120reg.h	349;"	d
GT_PCI1_RAS10SIZE	dev/gt64120reg.h	327;"	d
GT_PCI1_RAS32SIZE	dev/gt64120reg.h	328;"	d
GT_PCI1_Ras10BARO	dev/gt64120reg.h	366;"	d
GT_PCI1_Ras32BARO	dev/gt64120reg.h	368;"	d
GT_PCI1_SwapCs3Boot	dev/gt64120reg.h	372;"	d
GT_PCI1_SwapRAS10	dev/gt64120reg.h	367;"	d
GT_PCI1_SwapRAS32	dev/gt64120reg.h	369;"	d
GT_PCI1_TOR	dev/gt64120reg.h	311;"	d
GT_READ	dev/gt64240reg.h	51;"	d
GT_READ	dev/gt64240reg.h	56;"	d
GT_READ	dev/gt64260reg.h	48;"	d
GT_READ	dev/gt64420reg.h	51;"	d
GT_READ	dev/gt64420reg.h	56;"	d
GT_READ	dev/gt96132reg.h	54;"	d
GT_READ	dev/mv64340reg.h	53;"	d
GT_READ	dev/mv64360reg.h	46;"	d
GT_READ_BYTE	dev/gt64240reg.h	58;"	d
GT_READ_BYTE	dev/gt64420reg.h	58;"	d
GT_READ_NOSWAP	dev/gt96132reg.h	56;"	d
GT_READ_WORD	dev/gt64240reg.h	57;"	d
GT_READ_WORD	dev/gt64420reg.h	57;"	d
GT_SMIR_REG	dev/gt64240reg.h	90;"	d
GT_SMIR_REG	dev/gt64260reg.h	77;"	d
GT_SMIR_REG	dev/gt64420reg.h	92;"	d
GT_SMIR_REG	dev/gt96132reg.h	426;"	d
GT_SMIR_REG	dev/mv64340reg.h	90;"	d
GT_WRITE	dev/gt64240reg.h	50;"	d
GT_WRITE	dev/gt64240reg.h	53;"	d
GT_WRITE	dev/gt64260reg.h	45;"	d
GT_WRITE	dev/gt64420reg.h	50;"	d
GT_WRITE	dev/gt64420reg.h	53;"	d
GT_WRITE	dev/gt96132reg.h	49;"	d
GT_WRITE	dev/mv64340reg.h	50;"	d
GT_WRITE	dev/mv64360reg.h	43;"	d
GT_WRITE_BYTE	dev/gt64240reg.h	55;"	d
GT_WRITE_BYTE	dev/gt64420reg.h	55;"	d
GT_WRITE_NOSWAP	dev/gt96132reg.h	51;"	d
GT_WRITE_WORD	dev/gt64240reg.h	54;"	d
GT_WRITE_WORD	dev/gt64420reg.h	54;"	d
HAVE_QUAD	include/types.h	119;"	d
HEADER	include/arpa/nameser.h	/^} HEADER;$/;"	t	typeref:struct:__anon3
HFIXEDSZ	include/arpa/nameser.h	117;"	d
HI	include/powerpc.h	131;"	d
HIADJ	include/powerpc.h	130;"	d
HID0	include/powerpc.h	45;"	d
HID0_BCLK	include/powerpc.h	56;"	d
HID0_BHTE	include/powerpc.h	76;"	d
HID0_BTIC	include/powerpc.h	75;"	d
HID0_DCE	include/powerpc.h	66;"	d
HID0_DCFA	include/powerpc.h	74;"	d
HID0_DCFI	include/powerpc.h	70;"	d
HID0_DLOCK	include/powerpc.h	68;"	d
HID0_DOZE	include/powerpc.h	59;"	d
HID0_DPM	include/powerpc.h	62;"	d
HID0_EBA	include/powerpc.h	54;"	d
HID0_EBD	include/powerpc.h	55;"	d
HID0_ECLK	include/powerpc.h	57;"	d
HID0_EIEC	include/powerpc.h	63;"	d
HID0_ICE	include/powerpc.h	65;"	d
HID0_ICFI	include/powerpc.h	69;"	d
HID0_IFTT	include/powerpc.h	72;"	d
HID0_ILOCK	include/powerpc.h	67;"	d
HID0_NAP	include/powerpc.h	60;"	d
HID0_NHR	include/powerpc.h	64;"	d
HID0_NMCP	include/powerpc.h	53;"	d
HID0_NOPDST	include/powerpc.h	77;"	d
HID0_NOPTI	include/powerpc.h	78;"	d
HID0_PAR	include/powerpc.h	58;"	d
HID0_SGE	include/powerpc.h	73;"	d
HID0_SLEEP	include/powerpc.h	61;"	d
HID0_SPD	include/powerpc.h	71;"	d
HID1	include/powerpc.h	46;"	d
HIGH_INTERRUPT_CAUSE_REGISTER	dev/gt64240reg.h	910;"	d
HIGH_INTERRUPT_CAUSE_REGISTER	dev/gt64260reg.h	901;"	d
HIGH_INTERRUPT_CAUSE_REGISTER	dev/gt64420reg.h	605;"	d
HIGH_INTERRUPT_CAUSE_REGISTER	dev/gt96132reg.h	276;"	d
HIGH_INTERRUPT_CAUSE_REGISTER	dev/mv64340reg.h	734;"	d
HOSTNAMESIZE	include/url.h	42;"	d
HOST_NOT_FOUND	include/netdb.h	134;"	d
HTOLE32	dev/gt64240reg.h	39;"	d
HTOLE32	dev/gt64240reg.h	43;"	d
HTOLE32	dev/gt64420reg.h	39;"	d
HTOLE32	dev/gt64420reg.h	43;"	d
HTOLE32	dev/gt96132reg.h	46;"	d
HTOLE32	dev/mv64340reg.h	40;"	d
HTOLE32	dev/mv64340reg.h	44;"	d
I2C_CCR_MEN	dev/mpc107reg.h	163;"	d
I2C_CCR_MSTA	dev/mpc107reg.h	164;"	d
I2C_CCR_MTX	dev/mpc107reg.h	165;"	d
I2C_CCR_RSTA	dev/mpc107reg.h	167;"	d
I2C_CCR_TXAK	dev/mpc107reg.h	166;"	d
I2C_CONTROL	dev/gt64240reg.h	1259;"	d
I2C_CONTROL	dev/gt64260reg.h	1250;"	d
I2C_CONTROL	dev/gt64420reg.h	995;"	d
I2C_CONTROL	dev/mv64340reg.h	1109;"	d
I2C_CONTROL	dev/mv64360reg.h	1038;"	d
I2C_CSR_MBB	dev/mpc107reg.h	170;"	d
I2C_CSR_MCF	dev/mpc107reg.h	169;"	d
I2C_CSR_MIF	dev/mpc107reg.h	171;"	d
I2C_CSR_RXAK	dev/mpc107reg.h	172;"	d
I2C_DATA	dev/gt64240reg.h	1258;"	d
I2C_DATA	dev/gt64260reg.h	1249;"	d
I2C_DATA	dev/gt64420reg.h	994;"	d
I2C_DATA	dev/mv64340reg.h	1108;"	d
I2C_DATA	dev/mv64360reg.h	1037;"	d
I2C_EXTENDED_SLAVE_ADDR	dev/mv64360reg.h	1036;"	d
I2C_EXTENDED_SLAVE_ADDRESS	dev/gt64240reg.h	1257;"	d
I2C_EXTENDED_SLAVE_ADDRESS	dev/gt64260reg.h	1248;"	d
I2C_EXTENDED_SLAVE_ADDRESS	dev/gt64420reg.h	993;"	d
I2C_EXTENDED_SLAVE_ADDRESS	dev/mv64340reg.h	1107;"	d
I2C_READ	dev/mpc107reg.h	174;"	d
I2C_SLAVE_ADDR	dev/mv64360reg.h	1035;"	d
I2C_SLAVE_ADDRESS	dev/gt64240reg.h	1256;"	d
I2C_SLAVE_ADDRESS	dev/gt64260reg.h	1247;"	d
I2C_SLAVE_ADDRESS	dev/gt64420reg.h	992;"	d
I2C_SLAVE_ADDRESS	dev/mv64340reg.h	1106;"	d
I2C_SOFT_RESET	dev/gt64240reg.h	1261;"	d
I2C_SOFT_RESET	dev/gt64260reg.h	1252;"	d
I2C_SOFT_RESET	dev/gt64420reg.h	997;"	d
I2C_SOFT_RESET	dev/mv64340reg.h	1111;"	d
I2C_SOFT_RESET	dev/mv64360reg.h	1040;"	d
I2C_STATUS_BAUDE_RATE	dev/gt64240reg.h	1260;"	d
I2C_STATUS_BAUDE_RATE	dev/gt64260reg.h	1251;"	d
I2C_STATUS_BAUDE_RATE	dev/gt64420reg.h	996;"	d
I2C_STATUS_BAUDE_RATE	dev/mv64340reg.h	1110;"	d
I2C_STATUS_BAUDE_RATE	dev/mv64360reg.h	1039;"	d
I2C_WRITE	dev/mpc107reg.h	175;"	d
I2O_INBOUND_DOORBELL_REG_CPU0_SIDE	dev/mv64360reg.h	675;"	d
I2O_INBOUND_DOORBELL_REG_CPU1_SIDE	dev/mv64360reg.h	697;"	d
I2O_INBOUND_DOORBELL_REG_PCI_0_SIDE	dev/mv64360reg.h	629;"	d
I2O_INBOUND_DOORBELL_REG_PCI_1_SIDE	dev/mv64360reg.h	652;"	d
I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE	dev/mv64360reg.h	685;"	d
I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE	dev/mv64360reg.h	707;"	d
I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE	dev/mv64360reg.h	639;"	d
I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE	dev/mv64360reg.h	662;"	d
I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE	dev/mv64360reg.h	686;"	d
I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE	dev/mv64360reg.h	708;"	d
I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE	dev/mv64360reg.h	640;"	d
I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE	dev/mv64360reg.h	663;"	d
I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE	dev/mv64360reg.h	676;"	d
I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE	dev/mv64360reg.h	698;"	d
I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE	dev/mv64360reg.h	630;"	d
I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE	dev/mv64360reg.h	653;"	d
I2O_INBOUND_INTERRUPT_MASK_REG_CPU0_SIDE	dev/mv64360reg.h	677;"	d
I2O_INBOUND_INTERRUPT_MASK_REG_CPU1_SIDE	dev/mv64360reg.h	699;"	d
I2O_INBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE	dev/mv64360reg.h	631;"	d
I2O_INBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE	dev/mv64360reg.h	654;"	d
I2O_INBOUND_MESSAGE_REG0_CPU0_SIDE	dev/mv64360reg.h	671;"	d
I2O_INBOUND_MESSAGE_REG0_CPU1_SIDE	dev/mv64360reg.h	693;"	d
I2O_INBOUND_MESSAGE_REG0_PCI_0_SIDE	dev/mv64360reg.h	625;"	d
I2O_INBOUND_MESSAGE_REG0_PCI_1_SIDE	dev/mv64360reg.h	648;"	d
I2O_INBOUND_MESSAGE_REG1_CPU0_SIDE	dev/mv64360reg.h	672;"	d
I2O_INBOUND_MESSAGE_REG1_CPU1_SIDE	dev/mv64360reg.h	694;"	d
I2O_INBOUND_MESSAGE_REG1_PCI_0_SIDE	dev/mv64360reg.h	626;"	d
I2O_INBOUND_MESSAGE_REG1_PCI_1_SIDE	dev/mv64360reg.h	649;"	d
I2O_INBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE	dev/mv64360reg.h	687;"	d
I2O_INBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE	dev/mv64360reg.h	709;"	d
I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE	dev/mv64360reg.h	641;"	d
I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE	dev/mv64360reg.h	664;"	d
I2O_INBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE	dev/mv64360reg.h	688;"	d
I2O_INBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE	dev/mv64360reg.h	710;"	d
I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE	dev/mv64360reg.h	642;"	d
I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE	dev/mv64360reg.h	665;"	d
I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE	dev/mv64360reg.h	681;"	d
I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE	dev/mv64360reg.h	703;"	d
I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE	dev/mv64360reg.h	635;"	d
I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE	dev/mv64360reg.h	658;"	d
I2O_OUTBOUND_DOORBELL_REG_CPU0_SIDE	dev/mv64360reg.h	678;"	d
I2O_OUTBOUND_DOORBELL_REG_CPU1_SIDE	dev/mv64360reg.h	700;"	d
I2O_OUTBOUND_DOORBELL_REG_PCI_0_SIDE	dev/mv64360reg.h	632;"	d
I2O_OUTBOUND_DOORBELL_REG_PCI_1_SIDE	dev/mv64360reg.h	655;"	d
I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE	dev/mv64360reg.h	689;"	d
I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE	dev/mv64360reg.h	711;"	d
I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE	dev/mv64360reg.h	643;"	d
I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE	dev/mv64360reg.h	666;"	d
I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE	dev/mv64360reg.h	690;"	d
I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE	dev/mv64360reg.h	712;"	d
I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE	dev/mv64360reg.h	644;"	d
I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE	dev/mv64360reg.h	667;"	d
I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE	dev/mv64360reg.h	679;"	d
I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE	dev/mv64360reg.h	701;"	d
I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE	dev/mv64360reg.h	633;"	d
I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE	dev/mv64360reg.h	656;"	d
I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU0_SIDE	dev/mv64360reg.h	680;"	d
I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU1_SIDE	dev/mv64360reg.h	702;"	d
I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE	dev/mv64360reg.h	634;"	d
I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE	dev/mv64360reg.h	657;"	d
I2O_OUTBOUND_MESSAGE_REG0_CPU0_SIDE	dev/mv64360reg.h	673;"	d
I2O_OUTBOUND_MESSAGE_REG0_CPU1_SIDE	dev/mv64360reg.h	695;"	d
I2O_OUTBOUND_MESSAGE_REG0_PCI_0_SIDE	dev/mv64360reg.h	627;"	d
I2O_OUTBOUND_MESSAGE_REG0_PCI_1_SIDE	dev/mv64360reg.h	650;"	d
I2O_OUTBOUND_MESSAGE_REG1_CPU0_SIDE	dev/mv64360reg.h	674;"	d
I2O_OUTBOUND_MESSAGE_REG1_CPU1_SIDE	dev/mv64360reg.h	696;"	d
I2O_OUTBOUND_MESSAGE_REG1_PCI_0_SIDE	dev/mv64360reg.h	628;"	d
I2O_OUTBOUND_MESSAGE_REG1_PCI_1_SIDE	dev/mv64360reg.h	651;"	d
I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE	dev/mv64360reg.h	691;"	d
I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE	dev/mv64360reg.h	713;"	d
I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE	dev/mv64360reg.h	645;"	d
I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE	dev/mv64360reg.h	668;"	d
I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE	dev/mv64360reg.h	692;"	d
I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE	dev/mv64360reg.h	714;"	d
I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE	dev/mv64360reg.h	646;"	d
I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE	dev/mv64360reg.h	669;"	d
I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE	dev/mv64360reg.h	682;"	d
I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE	dev/mv64360reg.h	704;"	d
I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE	dev/mv64360reg.h	636;"	d
I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE	dev/mv64360reg.h	659;"	d
I2O_QUEUE_BASE_ADDR_REG_CPU0_SIDE	dev/mv64360reg.h	684;"	d
I2O_QUEUE_BASE_ADDR_REG_CPU1_SIDE	dev/mv64360reg.h	706;"	d
I2O_QUEUE_BASE_ADDR_REG_PCI_0_SIDE	dev/mv64360reg.h	638;"	d
I2O_QUEUE_BASE_ADDR_REG_PCI_1_SIDE	dev/mv64360reg.h	661;"	d
I2O_QUEUE_CONTROL_REG_CPU0_SIDE	dev/mv64360reg.h	683;"	d
I2O_QUEUE_CONTROL_REG_CPU1_SIDE	dev/mv64360reg.h	705;"	d
I2O_QUEUE_CONTROL_REG_PCI_0_SIDE	dev/mv64360reg.h	637;"	d
I2O_QUEUE_CONTROL_REG_PCI_1_SIDE	dev/mv64360reg.h	660;"	d
IAC	include/arpa/telnet.h	45;"	d
IADDR	include/pmon.h	57;"	d
IBAT_SETUP	include/powerpc.h	142;"	d
ICACHE	include/pmon.h	55;"	d
ICANON	include/termio.h	32;"	d
ICRNL	include/termio.h	22;"	d
IER_EMSC	dev/ns16550.h	111;"	d
IER_ERLS	dev/ns16550.h	110;"	d
IER_ERXRDY	dev/ns16550.h	108;"	d
IER_ETXRDY	dev/ns16550.h	109;"	d
IIR_FIFO_MASK	dev/ns16550.h	121;"	d
IIR_IMASK	dev/ns16550.h	114;"	d
IIR_MLSC	dev/ns16550.h	120;"	d
IIR_NOPEND	dev/ns16550.h	119;"	d
IIR_RLS	dev/ns16550.h	116;"	d
IIR_RXRDY	dev/ns16550.h	117;"	d
IIR_RXTOUT	dev/ns16550.h	115;"	d
IIR_TXRDY	dev/ns16550.h	118;"	d
IN6ADDRSZ	include/arpa/nameser.h	123;"	d
INADDRSZ	include/arpa/nameser.h	122;"	d
INBASE_AUTO	include/pmon.h	84;"	d
INBASE_DEC	include/pmon.h	86;"	d
INBASE_DEFAULT	include/pmon.h	90;"	d
INBASE_HEX	include/pmon.h	87;"	d
INBASE_OCT	include/pmon.h	85;"	d
INBASE_STRING	include/pmon.h	88;"	d
INBOUND_DOORBELL_REGISTER_CPU_SIDE	dev/gt64240reg.h	956;"	d
INBOUND_DOORBELL_REGISTER_CPU_SIDE	dev/gt64260reg.h	947;"	d
INBOUND_DOORBELL_REGISTER_CPU_SIDE	dev/gt64420reg.h	644;"	d
INBOUND_DOORBELL_REGISTER_CPU_SIDE	dev/gt96132reg.h	403;"	d
INBOUND_DOORBELL_REGISTER_CPU_SIDE	dev/mv64340reg.h	780;"	d
INBOUND_DOORBELL_REGISTER_PCI_SIDE	dev/gt64240reg.h	933;"	d
INBOUND_DOORBELL_REGISTER_PCI_SIDE	dev/gt64260reg.h	924;"	d
INBOUND_DOORBELL_REGISTER_PCI_SIDE	dev/gt64420reg.h	621;"	d
INBOUND_DOORBELL_REGISTER_PCI_SIDE	dev/gt96132reg.h	380;"	d
INBOUND_DOORBELL_REGISTER_PCI_SIDE	dev/mv64340reg.h	757;"	d
INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE	dev/gt64240reg.h	966;"	d
INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE	dev/gt64260reg.h	957;"	d
INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE	dev/gt64420reg.h	654;"	d
INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE	dev/gt96132reg.h	413;"	d
INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE	dev/mv64340reg.h	790;"	d
INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE	dev/gt64240reg.h	943;"	d
INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE	dev/gt64260reg.h	934;"	d
INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE	dev/gt64420reg.h	631;"	d
INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE	dev/gt96132reg.h	390;"	d
INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE	dev/mv64340reg.h	767;"	d
INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE	dev/gt64240reg.h	967;"	d
INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE	dev/gt64260reg.h	958;"	d
INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE	dev/gt64420reg.h	655;"	d
INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE	dev/gt96132reg.h	414;"	d
INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE	dev/mv64340reg.h	791;"	d
INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE	dev/gt64240reg.h	944;"	d
INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE	dev/gt64260reg.h	935;"	d
INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE	dev/gt64420reg.h	632;"	d
INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE	dev/gt96132reg.h	391;"	d
INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE	dev/mv64340reg.h	768;"	d
INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE	dev/gt64240reg.h	957;"	d
INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE	dev/gt64260reg.h	948;"	d
INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE	dev/gt64420reg.h	645;"	d
INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE	dev/gt96132reg.h	404;"	d
INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE	dev/mv64340reg.h	781;"	d
INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE	dev/gt64240reg.h	934;"	d
INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE	dev/gt64260reg.h	925;"	d
INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE	dev/gt64420reg.h	622;"	d
INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE	dev/gt96132reg.h	381;"	d
INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE	dev/mv64340reg.h	758;"	d
INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE	dev/gt64240reg.h	958;"	d
INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE	dev/gt64260reg.h	949;"	d
INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE	dev/gt64420reg.h	646;"	d
INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE	dev/gt96132reg.h	405;"	d
INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE	dev/mv64340reg.h	782;"	d
INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE	dev/gt64240reg.h	935;"	d
INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE	dev/gt64260reg.h	926;"	d
INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE	dev/gt64420reg.h	623;"	d
INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE	dev/gt96132reg.h	382;"	d
INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE	dev/mv64340reg.h	759;"	d
INBOUND_MESSAGE_REGISTER0_CPU_SIDE	dev/gt64240reg.h	952;"	d
INBOUND_MESSAGE_REGISTER0_CPU_SIDE	dev/gt64260reg.h	943;"	d
INBOUND_MESSAGE_REGISTER0_CPU_SIDE	dev/gt64420reg.h	640;"	d
INBOUND_MESSAGE_REGISTER0_CPU_SIDE	dev/gt96132reg.h	399;"	d
INBOUND_MESSAGE_REGISTER0_CPU_SIDE	dev/mv64340reg.h	776;"	d
INBOUND_MESSAGE_REGISTER0_PCI_SIDE	dev/gt64240reg.h	929;"	d
INBOUND_MESSAGE_REGISTER0_PCI_SIDE	dev/gt64260reg.h	920;"	d
INBOUND_MESSAGE_REGISTER0_PCI_SIDE	dev/gt64420reg.h	617;"	d
INBOUND_MESSAGE_REGISTER0_PCI_SIDE	dev/gt96132reg.h	376;"	d
INBOUND_MESSAGE_REGISTER0_PCI_SIDE	dev/mv64340reg.h	753;"	d
INBOUND_MESSAGE_REGISTER1_CPU_SIDE	dev/gt64240reg.h	953;"	d
INBOUND_MESSAGE_REGISTER1_CPU_SIDE	dev/gt64260reg.h	944;"	d
INBOUND_MESSAGE_REGISTER1_CPU_SIDE	dev/gt64420reg.h	641;"	d
INBOUND_MESSAGE_REGISTER1_CPU_SIDE	dev/gt96132reg.h	400;"	d
INBOUND_MESSAGE_REGISTER1_CPU_SIDE	dev/mv64340reg.h	777;"	d
INBOUND_MESSAGE_REGISTER1_PCI_SIDE	dev/gt64240reg.h	930;"	d
INBOUND_MESSAGE_REGISTER1_PCI_SIDE	dev/gt64260reg.h	921;"	d
INBOUND_MESSAGE_REGISTER1_PCI_SIDE	dev/gt64420reg.h	618;"	d
INBOUND_MESSAGE_REGISTER1_PCI_SIDE	dev/gt96132reg.h	377;"	d
INBOUND_MESSAGE_REGISTER1_PCI_SIDE	dev/mv64340reg.h	754;"	d
INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE	dev/gt64240reg.h	968;"	d
INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE	dev/gt64260reg.h	959;"	d
INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE	dev/gt64420reg.h	656;"	d
INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE	dev/gt96132reg.h	415;"	d
INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE	dev/mv64340reg.h	792;"	d
INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE	dev/gt64240reg.h	945;"	d
INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE	dev/gt64260reg.h	936;"	d
INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE	dev/gt64420reg.h	633;"	d
INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE	dev/gt96132reg.h	392;"	d
INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE	dev/mv64340reg.h	769;"	d
INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE	dev/gt64240reg.h	969;"	d
INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE	dev/gt64260reg.h	960;"	d
INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE	dev/gt64420reg.h	657;"	d
INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE	dev/gt96132reg.h	416;"	d
INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE	dev/mv64340reg.h	793;"	d
INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE	dev/gt64240reg.h	946;"	d
INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE	dev/gt64260reg.h	937;"	d
INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE	dev/gt64420reg.h	634;"	d
INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE	dev/gt96132reg.h	393;"	d
INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE	dev/mv64340reg.h	770;"	d
INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE	dev/gt64240reg.h	962;"	d
INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE	dev/gt64260reg.h	953;"	d
INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE	dev/gt64420reg.h	650;"	d
INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE	dev/gt96132reg.h	409;"	d
INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE	dev/mv64340reg.h	786;"	d
INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE	dev/gt64240reg.h	939;"	d
INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE	dev/gt64260reg.h	930;"	d
INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE	dev/gt64420reg.h	627;"	d
INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE	dev/gt96132reg.h	386;"	d
INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE	dev/mv64340reg.h	763;"	d
INDIR_MASK	include/arpa/nameser.h	347;"	d
INITIALIZE_MOUSE	dev/kbd.h	46;"	d
INT16SZ	include/arpa/nameser.h	121;"	d
INT32SZ	include/arpa/nameser.h	120;"	d
INTEGRATED_SRAM_BASE_ADDR	dev/mv64360reg.h	131;"	d
INTERNAL_SPACE_BASE	dev/mv64340reg.h	192;"	d
INTERNAL_SPACE_BASE_ADDR	dev/mv64360reg.h	134;"	d
INTERNAL_SPACE_DECODE	dev/gt64240reg.h	188;"	d
INTERNAL_SPACE_DECODE	dev/gt64260reg.h	179;"	d
INTERNAL_SPACE_DECODE	dev/gt64420reg.h	167;"	d
INTERNAL_SPACE_DECODE	dev/gt96132reg.h	98;"	d
INTERNAL_SRAM_BASE	dev/mv64340reg.h	193;"	d
INTERRUPT0_HIGH_MASK_REGISTER	dev/gt96132reg.h	271;"	d
INTERRUPT0_MAIN_MASK_REGISTER	dev/gt96132reg.h	268;"	d
INTERRUPT0_MASK_0_HIGH	dev/mv64360reg.h	1072;"	d
INTERRUPT0_MASK_0_LOW	dev/mv64360reg.h	1071;"	d
INTERRUPT0_SELECT_CAUSE	dev/mv64360reg.h	1073;"	d
INTERRUPT0_SELECT_REGISTER	dev/gt96132reg.h	273;"	d
INTERRUPT1_HIGH_MASK_REGISTER	dev/gt96132reg.h	272;"	d
INTERRUPT1_MAIN_MASK_REGISTER	dev/gt96132reg.h	269;"	d
INTERRUPT1_MASK_0_HIGH	dev/mv64360reg.h	1075;"	d
INTERRUPT1_MASK_0_LOW	dev/mv64360reg.h	1074;"	d
INTERRUPT1_SELECT_CAUSE	dev/mv64360reg.h	1076;"	d
INTERRUPT1_SELECT_REGISTER	dev/gt96132reg.h	274;"	d
INTERRUPT_CAUSE_REGISTER	dev/gt96132reg.h	275;"	d
INTERRUPT_HIGH_CAUSE_REGISTER	dev/gt96132reg.h	270;"	d
INTERRUPT_MAIN_CAUSE_REGISTER	dev/gt96132reg.h	267;"	d
INTERRUPT_MASK_REGISTER_HIGH	dev/gt64420reg.h	610;"	d
INTERRUPT_MASK_REGISTER_LOW	dev/gt64420reg.h	609;"	d
IORDER	dev/cpc700.h	354;"	d
IORDER	include/powerpc.h	137;"	d
IP	include/arpa/telnet.h	56;"	d
IQC_ENABLE_INTERRUPTS_REGISTER	dev/gt96132reg.h	838;"	d
IQC_FIRST	dev/gt96132reg.h	833;"	d
IQC_HEAD	dev/gt96132reg.h	835;"	d
IQC_LAST	dev/gt96132reg.h	834;"	d
IQC_TAIL	dev/gt96132reg.h	836;"	d
IQUERY	include/arpa/nameser.h	134;"	d
ISIG	include/termio.h	31;"	d
ISTRIP	include/termio.h	21;"	d
IXANY	include/termio.h	24;"	d
IXOFF	include/termio.h	25;"	d
IXON	include/termio.h	23;"	d
I_CACHEOP_SFT	include/ri.h	21;"	d
I_CACHESEL_SFT	include/ri.h	24;"	d
I_FD_SFT	include/ri.h	45;"	d
I_FFMT_SFT	include/ri.h	36;"	d
I_FMA_FFMT_SFT	include/ri.h	54;"	d
I_FMA_FUNC_SFT	include/ri.h	51;"	d
I_FR_SFT	include/ri.h	48;"	d
I_FS_SFT	include/ri.h	42;"	d
I_FT_SFT	include/ri.h	39;"	d
I_FUNC_SFT	include/ri.h	33;"	d
I_IMM_SFT	include/ri.h	17;"	d
I_JTARGET_SFT	include/ri.h	8;"	d
I_OPCODE_SFT	include/ri.h	5;"	d
I_RD_SFT	include/ri.h	27;"	d
I_RE_SFT	include/ri.h	30;"	d
I_RS_SFT	include/ri.h	11;"	d
I_RT_SFT	include/ri.h	14;"	d
KBC_TIMEOUT	dev/kbd.h	51;"	d
KBD_BAD_DATA	dev/kbd.h	155;"	d
KBD_CCMD_GET_VERSION	dev/kbd.h	75;"	d
KBD_CCMD_KBD_DISABLE	dev/kbd.h	81;"	d
KBD_CCMD_KBD_ENABLE	dev/kbd.h	82;"	d
KBD_CCMD_KBD_TEST	dev/kbd.h	80;"	d
KBD_CCMD_MOUSE_DISABLE	dev/kbd.h	76;"	d
KBD_CCMD_MOUSE_ENABLE	dev/kbd.h	77;"	d
KBD_CCMD_READ_MODE	dev/kbd.h	73;"	d
KBD_CCMD_SELF_TEST	dev/kbd.h	79;"	d
KBD_CCMD_TEST_MOUSE	dev/kbd.h	78;"	d
KBD_CCMD_WRITE_AUX_OBUF	dev/kbd.h	83;"	d
KBD_CCMD_WRITE_MODE	dev/kbd.h	74;"	d
KBD_CCMD_WRITE_MOUSE	dev/kbd.h	85;"	d
KBD_CMD_DISABLE	dev/kbd.h	94;"	d
KBD_CMD_ENABLE	dev/kbd.h	93;"	d
KBD_CMD_RESET	dev/kbd.h	95;"	d
KBD_CMD_SET_LEDS	dev/kbd.c	894;"	d	file:
KBD_CMD_SET_LEDS	dev/kbd.h	91;"	d
KBD_CMD_SET_RATE	dev/kbd.h	92;"	d
KBD_CNTL_REG	dev/kbd.h	13;"	d
KBD_CNTL_REG	dev/kbd.h	66;"	d
KBD_DATA_REG	dev/kbd.h	14;"	d
KBD_DATA_REG	dev/kbd.h	67;"	d
KBD_INIT_TIMEOUT	dev/kbd.h	50;"	d
KBD_IS_FOCUS_9000	dev/kbd.h	45;"	d
KBD_MODE_DISABLE_KBD	dev/kbd.h	128;"	d
KBD_MODE_DISABLE_MOUSE	dev/kbd.h	129;"	d
KBD_MODE_KBD_INT	dev/kbd.h	124;"	d
KBD_MODE_KCC	dev/kbd.h	130;"	d
KBD_MODE_MOUSE_INT	dev/kbd.h	125;"	d
KBD_MODE_NO_KEYLOCK	dev/kbd.h	127;"	d
KBD_MODE_RFU	dev/kbd.h	131;"	d
KBD_MODE_SYS	dev/kbd.h	126;"	d
KBD_NO_DATA	dev/kbd.h	154;"	d
KBD_REPLY_ACK	dev/kbd.h	102;"	d
KBD_REPLY_ACK	dev/kbd.h	27;"	d
KBD_REPLY_POR	dev/kbd.h	101;"	d
KBD_REPLY_POR	dev/kbd.h	26;"	d
KBD_REPLY_RESEND	dev/kbd.h	103;"	d
KBD_REPLY_RESEND	dev/kbd.h	28;"	d
KBD_REPORT_ERR	dev/kbd.h	42;"	d
KBD_REPORT_TIMEOUTS	dev/kbd.h	44;"	d
KBD_REPORT_UNKN	dev/kbd.h	43;"	d
KBD_STATUS_REG	dev/kbd.h	12;"	d
KBD_STATUS_REG	dev/kbd.h	65;"	d
KBD_STAT_CMD	dev/kbd.h	112;"	d
KBD_STAT_CMD	dev/kbd.h	6;"	d
KBD_STAT_GTO	dev/kbd.h	115;"	d
KBD_STAT_GTO	dev/kbd.h	9;"	d
KBD_STAT_IBF	dev/kbd.h	110;"	d
KBD_STAT_IBF	dev/kbd.h	4;"	d
KBD_STAT_MOUSE_OBF	dev/kbd.h	114;"	d
KBD_STAT_MOUSE_OBF	dev/kbd.h	8;"	d
KBD_STAT_OBF	dev/kbd.h	109;"	d
KBD_STAT_OBF	dev/kbd.h	3;"	d
KBD_STAT_PERR	dev/kbd.h	10;"	d
KBD_STAT_PERR	dev/kbd.h	116;"	d
KBD_STAT_SELFTEST	dev/kbd.h	111;"	d
KBD_STAT_SELFTEST	dev/kbd.h	5;"	d
KBD_STAT_UNLOCKED	dev/kbd.h	113;"	d
KBD_STAT_UNLOCKED	dev/kbd.h	7;"	d
KBD_TIMEOUT	dev/kbd.h	52;"	d
KEYFLAG_EMAIL	include/arpa/nameser.h	227;"	d
KEYFLAG_ENTITY	include/arpa/nameser.h	224;"	d
KEYFLAG_EXPERIMENTAL	include/arpa/nameser.h	220;"	d
KEYFLAG_IPSEC	include/arpa/nameser.h	226;"	d
KEYFLAG_NO_AUTH	include/arpa/nameser.h	217;"	d
KEYFLAG_NO_CONF	include/arpa/nameser.h	218;"	d
KEYFLAG_RESERVED10	include/arpa/nameser.h	228;"	d
KEYFLAG_RESERVED11	include/arpa/nameser.h	229;"	d
KEYFLAG_RESERVED3	include/arpa/nameser.h	221;"	d
KEYFLAG_RESERVED4	include/arpa/nameser.h	222;"	d
KEYFLAG_RESERVED_BITMASK	include/arpa/nameser.h	232;"	d
KEYFLAG_SIGNATORYMASK	include/arpa/nameser.h	230;"	d
KEYFLAG_TYPEMASK	include/arpa/nameser.h	211;"	d
KEYFLAG_TYPE_AUTH_CONF	include/arpa/nameser.h	212;"	d
KEYFLAG_TYPE_AUTH_ONLY	include/arpa/nameser.h	214;"	d
KEYFLAG_TYPE_CONF_ONLY	include/arpa/nameser.h	213;"	d
KEYFLAG_TYPE_NO_KEY	include/arpa/nameser.h	215;"	d
KEYFLAG_USERACCOUNT	include/arpa/nameser.h	223;"	d
KEYFLAG_ZONEKEY	include/arpa/nameser.h	225;"	d
KEY_PRESS_MASK	dev/key_defs.h	17;"	d
KTYP	dev/kbd.h	174;"	d
KT_ASCII	dev/kbd.h	169;"	d
KT_CONS	dev/kbd.h	165;"	d
KT_CUR	dev/kbd.h	166;"	d
KT_DEAD	dev/kbd.h	164;"	d
KT_FN	dev/kbd.h	161;"	d
KT_LATIN	dev/kbd.h	160;"	d
KT_LETTER	dev/kbd.h	171;"	d
KT_LOCK	dev/kbd.h	170;"	d
KT_META	dev/kbd.h	168;"	d
KT_PAD	dev/kbd.h	163;"	d
KT_SHIFT	dev/kbd.h	167;"	d
KT_SLOCK	dev/kbd.h	172;"	d
KT_SPEC	dev/kbd.h	162;"	d
L2CR	include/powerpc.h	47;"	d
L2CR_L2BYP	include/powerpc.h	112;"	d
L2CR_L2CLKSTP	include/powerpc.h	116;"	d
L2CR_L2CLK_1	include/powerpc.h	89;"	d
L2CR_L2CLK_15	include/powerpc.h	90;"	d
L2CR_L2CLK_2	include/powerpc.h	92;"	d
L2CR_L2CLK_25	include/powerpc.h	93;"	d
L2CR_L2CLK_3	include/powerpc.h	94;"	d
L2CR_L2CLK_35	include/powerpc.h	91;"	d
L2CR_L2CLK_4	include/powerpc.h	95;"	d
L2CR_L2CLK_DIS	include/powerpc.h	88;"	d
L2CR_L2CLK_SPEED_MSK	include/powerpc.h	96;"	d
L2CR_L2CTL	include/powerpc.h	103;"	d
L2CR_L2CTR	include/powerpc.h	118;"	d
L2CR_L2DF	include/powerpc.h	111;"	d
L2CR_L2DO	include/powerpc.h	101;"	d
L2CR_L2DRO	include/powerpc.h	117;"	d
L2CR_L2E	include/powerpc.h	82;"	d
L2CR_L2FA	include/powerpc.h	113;"	d
L2CR_L2HWF	include/powerpc.h	114;"	d
L2CR_L2I	include/powerpc.h	102;"	d
L2CR_L2IO	include/powerpc.h	115;"	d
L2CR_L2IP	include/powerpc.h	119;"	d
L2CR_L2OH_05	include/powerpc.h	106;"	d
L2CR_L2OH_10	include/powerpc.h	107;"	d
L2CR_L2OH_EMOUT	include/powerpc.h	109;"	d
L2CR_L2OH_MOUT	include/powerpc.h	108;"	d
L2CR_L2PE	include/powerpc.h	83;"	d
L2CR_L2RAM_FLOW	include/powerpc.h	97;"	d
L2CR_L2RAM_LATEW	include/powerpc.h	100;"	d
L2CR_L2RAM_PIPE	include/powerpc.h	99;"	d
L2CR_L2RAM_RES	include/powerpc.h	98;"	d
L2CR_L2SIZ_1024	include/powerpc.h	86;"	d
L2CR_L2SIZ_2048	include/powerpc.h	87;"	d
L2CR_L2SIZ_256	include/powerpc.h	84;"	d
L2CR_L2SIZ_512	include/powerpc.h	85;"	d
L2CR_L2SL	include/powerpc.h	110;"	d
L2CR_L2TS	include/powerpc.h	105;"	d
L2CR_L2WT	include/powerpc.h	104;"	d
LED_CAPS_LOCK	dev/key_defs.h	23;"	d
LED_NUM_LOCK	dev/key_defs.h	21;"	d
LED_SCROLL_LOCK	dev/key_defs.h	22;"	d
LFLOW_OFF	include/arpa/telnet.h	157;"	d
LFLOW_ON	include/arpa/telnet.h	158;"	d
LFLOW_RESTART_ANY	include/arpa/telnet.h	159;"	d
LFLOW_RESTART_XON	include/arpa/telnet.h	160;"	d
LINESZ	include/pmon.h	60;"	d
LITTLE_ENDIAN	include/arpa/nameser.h	266;"	d
LM_FORWARDMASK	include/arpa/telnet.h	167;"	d
LM_MODE	include/arpa/telnet.h	166;"	d
LM_SLC	include/arpa/telnet.h	168;"	d
LO	include/powerpc.h	132;"	d
LOCALDOMAINPARTS	include/resolv.h	101;"	d
LOW_INTERRUPT_CAUSE_REGISTER	dev/gt64240reg.h	909;"	d
LOW_INTERRUPT_CAUSE_REGISTER	dev/gt64260reg.h	900;"	d
LOW_INTERRUPT_CAUSE_REGISTER	dev/gt64420reg.h	604;"	d
LOW_INTERRUPT_CAUSE_REGISTER	dev/mv64340reg.h	733;"	d
LSR_BI	dev/ns16550.h	158;"	d
LSR_FE	dev/ns16550.h	159;"	d
LSR_OE	dev/ns16550.h	161;"	d
LSR_PE	dev/ns16550.h	160;"	d
LSR_RCV_FIFO	dev/ns16550.h	155;"	d
LSR_RCV_MASK	dev/ns16550.h	163;"	d
LSR_RXRDY	dev/ns16550.h	162;"	d
LSR_TSRE	dev/ns16550.h	156;"	d
LSR_TXRDY	dev/ns16550.h	157;"	d
L_SLAVE_READ_DATA_HIGH	dev/gt64240reg.h	807;"	d
L_SLAVE_READ_DATA_HIGH	dev/gt64260reg.h	798;"	d
L_SLAVE_READ_DATA_LOW	dev/gt64240reg.h	806;"	d
L_SLAVE_READ_DATA_LOW	dev/gt64260reg.h	797;"	d
L_SLAVE_READ_ID	dev/gt64240reg.h	808;"	d
L_SLAVE_READ_ID	dev/gt64260reg.h	799;"	d
L_SLAVE_WRITE_BYTE_ENABLE	dev/gt64240reg.h	805;"	d
L_SLAVE_WRITE_BYTE_ENABLE	dev/gt64260reg.h	796;"	d
L_SLAVE_WRITE_DATA_HIGH	dev/gt64240reg.h	804;"	d
L_SLAVE_WRITE_DATA_HIGH	dev/gt64260reg.h	795;"	d
L_SLAVE_WRITE_DATA_LOW	dev/gt64240reg.h	803;"	d
L_SLAVE_WRITE_DATA_LOW	dev/gt64260reg.h	794;"	d
L_SLAVE_X0_ADDRESS	dev/gt64240reg.h	799;"	d
L_SLAVE_X0_ADDRESS	dev/gt64260reg.h	790;"	d
L_SLAVE_X0_COMMAND_AND_ID	dev/gt64240reg.h	800;"	d
L_SLAVE_X0_COMMAND_AND_ID	dev/gt64260reg.h	791;"	d
L_SLAVE_X1_ADDRESS	dev/gt64240reg.h	801;"	d
L_SLAVE_X1_ADDRESS	dev/gt64260reg.h	792;"	d
L_SLAVE_X1_COMMAND_AND_ID	dev/gt64240reg.h	802;"	d
L_SLAVE_X1_COMMAND_AND_ID	dev/gt64260reg.h	793;"	d
M1543C_BCSC	dev/m1543reg.h	47;"	d
M1543C_COM1_IO_ADRS	dev/m1543reg.h	114;"	d
M1543C_COM1_IRQ	dev/m1543reg.h	125;"	d
M1543C_COM2_IO_ADRS	dev/m1543reg.h	115;"	d
M1543C_COM2_IRQ	dev/m1543reg.h	126;"	d
M1543C_DEV_ID_REG	dev/m1543reg.h	37;"	d
M1543C_DEV_REV	dev/m1543reg.h	40;"	d
M1543C_DMDC	dev/m1543reg.h	58;"	d
M1543C_FDC_DMA	dev/m1543reg.h	119;"	d
M1543C_FDC_IO_ADRS	dev/m1543reg.h	112;"	d
M1543C_FDC_IRQ	dev/m1543reg.h	123;"	d
M1543C_GPIS	dev/m1543reg.h	56;"	d
M1543C_GPOS	dev/m1543reg.h	57;"	d
M1543C_IORC	dev/m1543reg.h	43;"	d
M1543C_ISAC1	dev/m1543reg.h	44;"	d
M1543C_ISAC2	dev/m1543reg.h	45;"	d
M1543C_KBC_IRQ	dev/m1543reg.h	127;"	d
M1543C_LPT_DMA	dev/m1543reg.h	120;"	d
M1543C_LPT_IO_ADRS	dev/m1543reg.h	113;"	d
M1543C_LPT_IRQ	dev/m1543reg.h	124;"	d
M1543C_PCI_CMD	dev/m1543reg.h	38;"	d
M1543C_PCI_STAT	dev/m1543reg.h	39;"	d
M1543C_PCSAD	dev/m1543reg.h	54;"	d
M1543C_PIC	dev/m1543reg.h	42;"	d
M1543C_PILET	dev/m1543reg.h	52;"	d
M1543C_PIRT1	dev/m1543reg.h	48;"	d
M1543C_PIRT2	dev/m1543reg.h	49;"	d
M1543C_PIRT3	dev/m1543reg.h	50;"	d
M1543C_PIRT4	dev/m1543reg.h	51;"	d
M1543C_PMU_COESII	dev/m1543reg.h	65;"	d
M1543C_PMU_DOGPOI	dev/m1543reg.h	66;"	d
M1543C_PMU_ODGPOII	dev/m1543reg.h	67;"	d
M1543C_PMU_SMIRB	dev/m1543reg.h	68;"	d
M1543C_SIO_APDR	dev/m1543reg.h	83;"	d
M1543C_SIO_CNF2R	dev/m1543reg.h	91;"	d
M1543C_SIO_CNFR	dev/m1543reg.h	90;"	d
M1543C_SIO_CNF_PORT	dev/m1543reg.h	73;"	d
M1543C_SIO_DATA_PORT	dev/m1543reg.h	75;"	d
M1543C_SIO_DEV_ID1	dev/m1543reg.h	81;"	d
M1543C_SIO_DEV_ID2	dev/m1543reg.h	80;"	d
M1543C_SIO_DEV_VER	dev/m1543reg.h	79;"	d
M1543C_SIO_DMAR	dev/m1543reg.h	89;"	d
M1543C_SIO_DPDR	dev/m1543reg.h	82;"	d
M1543C_SIO_ENR	dev/m1543reg.h	85;"	d
M1543C_SIO_HIAR	dev/m1543reg.h	86;"	d
M1543C_SIO_IDX_PORT	dev/m1543reg.h	74;"	d
M1543C_SIO_IRQR	dev/m1543reg.h	122;"	d
M1543C_SIO_IRQR	dev/m1543reg.h	88;"	d
M1543C_SIO_LOAR	dev/m1543reg.h	87;"	d
M1543C_SIO_LPT_CNFR	dev/m1543reg.h	93;"	d
M1543C_SIO_LUN_COM1	dev/m1543reg.h	103;"	d
M1543C_SIO_LUN_COM2	dev/m1543reg.h	104;"	d
M1543C_SIO_LUN_DISABLE	dev/m1543reg.h	96;"	d
M1543C_SIO_LUN_ENABLE	dev/m1543reg.h	95;"	d
M1543C_SIO_LUN_FDC	dev/m1543reg.h	101;"	d
M1543C_SIO_LUN_HOTK	dev/m1543reg.h	107;"	d
M1543C_SIO_LUN_IDX	dev/m1543reg.h	78;"	d
M1543C_SIO_LUN_KBC	dev/m1543reg.h	105;"	d
M1543C_SIO_LUN_LPT	dev/m1543reg.h	102;"	d
M1543C_SIO_LUN_UART3	dev/m1543reg.h	106;"	d
M1543C_SIO_RESET	dev/m1543reg.h	77;"	d
M1543C_SMCCI	dev/m1543reg.h	59;"	d
M1543C_SMCCII	dev/m1543reg.h	60;"	d
M1543C_VEND_ID_REG	dev/m1543reg.h	36;"	d
MAIN_INTERRUPT_CAUSE_HIGH	dev/mv64360reg.h	1064;"	d
MAIN_INTERRUPT_CAUSE_LOW	dev/mv64360reg.h	1063;"	d
MAIN_ROUTING_REGISTER	dev/gt64240reg.h	1207;"	d
MAIN_ROUTING_REGISTER	dev/gt64260reg.h	1198;"	d
MAIN_ROUTING_REGISTER	dev/gt64420reg.h	943;"	d
MAIN_ROUTING_REGISTER	dev/gt96132reg.h	288;"	d
MAIN_ROUTING_REGISTER	dev/mv64340reg.h	1057;"	d
MANUFACTURER_ST	dev/flash_st.c	78;"	d	file:
MAXCDNAME	include/arpa/nameser.h	115;"	d
MAXDFLSRCH	include/resolv.h	99;"	d
MAXDNAME	include/arpa/nameser.h	114;"	d
MAXDNSLUS	include/resolv.h	102;"	d
MAXDNSRCH	include/resolv.h	100;"	d
MAXLABEL	include/arpa/nameser.h	116;"	d
MAXLN	include/stdio.h	91;"	d
MAXLN	lib.c	109;"	d	file:
MAXNS	include/resolv.h	98;"	d
MAXRESOLVSORT	include/resolv.h	105;"	d
MAX_AC	include/pmon.h	61;"	d
MAX_AC	lib.c	177;"	d	file:
MAX_BPT	include/pmon.h	59;"	d
MAX_DIACR	dev/kbd.h	20;"	d
MAX_KEY_BASE64	include/arpa/nameser.h	248;"	d
MAX_MATCH	include/linux/zutil.h	52;"	d
MAX_MD5RSA_KEY_BYTES	include/arpa/nameser.h	246;"	d
MAX_MD5RSA_KEY_PART_BITS	include/arpa/nameser.h	244;"	d
MAX_MEM_LEVEL	include/linux/zconf.h	38;"	d
MAX_NR_FUNC	dev/kbd.h	158;"	d
MAX_NR_KEYMAPS	dev/kbd.h	241;"	d
MAX_WBITS	include/linux/zconf.h	47;"	d
MB_CUR_MAX	include/stdlib.h	88;"	d
MCDMA_GLOBAL_CONTROL_REGISTER	dev/gt96132reg.h	825;"	d
MCR_DRS	dev/ns16550.h	150;"	d
MCR_DTR	dev/ns16550.h	152;"	d
MCR_IENABLE	dev/ns16550.h	149;"	d
MCR_LOOPBACK	dev/ns16550.h	148;"	d
MCR_RTS	dev/ns16550.h	151;"	d
MCSC_EXTENDED_INTERRUPT_CAUSE	dev/gt96132reg.h	828;"	d
MCSC_EXTENDED_INTERRUPT_MASK	dev/gt96132reg.h	831;"	d
MCSC_GLOBAL_CONTROL_REGISTER	dev/gt96132reg.h	841;"	d
MCSC_GLOBAL_INTERRUPT_CAUSE	dev/gt96132reg.h	827;"	d
MCSC_GLOBAL_INTERRUPT_MASK	dev/gt96132reg.h	830;"	d
MEM13OHM	dev/mpc107reg.h	137;"	d
MEM20OHM	dev/mpc107reg.h	138;"	d
MEM40OHM	dev/mpc107reg.h	139;"	d
MEM8OHM	dev/mpc107reg.h	136;"	d
MEMCLK13OHM	dev/mpc107reg.h	145;"	d
MEMCLK20OHM	dev/mpc107reg.h	146;"	d
MEMCLK40OHM	dev/mpc107reg.h	147;"	d
MEMCLK8OHM	dev/mpc107reg.h	144;"	d
MINIMUM_ACCESS_WIN_SIZE	dev/gt64420reg.h	128;"	d
MINIMUM_DEVICE_WINDOW_SIZE	dev/gt64420reg.h	126;"	d
MINIMUM_MEM_BANK_SIZE	dev/gt64420reg.h	125;"	d
MINIMUM_PCI_WINDOW_SIZE	dev/gt64420reg.h	127;"	d
MIN_MATCH	include/linux/zutil.h	51;"	d
MIN_MD5RSA_KEY_PART_BITS	include/arpa/nameser.h	243;"	d
MIPSInst	include/ri.h	3;"	d
MIPSInst_CACHEOP	include/ri.h	22;"	d
MIPSInst_CACHESEL	include/ri.h	25;"	d
MIPSInst_FD	include/ri.h	46;"	d
MIPSInst_FFMT	include/ri.h	37;"	d
MIPSInst_FMA_FFMT	include/ri.h	55;"	d
MIPSInst_FMA_FUNC	include/ri.h	52;"	d
MIPSInst_FR	include/ri.h	49;"	d
MIPSInst_FS	include/ri.h	43;"	d
MIPSInst_FT	include/ri.h	40;"	d
MIPSInst_FUNC	include/ri.h	34;"	d
MIPSInst_JTARGET	include/ri.h	9;"	d
MIPSInst_OPCODE	include/ri.h	6;"	d
MIPSInst_RD	include/ri.h	28;"	d
MIPSInst_RE	include/ri.h	31;"	d
MIPSInst_RS	include/ri.h	12;"	d
MIPSInst_RT	include/ri.h	15;"	d
MIPSInst_SIMM	include/ri.h	18;"	d
MIPSInst_UIMM	include/ri.h	19;"	d
MODE_ACK	include/arpa/telnet.h	172;"	d
MODE_B	include/arpa/ftp.h	89;"	d
MODE_C	include/arpa/ftp.h	90;"	d
MODE_ECHO	include/arpa/telnet.h	180;"	d
MODE_EDIT	include/arpa/telnet.h	170;"	d
MODE_FLOW	include/arpa/telnet.h	179;"	d
MODE_FORCE	include/arpa/telnet.h	183;"	d
MODE_INBIN	include/arpa/telnet.h	181;"	d
MODE_LIT_ECHO	include/arpa/telnet.h	174;"	d
MODE_MASK	include/arpa/telnet.h	176;"	d
MODE_OUTBIN	include/arpa/telnet.h	182;"	d
MODE_S	include/arpa/ftp.h	88;"	d
MODE_SOFT_TAB	include/arpa/telnet.h	173;"	d
MODE_TRAPSIG	include/arpa/telnet.h	171;"	d
MODULE_LICENSE	include/linux/module.h	2;"	d
MPC106_CONF_BASE	dev/mpc106reg.h	53;"	d
MPC106_CONF_DATA	dev/mpc106reg.h	54;"	d
MPC106_PCI_CMD	dev/mpc106reg.h	138;"	d
MPC106_PCI_CONF_SPACE	dev/mpc106reg.h	50;"	d
MPC106_PCI_CPUMEM	dev/mpc106reg.h	58;"	d
MPC106_PCI_DEVICE	dev/mpc106reg.h	137;"	d
MPC106_PCI_PMGMT	dev/mpc106reg.h	142;"	d
MPC106_PCI_REVID	dev/mpc106reg.h	140;"	d
MPC106_PCI_STAT	dev/mpc106reg.h	139;"	d
MPC106_PCI_VENDOR	dev/mpc106reg.h	136;"	d
MPC106_P_ISA_IO_SPACE	dev/mpc106reg.h	45;"	d
MPC106_P_PCI_MEM_SPACE	dev/mpc106reg.h	42;"	d
MPC106_REGOFFS	dev/mpc106reg.h	55;"	d
MPC106_V_ISA_IO_SPACE	dev/mpc106reg.h	46;"	d
MPC106_V_PCI_IO_SPACE	dev/mpc106reg.h	47;"	d
MPC106_V_PCI_MEM_SPACE	dev/mpc106reg.h	41;"	d
MPC107_CFG_AMBOR	dev/mpc107reg.h	122;"	d
MPC107_CFG_CDCR	dev/mpc107reg.h	99;"	d
MPC107_CFG_ECC_ERCNT	dev/mpc107reg.h	114;"	d
MPC107_CFG_ECC_ERRTRG	dev/mpc107reg.h	115;"	d
MPC107_CFG_EMEND_03	dev/mpc107reg.h	108;"	d
MPC107_CFG_EMEND_47	dev/mpc107reg.h	109;"	d
MPC107_CFG_EMSTA_03	dev/mpc107reg.h	104;"	d
MPC107_CFG_EMSTA_47	dev/mpc107reg.h	105;"	d
MPC107_CFG_ERR_ADDR	dev/mpc107reg.h	121;"	d
MPC107_CFG_ERR_DR1	dev/mpc107reg.h	117;"	d
MPC107_CFG_ERR_DR2	dev/mpc107reg.h	119;"	d
MPC107_CFG_ERR_EN1	dev/mpc107reg.h	116;"	d
MPC107_CFG_ERR_EN2	dev/mpc107reg.h	118;"	d
MPC107_CFG_ERR_PCIBUS	dev/mpc107reg.h	120;"	d
MPC107_CFG_EUMBBAR	dev/mpc107reg.h	101;"	d
MPC107_CFG_LMBAR	dev/mpc107reg.h	93;"	d
MPC107_CFG_MBEN	dev/mpc107reg.h	110;"	d
MPC107_CFG_MCFG1	dev/mpc107reg.h	123;"	d
MPC107_CFG_MCFG2	dev/mpc107reg.h	124;"	d
MPC107_CFG_MCFG3	dev/mpc107reg.h	125;"	d
MPC107_CFG_MCFG4	dev/mpc107reg.h	126;"	d
MPC107_CFG_MDCR	dev/mpc107reg.h	100;"	d
MPC107_CFG_MEND_03	dev/mpc107reg.h	106;"	d
MPC107_CFG_MEND_47	dev/mpc107reg.h	107;"	d
MPC107_CFG_MPMR	dev/mpc107reg.h	111;"	d
MPC107_CFG_MSTA_03	dev/mpc107reg.h	102;"	d
MPC107_CFG_MSTA_47	dev/mpc107reg.h	103;"	d
MPC107_CFG_ODCR	dev/mpc107reg.h	98;"	d
MPC107_CFG_PACR	dev/mpc107reg.h	95;"	d
MPC107_CFG_PCSRBAR	dev/mpc107reg.h	94;"	d
MPC107_CFG_PICR1	dev/mpc107reg.h	112;"	d
MPC107_CFG_PICR2	dev/mpc107reg.h	113;"	d
MPC107_CFG_PMCR1	dev/mpc107reg.h	96;"	d
MPC107_CFG_PMCR2	dev/mpc107reg.h	97;"	d
MPC107_CONF_ADDR	dev/mpc107reg.h	49;"	d
MPC107_CONF_ADDR	dev/mpc107reg.h	69;"	d
MPC107_CONF_DATA	dev/mpc107reg.h	50;"	d
MPC107_CONF_DATA	dev/mpc107reg.h	70;"	d
MPC107_EUMBAR	dev/mpc107reg.h	152;"	d
MPC107_I2C_ADR	dev/mpc107reg.h	157;"	d
MPC107_I2C_CCR	dev/mpc107reg.h	159;"	d
MPC107_I2C_CDR	dev/mpc107reg.h	161;"	d
MPC107_I2C_CSR	dev/mpc107reg.h	160;"	d
MPC107_I2C_FDR	dev/mpc107reg.h	158;"	d
MPC107_INT_ACK	dev/mpc107reg.h	71;"	d
MPC107_IRQ0	dev/mpc107reg.h	177;"	d
MPC107_IRQ1	dev/mpc107reg.h	178;"	d
MPC107_IRQ10	dev/mpc107reg.h	187;"	d
MPC107_IRQ11	dev/mpc107reg.h	188;"	d
MPC107_IRQ12	dev/mpc107reg.h	189;"	d
MPC107_IRQ13	dev/mpc107reg.h	190;"	d
MPC107_IRQ14	dev/mpc107reg.h	191;"	d
MPC107_IRQ15	dev/mpc107reg.h	192;"	d
MPC107_IRQ2	dev/mpc107reg.h	179;"	d
MPC107_IRQ3	dev/mpc107reg.h	180;"	d
MPC107_IRQ4	dev/mpc107reg.h	181;"	d
MPC107_IRQ5	dev/mpc107reg.h	182;"	d
MPC107_IRQ6	dev/mpc107reg.h	183;"	d
MPC107_IRQ7	dev/mpc107reg.h	184;"	d
MPC107_IRQ8	dev/mpc107reg.h	185;"	d
MPC107_IRQ9	dev/mpc107reg.h	186;"	d
MPC107_PCI_CMD	dev/mpc107reg.h	87;"	d
MPC107_PCI_IO_BASE	dev/mpc107reg.h	45;"	d
MPC107_PCI_IO_BASE	dev/mpc107reg.h	64;"	d
MPC107_PCI_IO_SIZE	dev/mpc107reg.h	47;"	d
MPC107_PCI_IO_SIZE	dev/mpc107reg.h	65;"	d
MPC107_PCI_ISA_IO_BASE	dev/mpc107reg.h	46;"	d
MPC107_PCI_ISA_IO_BASE	dev/mpc107reg.h	66;"	d
MPC107_PCI_ISA_IO_SIZE	dev/mpc107reg.h	67;"	d
MPC107_PCI_MEM_BASE	dev/mpc107reg.h	43;"	d
MPC107_PCI_MEM_BASE	dev/mpc107reg.h	62;"	d
MPC107_PCI_MEM_SIZE	dev/mpc107reg.h	44;"	d
MPC107_PCI_MEM_SIZE	dev/mpc107reg.h	63;"	d
MPC107_PCI_STAT	dev/mpc107reg.h	88;"	d
MPC107_PICR1_FLASH_WR_EN	dev/mpc107reg.h	128;"	d
MPC_CFG_AD	dev/mpc107reg.h	199;"	d
MPC_CFG_RD	dev/mpc107reg.h	212;"	d
MPC_CFG_RD3	dev/mpc107reg.h	216;"	d
MPC_CFG_RWR	dev/mpc107reg.h	208;"	d
MPC_CFG_WR	dev/mpc107reg.h	203;"	d
MPP_CNTRL0	dev/gt64240reg.h	133;"	d
MPP_CNTRL0	dev/gt64260reg.h	124;"	d
MPP_CNTRL0	dev/gt64420reg.h	117;"	d
MPP_CNTRL0	dev/mv64340reg.h	133;"	d
MPP_CNTRL1	dev/gt64240reg.h	134;"	d
MPP_CNTRL1	dev/gt64260reg.h	125;"	d
MPP_CNTRL1	dev/gt64420reg.h	118;"	d
MPP_CNTRL1	dev/mv64340reg.h	134;"	d
MPP_CNTRL2	dev/gt64240reg.h	135;"	d
MPP_CNTRL2	dev/gt64260reg.h	126;"	d
MPP_CNTRL2	dev/gt64420reg.h	119;"	d
MPP_CNTRL2	dev/mv64340reg.h	135;"	d
MPP_CNTRL3	dev/gt64240reg.h	136;"	d
MPP_CNTRL3	dev/gt64260reg.h	127;"	d
MPP_CNTRL3	dev/gt64420reg.h	120;"	d
MPP_CNTRL3	dev/mv64340reg.h	136;"	d
MPP_CONTROL0	dev/gt64240reg.h	1245;"	d
MPP_CONTROL0	dev/gt64260reg.h	1236;"	d
MPP_CONTROL0	dev/gt64420reg.h	981;"	d
MPP_CONTROL0	dev/mv64340reg.h	1097;"	d
MPP_CONTROL0	dev/mv64360reg.h	1082;"	d
MPP_CONTROL1	dev/gt64240reg.h	1246;"	d
MPP_CONTROL1	dev/gt64260reg.h	1237;"	d
MPP_CONTROL1	dev/gt64420reg.h	982;"	d
MPP_CONTROL1	dev/mv64340reg.h	1098;"	d
MPP_CONTROL1	dev/mv64360reg.h	1083;"	d
MPP_CONTROL2	dev/gt64240reg.h	1247;"	d
MPP_CONTROL2	dev/gt64260reg.h	1238;"	d
MPP_CONTROL2	dev/gt64420reg.h	983;"	d
MPP_CONTROL2	dev/mv64340reg.h	1099;"	d
MPP_CONTROL2	dev/mv64360reg.h	1084;"	d
MPP_CONTROL3	dev/gt64240reg.h	1248;"	d
MPP_CONTROL3	dev/gt64260reg.h	1239;"	d
MPP_CONTROL3	dev/gt64420reg.h	984;"	d
MPP_CONTROL3	dev/mv64340reg.h	1100;"	d
MPP_CONTROL3	dev/mv64360reg.h	1085;"	d
MPSC0_ACCESS_PROTECTION_REG	dev/mv64360reg.h	848;"	d
MPSC0_CAUSE	dev/gt64240reg.h	1320;"	d
MPSC0_CAUSE	dev/gt64260reg.h	1294;"	d
MPSC0_CAUSE	dev/mv64340reg.h	1170;"	d
MPSC0_CAUSE_REGISTER	dev/gt96132reg.h	300;"	d
MPSC0_MAIN_CONFIGURATION_HIGH	dev/gt64240reg.h	1270;"	d
MPSC0_MAIN_CONFIGURATION_HIGH	dev/gt64260reg.h	1261;"	d
MPSC0_MAIN_CONFIGURATION_HIGH	dev/mv64340reg.h	1120;"	d
MPSC0_MAIN_CONFIGURATION_LOW	dev/gt64240reg.h	1269;"	d
MPSC0_MAIN_CONFIGURATION_LOW	dev/gt64260reg.h	1260;"	d
MPSC0_MAIN_CONFIGURATION_LOW	dev/mv64340reg.h	1119;"	d
MPSC0_MAIN_CONFIG_HIGH	dev/gt96132reg.h	602;"	d
MPSC0_MAIN_CONFIG_LOW	dev/gt96132reg.h	601;"	d
MPSC0_MASK	dev/gt64240reg.h	1321;"	d
MPSC0_MASK	dev/gt64260reg.h	1295;"	d
MPSC0_MASK	dev/mv64340reg.h	1171;"	d
MPSC0_MASK_REGISTER	dev/gt96132reg.h	301;"	d
MPSC0_PROTOCOL_CONFIG	dev/gt96132reg.h	603;"	d
MPSC0_PROTOCOL_CONFIGURATION	dev/gt64240reg.h	1271;"	d
MPSC0_PROTOCOL_CONFIGURATION	dev/gt64260reg.h	1262;"	d
MPSC0_PROTOCOL_CONFIGURATION	dev/mv64340reg.h	1121;"	d
MPSC1_ACCESS_PROTECTION_REG	dev/mv64360reg.h	849;"	d
MPSC1_CAUSE	dev/gt64240reg.h	1322;"	d
MPSC1_CAUSE	dev/gt64260reg.h	1296;"	d
MPSC1_CAUSE	dev/mv64340reg.h	1172;"	d
MPSC1_CAUSE_REGISTER	dev/gt96132reg.h	302;"	d
MPSC1_MAIN_CONFIGURATION_HIGH	dev/gt64240reg.h	1287;"	d
MPSC1_MAIN_CONFIGURATION_HIGH	dev/gt64260reg.h	1278;"	d
MPSC1_MAIN_CONFIGURATION_HIGH	dev/mv64340reg.h	1137;"	d
MPSC1_MAIN_CONFIGURATION_LOW	dev/gt64240reg.h	1286;"	d
MPSC1_MAIN_CONFIGURATION_LOW	dev/gt64260reg.h	1277;"	d
MPSC1_MAIN_CONFIGURATION_LOW	dev/mv64340reg.h	1136;"	d
MPSC1_MAIN_CONFIG_HIGH	dev/gt96132reg.h	616;"	d
MPSC1_MAIN_CONFIG_LOW	dev/gt96132reg.h	615;"	d
MPSC1_MASK	dev/gt64240reg.h	1323;"	d
MPSC1_MASK	dev/gt64260reg.h	1297;"	d
MPSC1_MASK	dev/mv64340reg.h	1173;"	d
MPSC1_MASK_REGISTER	dev/gt96132reg.h	303;"	d
MPSC1_PROTOCOL_CONFIG	dev/gt96132reg.h	617;"	d
MPSC1_PROTOCOL_CONFIGURATION	dev/gt64240reg.h	1288;"	d
MPSC1_PROTOCOL_CONFIGURATION	dev/gt64260reg.h	1279;"	d
MPSC1_PROTOCOL_CONFIGURATION	dev/mv64340reg.h	1138;"	d
MPSC2_CAUSE	dev/gt64240reg.h	1324;"	d
MPSC2_CAUSE	dev/mv64340reg.h	1174;"	d
MPSC2_CAUSE_REGISTER	dev/gt96132reg.h	304;"	d
MPSC2_MAIN_CONFIGURATION_HIGH	dev/gt64240reg.h	1304;"	d
MPSC2_MAIN_CONFIGURATION_HIGH	dev/mv64340reg.h	1154;"	d
MPSC2_MAIN_CONFIGURATION_LOW	dev/gt64240reg.h	1303;"	d
MPSC2_MAIN_CONFIGURATION_LOW	dev/mv64340reg.h	1153;"	d
MPSC2_MAIN_CONFIG_HIGH	dev/gt96132reg.h	630;"	d
MPSC2_MAIN_CONFIG_LOW	dev/gt96132reg.h	629;"	d
MPSC2_MASK	dev/gt64240reg.h	1325;"	d
MPSC2_MASK	dev/mv64340reg.h	1175;"	d
MPSC2_MASK_REGISTER	dev/gt96132reg.h	305;"	d
MPSC2_PROTOCOL_CONFIG	dev/gt96132reg.h	631;"	d
MPSC2_PROTOCOL_CONFIGURATION	dev/gt64240reg.h	1305;"	d
MPSC2_PROTOCOL_CONFIGURATION	dev/mv64340reg.h	1155;"	d
MPSC3_CAUSE_REGISTER	dev/gt96132reg.h	306;"	d
MPSC3_MAIN_CONFIG_HIGH	dev/gt96132reg.h	644;"	d
MPSC3_MAIN_CONFIG_LOW	dev/gt96132reg.h	643;"	d
MPSC3_MASK_REGISTER	dev/gt96132reg.h	307;"	d
MPSC3_PROTOCOL_CONFIG	dev/gt96132reg.h	645;"	d
MPSC4_CAUSE_REGISTER	dev/gt96132reg.h	308;"	d
MPSC4_MAIN_CONFIG_HIGH	dev/gt96132reg.h	658;"	d
MPSC4_MAIN_CONFIG_LOW	dev/gt96132reg.h	657;"	d
MPSC4_MASK_REGISTER	dev/gt96132reg.h	309;"	d
MPSC4_PROTOCOL_CONFIG	dev/gt96132reg.h	659;"	d
MPSC5_CAUSE_REGISTER	dev/gt96132reg.h	310;"	d
MPSC5_MAIN_CONFIG_HIGH	dev/gt96132reg.h	672;"	d
MPSC5_MAIN_CONFIG_LOW	dev/gt96132reg.h	671;"	d
MPSC5_MASK_REGISTER	dev/gt96132reg.h	311;"	d
MPSC5_PROTOCOL_CONFIG	dev/gt96132reg.h	673;"	d
MPSC6_CAUSE_REGISTER	dev/gt96132reg.h	312;"	d
MPSC6_MAIN_CONFIG_HIGH	dev/gt96132reg.h	686;"	d
MPSC6_MAIN_CONFIG_LOW	dev/gt96132reg.h	685;"	d
MPSC6_MASK_REGISTER	dev/gt96132reg.h	313;"	d
MPSC6_PROTOCOL_CONFIG	dev/gt96132reg.h	687;"	d
MPSC7_CAUSE_REGISTER	dev/gt96132reg.h	314;"	d
MPSC7_MAIN_CONFIG_HIGH	dev/gt96132reg.h	700;"	d
MPSC7_MAIN_CONFIG_LOW	dev/gt96132reg.h	699;"	d
MPSC7_MASK_REGISTER	dev/gt96132reg.h	315;"	d
MPSC7_PROTOCOL_CONFIG	dev/gt96132reg.h	701;"	d
MPSC_0_ADDRESS_CONTROL_HIGH	dev/gt64240reg.h	1001;"	d
MPSC_0_ADDRESS_CONTROL_HIGH	dev/gt64260reg.h	992;"	d
MPSC_0_ADDRESS_CONTROL_HIGH	dev/mv64340reg.h	940;"	d
MPSC_0_ADDRESS_CONTROL_LOW	dev/gt64240reg.h	1000;"	d
MPSC_0_ADDRESS_CONTROL_LOW	dev/gt64260reg.h	991;"	d
MPSC_0_ADDRESS_CONTROL_LOW	dev/mv64340reg.h	939;"	d
MPSC_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS	dev/gt64240reg.h	1002;"	d
MPSC_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS	dev/gt64260reg.h	993;"	d
MPSC_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS	dev/mv64340reg.h	941;"	d
MPSC_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS	dev/gt64240reg.h	1004;"	d
MPSC_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS	dev/gt64260reg.h	995;"	d
MPSC_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS	dev/mv64340reg.h	943;"	d
MPSC_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS	dev/gt64240reg.h	1003;"	d
MPSC_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS	dev/gt64260reg.h	994;"	d
MPSC_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS	dev/mv64340reg.h	942;"	d
MPSC_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS	dev/gt64240reg.h	1005;"	d
MPSC_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS	dev/gt64260reg.h	996;"	d
MPSC_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS	dev/mv64340reg.h	944;"	d
MPSC_1_ADDRESS_CONTROL_HIGH	dev/gt64240reg.h	1007;"	d
MPSC_1_ADDRESS_CONTROL_HIGH	dev/gt64260reg.h	998;"	d
MPSC_1_ADDRESS_CONTROL_HIGH	dev/mv64340reg.h	946;"	d
MPSC_1_ADDRESS_CONTROL_LOW	dev/gt64240reg.h	1006;"	d
MPSC_1_ADDRESS_CONTROL_LOW	dev/gt64260reg.h	997;"	d
MPSC_1_ADDRESS_CONTROL_LOW	dev/mv64340reg.h	945;"	d
MPSC_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS	dev/gt64240reg.h	1008;"	d
MPSC_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS	dev/gt64260reg.h	999;"	d
MPSC_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS	dev/mv64340reg.h	947;"	d
MPSC_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS	dev/gt64240reg.h	1010;"	d
MPSC_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS	dev/gt64260reg.h	1001;"	d
MPSC_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS	dev/mv64340reg.h	949;"	d
MPSC_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS	dev/gt64240reg.h	1009;"	d
MPSC_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS	dev/gt64260reg.h	1000;"	d
MPSC_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS	dev/mv64340reg.h	948;"	d
MPSC_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS	dev/gt64240reg.h	1011;"	d
MPSC_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS	dev/gt64260reg.h	1002;"	d
MPSC_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS	dev/mv64340reg.h	950;"	d
MPSC_2_ADDRESS_CONTROL_HIGH	dev/gt64240reg.h	1013;"	d
MPSC_2_ADDRESS_CONTROL_HIGH	dev/gt64260reg.h	1004;"	d
MPSC_2_ADDRESS_CONTROL_HIGH	dev/mv64340reg.h	952;"	d
MPSC_2_ADDRESS_CONTROL_LOW	dev/gt64240reg.h	1012;"	d
MPSC_2_ADDRESS_CONTROL_LOW	dev/gt64260reg.h	1003;"	d
MPSC_2_ADDRESS_CONTROL_LOW	dev/mv64340reg.h	951;"	d
MPSC_2_RECEIVE_BUFFER_PCI_HIGH_ADDRESS	dev/gt64240reg.h	1014;"	d
MPSC_2_RECEIVE_BUFFER_PCI_HIGH_ADDRESS	dev/gt64260reg.h	1005;"	d
MPSC_2_RECEIVE_BUFFER_PCI_HIGH_ADDRESS	dev/mv64340reg.h	953;"	d
MPSC_2_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS	dev/gt64240reg.h	1016;"	d
MPSC_2_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS	dev/gt64260reg.h	1007;"	d
MPSC_2_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS	dev/mv64340reg.h	955;"	d
MPSC_2_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS	dev/gt64240reg.h	1015;"	d
MPSC_2_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS	dev/gt64260reg.h	1006;"	d
MPSC_2_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS	dev/mv64340reg.h	954;"	d
MPSC_2_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS	dev/gt64240reg.h	1017;"	d
MPSC_2_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS	dev/gt64260reg.h	1008;"	d
MPSC_2_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS	dev/mv64340reg.h	956;"	d
MPSC_CAUSE_REG	dev/gt64420reg.h	1011;"	d
MPSC_CAUSE_REG	dev/mv64360reg.h	878;"	d
MPSC_CHAN0_REG1	dev/gt96132reg.h	604;"	d
MPSC_CHAN0_REG10	dev/gt96132reg.h	613;"	d
MPSC_CHAN0_REG11	dev/gt96132reg.h	614;"	d
MPSC_CHAN0_REG2	dev/gt96132reg.h	605;"	d
MPSC_CHAN0_REG3	dev/gt96132reg.h	606;"	d
MPSC_CHAN0_REG4	dev/gt96132reg.h	607;"	d
MPSC_CHAN0_REG5	dev/gt96132reg.h	608;"	d
MPSC_CHAN0_REG6	dev/gt96132reg.h	609;"	d
MPSC_CHAN0_REG7	dev/gt96132reg.h	610;"	d
MPSC_CHAN0_REG8	dev/gt96132reg.h	611;"	d
MPSC_CHAN0_REG9	dev/gt96132reg.h	612;"	d
MPSC_CHAN1_REG1	dev/gt96132reg.h	618;"	d
MPSC_CHAN1_REG10	dev/gt96132reg.h	627;"	d
MPSC_CHAN1_REG11	dev/gt96132reg.h	628;"	d
MPSC_CHAN1_REG2	dev/gt96132reg.h	619;"	d
MPSC_CHAN1_REG3	dev/gt96132reg.h	620;"	d
MPSC_CHAN1_REG4	dev/gt96132reg.h	621;"	d
MPSC_CHAN1_REG5	dev/gt96132reg.h	622;"	d
MPSC_CHAN1_REG6	dev/gt96132reg.h	623;"	d
MPSC_CHAN1_REG7	dev/gt96132reg.h	624;"	d
MPSC_CHAN1_REG8	dev/gt96132reg.h	625;"	d
MPSC_CHAN1_REG9	dev/gt96132reg.h	626;"	d
MPSC_CHAN2_REG1	dev/gt96132reg.h	632;"	d
MPSC_CHAN2_REG10	dev/gt96132reg.h	641;"	d
MPSC_CHAN2_REG11	dev/gt96132reg.h	642;"	d
MPSC_CHAN2_REG2	dev/gt96132reg.h	633;"	d
MPSC_CHAN2_REG3	dev/gt96132reg.h	634;"	d
MPSC_CHAN2_REG4	dev/gt96132reg.h	635;"	d
MPSC_CHAN2_REG5	dev/gt96132reg.h	636;"	d
MPSC_CHAN2_REG6	dev/gt96132reg.h	637;"	d
MPSC_CHAN2_REG7	dev/gt96132reg.h	638;"	d
MPSC_CHAN2_REG8	dev/gt96132reg.h	639;"	d
MPSC_CHAN2_REG9	dev/gt96132reg.h	640;"	d
MPSC_CHAN3_REG1	dev/gt96132reg.h	646;"	d
MPSC_CHAN3_REG10	dev/gt96132reg.h	655;"	d
MPSC_CHAN3_REG11	dev/gt96132reg.h	656;"	d
MPSC_CHAN3_REG2	dev/gt96132reg.h	647;"	d
MPSC_CHAN3_REG3	dev/gt96132reg.h	648;"	d
MPSC_CHAN3_REG4	dev/gt96132reg.h	649;"	d
MPSC_CHAN3_REG5	dev/gt96132reg.h	650;"	d
MPSC_CHAN3_REG6	dev/gt96132reg.h	651;"	d
MPSC_CHAN3_REG7	dev/gt96132reg.h	652;"	d
MPSC_CHAN3_REG8	dev/gt96132reg.h	653;"	d
MPSC_CHAN3_REG9	dev/gt96132reg.h	654;"	d
MPSC_CHAN4_REG1	dev/gt96132reg.h	660;"	d
MPSC_CHAN4_REG10	dev/gt96132reg.h	669;"	d
MPSC_CHAN4_REG11	dev/gt96132reg.h	670;"	d
MPSC_CHAN4_REG2	dev/gt96132reg.h	661;"	d
MPSC_CHAN4_REG3	dev/gt96132reg.h	662;"	d
MPSC_CHAN4_REG4	dev/gt96132reg.h	663;"	d
MPSC_CHAN4_REG5	dev/gt96132reg.h	664;"	d
MPSC_CHAN4_REG6	dev/gt96132reg.h	665;"	d
MPSC_CHAN4_REG7	dev/gt96132reg.h	666;"	d
MPSC_CHAN4_REG8	dev/gt96132reg.h	667;"	d
MPSC_CHAN4_REG9	dev/gt96132reg.h	668;"	d
MPSC_CHAN5_REG1	dev/gt96132reg.h	674;"	d
MPSC_CHAN5_REG10	dev/gt96132reg.h	683;"	d
MPSC_CHAN5_REG11	dev/gt96132reg.h	684;"	d
MPSC_CHAN5_REG2	dev/gt96132reg.h	675;"	d
MPSC_CHAN5_REG3	dev/gt96132reg.h	676;"	d
MPSC_CHAN5_REG4	dev/gt96132reg.h	677;"	d
MPSC_CHAN5_REG5	dev/gt96132reg.h	678;"	d
MPSC_CHAN5_REG6	dev/gt96132reg.h	679;"	d
MPSC_CHAN5_REG7	dev/gt96132reg.h	680;"	d
MPSC_CHAN5_REG8	dev/gt96132reg.h	681;"	d
MPSC_CHAN5_REG9	dev/gt96132reg.h	682;"	d
MPSC_CHAN6_REG1	dev/gt96132reg.h	688;"	d
MPSC_CHAN6_REG10	dev/gt96132reg.h	697;"	d
MPSC_CHAN6_REG11	dev/gt96132reg.h	698;"	d
MPSC_CHAN6_REG2	dev/gt96132reg.h	689;"	d
MPSC_CHAN6_REG3	dev/gt96132reg.h	690;"	d
MPSC_CHAN6_REG4	dev/gt96132reg.h	691;"	d
MPSC_CHAN6_REG5	dev/gt96132reg.h	692;"	d
MPSC_CHAN6_REG6	dev/gt96132reg.h	693;"	d
MPSC_CHAN6_REG7	dev/gt96132reg.h	694;"	d
MPSC_CHAN6_REG8	dev/gt96132reg.h	695;"	d
MPSC_CHAN6_REG9	dev/gt96132reg.h	696;"	d
MPSC_CHAN7_REG1	dev/gt96132reg.h	702;"	d
MPSC_CHAN7_REG10	dev/gt96132reg.h	711;"	d
MPSC_CHAN7_REG11	dev/gt96132reg.h	712;"	d
MPSC_CHAN7_REG2	dev/gt96132reg.h	703;"	d
MPSC_CHAN7_REG3	dev/gt96132reg.h	704;"	d
MPSC_CHAN7_REG4	dev/gt96132reg.h	705;"	d
MPSC_CHAN7_REG5	dev/gt96132reg.h	706;"	d
MPSC_CHAN7_REG6	dev/gt96132reg.h	707;"	d
MPSC_CHAN7_REG7	dev/gt96132reg.h	708;"	d
MPSC_CHAN7_REG8	dev/gt96132reg.h	709;"	d
MPSC_CHAN7_REG9	dev/gt96132reg.h	710;"	d
MPSC_CHANNEL_REG1	dev/gt64420reg.h	1017;"	d
MPSC_CHANNEL_REG1	dev/mv64360reg.h	884;"	d
MPSC_CHANNEL_REG10	dev/gt64420reg.h	1026;"	d
MPSC_CHANNEL_REG10	dev/mv64360reg.h	893;"	d
MPSC_CHANNEL_REG2	dev/gt64420reg.h	1018;"	d
MPSC_CHANNEL_REG2	dev/mv64360reg.h	885;"	d
MPSC_CHANNEL_REG3	dev/gt64420reg.h	1019;"	d
MPSC_CHANNEL_REG3	dev/mv64360reg.h	886;"	d
MPSC_CHANNEL_REG4	dev/gt64420reg.h	1020;"	d
MPSC_CHANNEL_REG4	dev/mv64360reg.h	887;"	d
MPSC_CHANNEL_REG5	dev/gt64420reg.h	1021;"	d
MPSC_CHANNEL_REG5	dev/mv64360reg.h	888;"	d
MPSC_CHANNEL_REG6	dev/gt64420reg.h	1022;"	d
MPSC_CHANNEL_REG6	dev/mv64360reg.h	889;"	d
MPSC_CHANNEL_REG7	dev/gt64420reg.h	1023;"	d
MPSC_CHANNEL_REG7	dev/mv64360reg.h	890;"	d
MPSC_CHANNEL_REG8	dev/gt64420reg.h	1024;"	d
MPSC_CHANNEL_REG8	dev/mv64360reg.h	891;"	d
MPSC_CHANNEL_REG9	dev/gt64420reg.h	1025;"	d
MPSC_CHANNEL_REG9	dev/mv64360reg.h	892;"	d
MPSC_MAIN_CONFIG_HIGH	dev/gt64420reg.h	1015;"	d
MPSC_MAIN_CONFIG_HIGH	dev/mv64360reg.h	882;"	d
MPSC_MAIN_CONFIG_LOW	dev/gt64420reg.h	1014;"	d
MPSC_MAIN_CONFIG_LOW	dev/mv64360reg.h	881;"	d
MPSC_MASK_REG	dev/gt64420reg.h	1012;"	d
MPSC_MASK_REG	dev/mv64360reg.h	879;"	d
MPSC_PROTOCOL_CONFIG	dev/gt64420reg.h	1016;"	d
MPSC_PROTOCOL_CONFIG	dev/mv64360reg.h	883;"	d
MPSC_ROUTING_REG	dev/gt64420reg.h	1005;"	d
MPSC_ROUTING_REG	dev/mv64360reg.h	872;"	d
MPSC_RX_CLOCK_ROUTING_REG	dev/gt64420reg.h	1006;"	d
MPSC_RX_CLOCK_ROUTING_REG	dev/mv64360reg.h	873;"	d
MPSC_TX_CLOCK_ROUTING_REG	dev/gt64420reg.h	1007;"	d
MPSC_TX_CLOCK_ROUTING_REG	dev/mv64360reg.h	874;"	d
MSI_0TRIGGER_TIMER	dev/gt64240reg.h	665;"	d
MSI_0TRIGGER_TIMER	dev/gt64260reg.h	656;"	d
MSI_0TRIGGER_TIMER	dev/mv64340reg.h	543;"	d
MSI_1TRIGGER_TIMER	dev/gt64240reg.h	666;"	d
MSI_1TRIGGER_TIMER	dev/gt64260reg.h	657;"	d
MSI_1TRIGGER_TIMER	dev/mv64340reg.h	544;"	d
MSI_TRIGGER_TIMER	dev/gt64420reg.h	487;"	d
MSR_CTS	dev/ns16550.h	169;"	d
MSR_DCD	dev/ns16550.h	166;"	d
MSR_DCTS	dev/ns16550.h	173;"	d
MSR_DDCD	dev/ns16550.h	170;"	d
MSR_DDSR	dev/ns16550.h	172;"	d
MSR_DSR	dev/ns16550.h	168;"	d
MSR_RI	dev/ns16550.h	167;"	d
MSR_TERI	dev/ns16550.h	171;"	d
MULTI_GT_REGISTER	dev/gt96132reg.h	72;"	d
Msg	include/queue.h	/^typedef unsigned char Msg;$/;"	t
NAMESERVER_PORT	include/arpa/nameser.h	128;"	d
NBBY	include/types.h	186;"	d
NCC	include/termio.h	95;"	d
NETDB_INTERNAL	include/netdb.h	132;"	d
NETDB_SUCCESS	include/netdb.h	133;"	d
NEW_ENV_VALUE	include/arpa/telnet.h	259;"	d
NEW_ENV_VAR	include/arpa/telnet.h	258;"	d
NFDBITS	include/types.h	198;"	d
NFLASH	include/tgt/flash.h	1;"	d
NI_DGRAM	include/netdb.h	150;"	d
NI_MAXHOST	include/netdb.h	152;"	d
NI_MAXSERV	include/netdb.h	153;"	d
NI_NAMEREQD	include/netdb.h	149;"	d
NI_NOFQDN	include/netdb.h	148;"	d
NI_NUMERICHOST	include/netdb.h	146;"	d
NI_NUMERICSERV	include/netdb.h	147;"	d
NMAX	include/linux/zutil.h	74;"	d
NMOD_FLASH_AMD	include/tgt/flash.h	2;"	d
NMOD_FLASH_INTEL	include/tgt/flash.h	3;"	d
NMOD_FLASH_SST	include/tgt/flash.h	4;"	d
NMOD_FLASH_WINBOND	include/tgt/flash.h	5;"	d
NOERROR	include/arpa/nameser.h	141;"	d
NOP	include/arpa/telnet.h	59;"	d
NOTIMP	include/arpa/nameser.h	145;"	d
NO_ADDRESS	include/netdb.h	138;"	d
NO_BPT	include/pmon.h	64;"	d
NO_DATA	include/netdb.h	137;"	d
NO_RECOVERY	include/netdb.h	136;"	d
NR_KEYS	dev/kbd.h	180;"	d
NS16550HZ	include/tgt/bonito.h	28;"	d
NS16550_CFCR	dev/ns16550.h	100;"	d
NS16550_CHANA	dev/ns16550.h	38;"	d
NS16550_CHANB	dev/ns16550.h	39;"	d
NS16550_DATA	dev/ns16550.h	96;"	d
NS16550_FIFO	dev/ns16550.h	99;"	d
NS16550_IER	dev/ns16550.h	97;"	d
NS16550_IIR	dev/ns16550.h	98;"	d
NS16550_LSR	dev/ns16550.h	102;"	d
NS16550_MCR	dev/ns16550.h	101;"	d
NS16550_MSR	dev/ns16550.h	103;"	d
NS16550_SCR	dev/ns16550.h	104;"	d
NSLC	include/arpa/telnet.h	216;"	d
NSREG	dev/ns16550.h	93;"	d
NS_NOTIFY_OP	include/arpa/nameser.h	137;"	d
NTELOPTS	include/arpa/telnet.h	129;"	d
NULL	include/stddef.h	57;"	d
NULL	include/stdio.h	19;"	d
NULL	include/stdlib.h	77;"	d
NULL	include/stdlib.h	79;"	d
NULL	include/string.h	45;"	d
NULL	include/time.h	51;"	d
NULL	include/unistd.h	51;"	d
NVAR	include/pmonenv.h	37;"	d
NVRAM_OFFS	include/tgt/bonito.h	35;"	d
NVRAM_OFFS	include/tgt/bonito.h	40;"	d
NVRAM_SECSIZE	include/tgt/bonito.h	34;"	d
NVRAM_SECSIZE	include/tgt/bonito.h	39;"	d
NVRAM_SIZE	include/tgt/bonito.h	33;"	d
NVRAM_SIZE	include/tgt/bonito.h	38;"	d
NXDOMAIN	include/arpa/nameser.h	144;"	d
OF	include/linux/zconf.h	54;"	d
OF	include/linux/zconf.h	56;"	d
OF	include/linux/zutil.h	/^typedef uLong (ZEXPORT *check_func) OF((uLong check, const Bytef *buf,$/;"	t
OLD_ENV_VALUE	include/arpa/telnet.h	257;"	d
OLD_ENV_VAR	include/arpa/telnet.h	256;"	d
ONLCR	include/termio.h	28;"	d
OPEN_MAX	include/stdio.h	87;"	d
OPEN_MAX	include/stdio.h	89;"	d
OPTIONS_CC	Makefile	/^OPTIONS_CC = -g -DHAVE_NVENV -DNVRAM_IN_FLASH$/;"	m
OPTIONS_LD	Makefile	/^OPTIONS_LD = -g$/;"	m
OP_BAUD	include/termio.h	70;"	d
OP_CLOSE	include/termio.h	75;"	d
OP_FLUSH	include/termio.h	72;"	d
OP_INIT	include/termio.h	65;"	d
OP_OPEN	include/termio.h	74;"	d
OP_RESET	include/termio.h	73;"	d
OP_RX	include/termio.h	67;"	d
OP_RXRDY	include/termio.h	68;"	d
OP_RXSTOP	include/termio.h	71;"	d
OP_TX	include/termio.h	66;"	d
OP_TXRDY	include/termio.h	69;"	d
OP_XBAUD	include/termio.h	76;"	d
OS_CODE	include/linux/zutil.h	62;"	d
OUTBOUND_DOORBELL_REGISTER_CPU_SIDE	dev/gt64240reg.h	959;"	d
OUTBOUND_DOORBELL_REGISTER_CPU_SIDE	dev/gt64260reg.h	950;"	d
OUTBOUND_DOORBELL_REGISTER_CPU_SIDE	dev/gt64420reg.h	647;"	d
OUTBOUND_DOORBELL_REGISTER_CPU_SIDE	dev/gt96132reg.h	406;"	d
OUTBOUND_DOORBELL_REGISTER_CPU_SIDE	dev/mv64340reg.h	783;"	d
OUTBOUND_DOORBELL_REGISTER_PCI_SIDE	dev/gt64240reg.h	936;"	d
OUTBOUND_DOORBELL_REGISTER_PCI_SIDE	dev/gt64260reg.h	927;"	d
OUTBOUND_DOORBELL_REGISTER_PCI_SIDE	dev/gt64420reg.h	624;"	d
OUTBOUND_DOORBELL_REGISTER_PCI_SIDE	dev/gt96132reg.h	383;"	d
OUTBOUND_DOORBELL_REGISTER_PCI_SIDE	dev/mv64340reg.h	760;"	d
OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE	dev/gt64240reg.h	970;"	d
OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE	dev/gt64260reg.h	961;"	d
OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE	dev/gt64420reg.h	658;"	d
OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE	dev/gt96132reg.h	417;"	d
OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE	dev/mv64340reg.h	794;"	d
OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE	dev/gt64240reg.h	947;"	d
OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE	dev/gt64260reg.h	938;"	d
OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE	dev/gt64420reg.h	635;"	d
OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE	dev/gt96132reg.h	394;"	d
OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE	dev/mv64340reg.h	771;"	d
OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE	dev/gt64240reg.h	971;"	d
OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE	dev/gt64260reg.h	962;"	d
OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE	dev/gt64420reg.h	659;"	d
OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE	dev/gt96132reg.h	418;"	d
OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE	dev/mv64340reg.h	795;"	d
OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE	dev/gt64240reg.h	948;"	d
OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE	dev/gt64260reg.h	939;"	d
OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE	dev/gt64420reg.h	636;"	d
OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE	dev/gt96132reg.h	395;"	d
OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE	dev/mv64340reg.h	772;"	d
OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE	dev/gt64240reg.h	960;"	d
OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE	dev/gt64260reg.h	951;"	d
OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE	dev/gt64420reg.h	648;"	d
OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE	dev/gt96132reg.h	407;"	d
OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE	dev/mv64340reg.h	784;"	d
OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE	dev/gt64240reg.h	937;"	d
OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE	dev/gt64260reg.h	928;"	d
OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE	dev/gt64420reg.h	625;"	d
OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE	dev/gt96132reg.h	384;"	d
OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE	dev/mv64340reg.h	761;"	d
OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE	dev/gt64240reg.h	961;"	d
OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE	dev/gt64260reg.h	952;"	d
OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE	dev/gt64420reg.h	649;"	d
OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE	dev/gt96132reg.h	408;"	d
OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE	dev/mv64340reg.h	785;"	d
OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE	dev/gt64240reg.h	938;"	d
OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE	dev/gt64260reg.h	929;"	d
OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE	dev/gt64420reg.h	626;"	d
OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE	dev/gt96132reg.h	385;"	d
OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE	dev/mv64340reg.h	762;"	d
OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE	dev/gt64240reg.h	954;"	d
OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE	dev/gt64260reg.h	945;"	d
OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE	dev/gt64420reg.h	642;"	d
OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE	dev/gt96132reg.h	401;"	d
OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE	dev/mv64340reg.h	778;"	d
OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE	dev/gt64240reg.h	931;"	d
OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE	dev/gt64260reg.h	922;"	d
OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE	dev/gt64420reg.h	619;"	d
OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE	dev/gt96132reg.h	378;"	d
OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE	dev/mv64340reg.h	755;"	d
OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE	dev/gt64240reg.h	955;"	d
OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE	dev/gt64260reg.h	946;"	d
OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE	dev/gt64420reg.h	643;"	d
OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE	dev/gt96132reg.h	402;"	d
OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE	dev/mv64340reg.h	779;"	d
OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE	dev/gt64240reg.h	932;"	d
OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE	dev/gt64260reg.h	923;"	d
OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE	dev/gt64420reg.h	620;"	d
OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE	dev/gt96132reg.h	379;"	d
OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE	dev/mv64340reg.h	756;"	d
OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE	dev/gt64240reg.h	972;"	d
OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE	dev/gt64260reg.h	963;"	d
OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE	dev/gt64420reg.h	660;"	d
OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE	dev/gt96132reg.h	419;"	d
OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE	dev/mv64340reg.h	796;"	d
OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE	dev/gt64240reg.h	949;"	d
OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE	dev/gt64260reg.h	940;"	d
OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE	dev/gt64420reg.h	637;"	d
OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE	dev/gt96132reg.h	396;"	d
OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE	dev/mv64340reg.h	773;"	d
OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE	dev/gt64240reg.h	973;"	d
OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE	dev/gt64260reg.h	964;"	d
OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE	dev/gt64420reg.h	661;"	d
OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE	dev/gt96132reg.h	420;"	d
OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE	dev/mv64340reg.h	797;"	d
OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE	dev/gt64240reg.h	950;"	d
OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE	dev/gt64260reg.h	941;"	d
OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE	dev/gt64420reg.h	638;"	d
OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE	dev/gt96132reg.h	397;"	d
OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE	dev/mv64340reg.h	774;"	d
OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE	dev/gt64240reg.h	963;"	d
OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE	dev/gt64260reg.h	954;"	d
OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE	dev/gt64420reg.h	651;"	d
OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE	dev/gt96132reg.h	410;"	d
OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE	dev/mv64340reg.h	787;"	d
OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE	dev/gt64240reg.h	940;"	d
OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE	dev/gt64260reg.h	931;"	d
OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE	dev/gt64420reg.h	628;"	d
OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE	dev/gt96132reg.h	387;"	d
OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE	dev/mv64340reg.h	764;"	d
Optdesc	include/pmon.h	/^typedef struct Optdesc {$/;"	s
Optdesc	include/pmon.h	/^} Optdesc;$/;"	t	typeref:struct:Optdesc
PACKETSZ	include/arpa/nameser.h	113;"	d
PASSWORDSIZE	include/url.h	41;"	d
PATSZ	include/pmon.h	62;"	d
PCHISTSZ	include/debugger.h	41;"	d
PCI0_COMMAND	dev/gt64240reg.h	102;"	d
PCI0_COMMAND	dev/gt64260reg.h	93;"	d
PCI0_COMMAND	dev/mv64340reg.h	102;"	d
PCI0_COMMAND_STATUS_REG	dev/gt64240reg.h	816;"	d
PCI0_COMMAND_STATUS_REG	dev/gt64260reg.h	807;"	d
PCI0_COMMAND_STATUS_REG	dev/mv64340reg.h	653;"	d
PCI0_DLL_STATUS_CONTROL	dev/mv64340reg.h	530;"	d
PCI0_IO_HI	dev/gt64240reg.h	105;"	d
PCI0_IO_HI	dev/gt64260reg.h	96;"	d
PCI0_IO_HI	dev/mv64340reg.h	105;"	d
PCI0_IO_LO	dev/gt64240reg.h	104;"	d
PCI0_IO_LO	dev/gt64260reg.h	95;"	d
PCI0_IO_LO	dev/mv64340reg.h	104;"	d
PCI0_MEM0_HI	dev/gt64240reg.h	107;"	d
PCI0_MEM0_HI	dev/gt64260reg.h	98;"	d
PCI0_MEM0_HI	dev/mv64340reg.h	107;"	d
PCI0_MEM0_LO	dev/gt64240reg.h	106;"	d
PCI0_MEM0_LO	dev/gt64260reg.h	97;"	d
PCI0_MEM0_LO	dev/mv64340reg.h	106;"	d
PCI0_PADS_CALIBRATION	dev/mv64340reg.h	532;"	d
PCI1_COMMAND	dev/gt64240reg.h	103;"	d
PCI1_COMMAND	dev/gt64260reg.h	94;"	d
PCI1_COMMAND	dev/mv64340reg.h	103;"	d
PCI1_COMMAND_STATUS_REG	dev/gt64240reg.h	817;"	d
PCI1_COMMAND_STATUS_REG	dev/gt64260reg.h	808;"	d
PCI1_COMMAND_STATUS_REG	dev/mv64340reg.h	654;"	d
PCI1_DLL_STATUS_CONTROL	dev/mv64340reg.h	531;"	d
PCI1_IO_HI	dev/gt64240reg.h	109;"	d
PCI1_IO_HI	dev/gt64260reg.h	100;"	d
PCI1_IO_HI	dev/mv64340reg.h	109;"	d
PCI1_IO_LO	dev/gt64240reg.h	108;"	d
PCI1_IO_LO	dev/gt64260reg.h	99;"	d
PCI1_IO_LO	dev/mv64340reg.h	108;"	d
PCI1_MEM0_HI	dev/gt64240reg.h	111;"	d
PCI1_MEM0_HI	dev/gt64260reg.h	102;"	d
PCI1_MEM0_HI	dev/mv64340reg.h	111;"	d
PCI1_MEM0_HIGH	dev/gt64240reg.h	124;"	d
PCI1_MEM0_HIGH	dev/gt64260reg.h	115;"	d
PCI1_MEM0_HIGH	dev/mv64340reg.h	124;"	d
PCI1_MEM0_LO	dev/gt64240reg.h	110;"	d
PCI1_MEM0_LO	dev/gt64260reg.h	101;"	d
PCI1_MEM0_LO	dev/mv64340reg.h	110;"	d
PCI1_MEM0_LOW	dev/gt64240reg.h	123;"	d
PCI1_MEM0_LOW	dev/gt64260reg.h	114;"	d
PCI1_MEM0_LOW	dev/mv64340reg.h	123;"	d
PCI1_PADS_CALIBRATION	dev/mv64340reg.h	533;"	d
PCI20OHM	dev/mpc107reg.h	135;"	d
PCI25OHM	dev/mpc107reg.h	133;"	d
PCI32_BAR_VALUE	dev/cpc710.h	41;"	d
PCI50OHM	dev/mpc107reg.h	132;"	d
PCI64_BAR_VALUE	dev/cpc710.h	42;"	d
PCICFG_ACR	dev/cpc710.h	65;"	d
PCICFG_BARPP	dev/cpc710.h	77;"	d
PCICFG_BARPS	dev/cpc710.h	76;"	d
PCICFG_BIODLK	dev/cpc710.h	82;"	d
PCICFG_BPMDLK	dev/cpc710.h	80;"	d
PCICFG_CFGA	dev/cpc710.h	72;"	d
PCICFG_CFGD	dev/cpc710.h	73;"	d
PCICFG_CRR	dev/cpc710.h	63;"	d
PCICFG_CSTAT	dev/cpc710.h	88;"	d
PCICFG_CTLRO	dev/cpc710.h	71;"	d
PCICFG_CTLRW	dev/cpc710.h	70;"	d
PCICFG_DLKCTRL	dev/cpc710.h	84;"	d
PCICFG_DLKDEV	dev/cpc710.h	85;"	d
PCICFG_INTA	dev/cpc710.h	60;"	d
PCICFG_INT_SET	dev/cpc710.h	87;"	d
PCICFG_IOSIZE	dev/cpc710.h	67;"	d
PCICFG_IT_ADD_RESET	dev/cpc710.h	86;"	d
PCICFG_PCIDG	dev/cpc710.h	59;"	d
PCICFG_PIBAR	dev/cpc710.h	61;"	d
PCICFG_PLSSR	dev/cpc710.h	89;"	d
PCICFG_PMBAR	dev/cpc710.h	62;"	d
PCICFG_PMSIZE	dev/cpc710.h	66;"	d
PCICFG_PPBAR	dev/cpc710.h	79;"	d
PCICFG_PPSIZE	dev/cpc710.h	75;"	d
PCICFG_PR	dev/cpc710.h	64;"	d
PCICFG_PSBAR	dev/cpc710.h	78;"	d
PCICFG_PSEA	dev/cpc710.h	58;"	d
PCICFG_PSSIZE	dev/cpc710.h	74;"	d
PCICFG_SIBAR	dev/cpc710.h	69;"	d
PCICFG_SMBAR	dev/cpc710.h	68;"	d
PCICFG_TIODLK	dev/cpc710.h	83;"	d
PCICFG_TPMDLK	dev/cpc710.h	81;"	d
PCICLK13OHM	dev/mpc107reg.h	141;"	d
PCICLK20OHM	dev/mpc107reg.h	142;"	d
PCICLK40OHM	dev/mpc107reg.h	143;"	d
PCICLK8OHM	dev/mpc107reg.h	140;"	d
PCI_0ACCESS_CONTROL_BASE_0_HIGH	dev/gt64240reg.h	678;"	d
PCI_0ACCESS_CONTROL_BASE_0_HIGH	dev/gt64260reg.h	669;"	d
PCI_0ACCESS_CONTROL_BASE_0_HIGH	dev/mv64340reg.h	556;"	d
PCI_0ACCESS_CONTROL_BASE_0_LOW	dev/gt64240reg.h	677;"	d
PCI_0ACCESS_CONTROL_BASE_0_LOW	dev/gt64260reg.h	668;"	d
PCI_0ACCESS_CONTROL_BASE_0_LOW	dev/mv64340reg.h	555;"	d
PCI_0ACCESS_CONTROL_BASE_1_HIGH	dev/gt64240reg.h	681;"	d
PCI_0ACCESS_CONTROL_BASE_1_HIGH	dev/gt64260reg.h	672;"	d
PCI_0ACCESS_CONTROL_BASE_1_HIGH	dev/mv64340reg.h	559;"	d
PCI_0ACCESS_CONTROL_BASE_1_LOW	dev/gt64240reg.h	680;"	d
PCI_0ACCESS_CONTROL_BASE_1_LOW	dev/gt64260reg.h	671;"	d
PCI_0ACCESS_CONTROL_BASE_1_LOW	dev/mv64340reg.h	558;"	d
PCI_0ACCESS_CONTROL_BASE_2_HIGH	dev/gt64240reg.h	684;"	d
PCI_0ACCESS_CONTROL_BASE_2_HIGH	dev/gt64260reg.h	675;"	d
PCI_0ACCESS_CONTROL_BASE_2_HIGH	dev/mv64340reg.h	562;"	d
PCI_0ACCESS_CONTROL_BASE_2_LOW	dev/gt64240reg.h	683;"	d
PCI_0ACCESS_CONTROL_BASE_2_LOW	dev/gt64260reg.h	674;"	d
PCI_0ACCESS_CONTROL_BASE_2_LOW	dev/mv64340reg.h	561;"	d
PCI_0ACCESS_CONTROL_BASE_3_HIGH	dev/gt64240reg.h	687;"	d
PCI_0ACCESS_CONTROL_BASE_3_HIGH	dev/gt64260reg.h	678;"	d
PCI_0ACCESS_CONTROL_BASE_3_HIGH	dev/mv64340reg.h	565;"	d
PCI_0ACCESS_CONTROL_BASE_3_LOW	dev/gt64240reg.h	686;"	d
PCI_0ACCESS_CONTROL_BASE_3_LOW	dev/gt64260reg.h	677;"	d
PCI_0ACCESS_CONTROL_BASE_3_LOW	dev/mv64340reg.h	564;"	d
PCI_0ACCESS_CONTROL_BASE_4_HIGH	dev/gt64240reg.h	690;"	d
PCI_0ACCESS_CONTROL_BASE_4_HIGH	dev/gt64260reg.h	681;"	d
PCI_0ACCESS_CONTROL_BASE_4_HIGH	dev/mv64340reg.h	568;"	d
PCI_0ACCESS_CONTROL_BASE_4_LOW	dev/gt64240reg.h	689;"	d
PCI_0ACCESS_CONTROL_BASE_4_LOW	dev/gt64260reg.h	680;"	d
PCI_0ACCESS_CONTROL_BASE_4_LOW	dev/mv64340reg.h	567;"	d
PCI_0ACCESS_CONTROL_BASE_5_HIGH	dev/gt64240reg.h	693;"	d
PCI_0ACCESS_CONTROL_BASE_5_HIGH	dev/gt64260reg.h	684;"	d
PCI_0ACCESS_CONTROL_BASE_5_HIGH	dev/mv64340reg.h	571;"	d
PCI_0ACCESS_CONTROL_BASE_5_LOW	dev/gt64240reg.h	692;"	d
PCI_0ACCESS_CONTROL_BASE_5_LOW	dev/gt64260reg.h	683;"	d
PCI_0ACCESS_CONTROL_BASE_5_LOW	dev/mv64340reg.h	570;"	d
PCI_0ACCESS_CONTROL_BASE_6_HIGH	dev/gt64240reg.h	696;"	d
PCI_0ACCESS_CONTROL_BASE_6_HIGH	dev/gt64260reg.h	687;"	d
PCI_0ACCESS_CONTROL_BASE_6_HIGH	dev/mv64340reg.h	574;"	d
PCI_0ACCESS_CONTROL_BASE_6_LOW	dev/gt64240reg.h	695;"	d
PCI_0ACCESS_CONTROL_BASE_6_LOW	dev/gt64260reg.h	686;"	d
PCI_0ACCESS_CONTROL_BASE_6_LOW	dev/mv64340reg.h	573;"	d
PCI_0ACCESS_CONTROL_BASE_7_HIGH	dev/gt64240reg.h	699;"	d
PCI_0ACCESS_CONTROL_BASE_7_HIGH	dev/gt64260reg.h	690;"	d
PCI_0ACCESS_CONTROL_BASE_7_HIGH	dev/mv64340reg.h	577;"	d
PCI_0ACCESS_CONTROL_BASE_7_LOW	dev/gt64240reg.h	698;"	d
PCI_0ACCESS_CONTROL_BASE_7_LOW	dev/gt64260reg.h	689;"	d
PCI_0ACCESS_CONTROL_BASE_7_LOW	dev/mv64340reg.h	576;"	d
PCI_0ACCESS_CONTROL_TOP_0	dev/gt64240reg.h	679;"	d
PCI_0ACCESS_CONTROL_TOP_0	dev/gt64260reg.h	670;"	d
PCI_0ACCESS_CONTROL_TOP_0	dev/mv64340reg.h	557;"	d
PCI_0ACCESS_CONTROL_TOP_1	dev/gt64240reg.h	682;"	d
PCI_0ACCESS_CONTROL_TOP_1	dev/gt64260reg.h	673;"	d
PCI_0ACCESS_CONTROL_TOP_1	dev/mv64340reg.h	560;"	d
PCI_0ACCESS_CONTROL_TOP_2	dev/gt64240reg.h	685;"	d
PCI_0ACCESS_CONTROL_TOP_2	dev/gt64260reg.h	676;"	d
PCI_0ACCESS_CONTROL_TOP_2	dev/mv64340reg.h	563;"	d
PCI_0ACCESS_CONTROL_TOP_3	dev/gt64240reg.h	688;"	d
PCI_0ACCESS_CONTROL_TOP_3	dev/gt64260reg.h	679;"	d
PCI_0ACCESS_CONTROL_TOP_3	dev/mv64340reg.h	566;"	d
PCI_0ACCESS_CONTROL_TOP_4	dev/gt64240reg.h	691;"	d
PCI_0ACCESS_CONTROL_TOP_4	dev/gt64260reg.h	682;"	d
PCI_0ACCESS_CONTROL_TOP_4	dev/mv64340reg.h	569;"	d
PCI_0ACCESS_CONTROL_TOP_5	dev/gt64240reg.h	694;"	d
PCI_0ACCESS_CONTROL_TOP_5	dev/gt64260reg.h	685;"	d
PCI_0ACCESS_CONTROL_TOP_5	dev/mv64340reg.h	572;"	d
PCI_0ACCESS_CONTROL_TOP_6	dev/gt64240reg.h	697;"	d
PCI_0ACCESS_CONTROL_TOP_6	dev/gt64260reg.h	688;"	d
PCI_0ACCESS_CONTROL_TOP_6	dev/mv64340reg.h	575;"	d
PCI_0ACCESS_CONTROL_TOP_7	dev/gt64240reg.h	700;"	d
PCI_0ACCESS_CONTROL_TOP_7	dev/gt64260reg.h	691;"	d
PCI_0ACCESS_CONTROL_TOP_7	dev/mv64340reg.h	578;"	d
PCI_0ADDRESS_DECODE_CONTROL	dev/gt64240reg.h	650;"	d
PCI_0ADDRESS_DECODE_CONTROL	dev/gt64260reg.h	641;"	d
PCI_0ADDRESS_DECODE_CONTROL	dev/mv64340reg.h	523;"	d
PCI_0ARBITER_CONTROL	dev/gt64240reg.h	667;"	d
PCI_0ARBITER_CONTROL	dev/gt64260reg.h	658;"	d
PCI_0ARBITER_CONTROL	dev/gt96132reg.h	357;"	d
PCI_0ARBITER_CONTROL	dev/mv64340reg.h	545;"	d
PCI_0BASE_ADDRESS_REGISTERS_ENABLE	dev/gt64240reg.h	588;"	d
PCI_0BASE_ADDRESS_REGISTERS_ENABLE	dev/gt64260reg.h	579;"	d
PCI_0BASE_ADDRESS_REGISTERS_ENABLE	dev/gt96132reg.h	232;"	d
PCI_0BASE_ADDRESS_REGISTERS_ENABLE	dev/mv64340reg.h	489;"	d
PCI_0COMMAND	dev/gt64240reg.h	657;"	d
PCI_0COMMAND	dev/gt64260reg.h	648;"	d
PCI_0COMMAND	dev/gt96132reg.h	226;"	d
PCI_0COMMAND	dev/mv64340reg.h	535;"	d
PCI_0CONFIGURATION_ADDRESS	dev/gt64240reg.h	766;"	d
PCI_0CONFIGURATION_ADDRESS	dev/gt64260reg.h	757;"	d
PCI_0CONFIGURATION_ADDRESS	dev/gt96132reg.h	241;"	d
PCI_0CONFIGURATION_ADDRESS	dev/mv64340reg.h	616;"	d
PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER	dev/gt64240reg.h	767;"	d
PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER	dev/gt64260reg.h	758;"	d
PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER	dev/gt96132reg.h	242;"	d
PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER	dev/mv64340reg.h	617;"	d
PCI_0CPU_BAR_SIZE	dev/gt64240reg.h	560;"	d
PCI_0CPU_BAR_SIZE	dev/gt64260reg.h	551;"	d
PCI_0CPU_BASE_ADDRESS_REMAP	dev/gt64240reg.h	618;"	d
PCI_0CPU_BASE_ADDRESS_REMAP	dev/gt64260reg.h	609;"	d
PCI_0CROSS_BAR_CONTROL_HIGH	dev/gt64240reg.h	671;"	d
PCI_0CROSS_BAR_CONTROL_HIGH	dev/gt64260reg.h	662;"	d
PCI_0CROSS_BAR_CONTROL_HIGH	dev/mv64340reg.h	550;"	d
PCI_0CROSS_BAR_CONTROL_LOW	dev/gt64240reg.h	670;"	d
PCI_0CROSS_BAR_CONTROL_LOW	dev/gt64260reg.h	661;"	d
PCI_0CROSS_BAR_CONTROL_LOW	dev/mv64340reg.h	549;"	d
PCI_0CROSS_BAR_TIMEOUT	dev/gt64240reg.h	672;"	d
PCI_0CROSS_BAR_TIMEOUT	dev/gt64260reg.h	663;"	d
PCI_0CROSS_BAR_TIMEOUT	dev/mv64340reg.h	551;"	d
PCI_0CS_0_BANK_SIZE	dev/gt64240reg.h	544;"	d
PCI_0CS_0_BANK_SIZE	dev/gt64260reg.h	535;"	d
PCI_0CS_0_BANK_SIZE	dev/mv64340reg.h	469;"	d
PCI_0CS_0_BASE_ADDRESS_REMAP	dev/gt64240reg.h	598;"	d
PCI_0CS_0_BASE_ADDRESS_REMAP	dev/gt64260reg.h	589;"	d
PCI_0CS_0_BASE_ADDRESS_REMAP	dev/mv64340reg.h	499;"	d
PCI_0CS_1_BANK_SIZE	dev/gt64240reg.h	546;"	d
PCI_0CS_1_BANK_SIZE	dev/gt64260reg.h	537;"	d
PCI_0CS_1_BANK_SIZE	dev/mv64340reg.h	471;"	d
PCI_0CS_1_BASE_ADDRESS_REMAP	dev/gt64240reg.h	600;"	d
PCI_0CS_1_BASE_ADDRESS_REMAP	dev/gt64260reg.h	591;"	d
PCI_0CS_1_BASE_ADDRESS_REMAP	dev/mv64340reg.h	501;"	d
PCI_0CS_2_0_BANK_SIZE	dev/gt96132reg.h	230;"	d
PCI_0CS_2_0_BASE_ADDRESS_REMAP	dev/gt96132reg.h	236;"	d
PCI_0CS_2_BANK_SIZE	dev/gt64240reg.h	548;"	d
PCI_0CS_2_BANK_SIZE	dev/gt64260reg.h	539;"	d
PCI_0CS_2_BANK_SIZE	dev/mv64340reg.h	473;"	d
PCI_0CS_2_BASE_ADDRESS_REMAP	dev/gt64240reg.h	602;"	d
PCI_0CS_2_BASE_ADDRESS_REMAP	dev/gt64260reg.h	593;"	d
PCI_0CS_2_BASE_ADDRESS_REMAP	dev/mv64340reg.h	503;"	d
PCI_0CS_3_BANK_SIZE	dev/gt64240reg.h	550;"	d
PCI_0CS_3_BANK_SIZE	dev/gt64260reg.h	541;"	d
PCI_0CS_3_BANK_SIZE	dev/mv64340reg.h	475;"	d
PCI_0CS_3_BASE_ADDRESS_REMAP	dev/gt64240reg.h	604;"	d
PCI_0CS_3_BASE_ADDRESS_REMAP	dev/gt64260reg.h	595;"	d
PCI_0CS_3_BASE_ADDRESS_REMAP	dev/mv64340reg.h	505;"	d
PCI_0CS_3_BOOTCS_ADDRESS_REMAP	dev/gt96132reg.h	237;"	d
PCI_0CS_3_BOOTCS_BANK_SIZE	dev/gt96132reg.h	231;"	d
PCI_0CS_BOOTCS_BASE_ADDRESS_REMAP	dev/gt64240reg.h	606;"	d
PCI_0CS_BOOTCS_BASE_ADDRESS_REMAP	dev/gt64260reg.h	597;"	d
PCI_0CS_BOOTCS_BASE_ADDRESS_REMAP	dev/mv64340reg.h	507;"	d
PCI_0CS_BOOT_BANK_SIZE	dev/gt64240reg.h	552;"	d
PCI_0CS_BOOT_BANK_SIZE	dev/gt64260reg.h	543;"	d
PCI_0CS_BOOT_BANK_SIZE	dev/mv64340reg.h	477;"	d
PCI_0DAC_BOOTCS_BANK_SIZE	dev/gt64240reg.h	578;"	d
PCI_0DAC_BOOTCS_BANK_SIZE	dev/gt64260reg.h	569;"	d
PCI_0DAC_BOOTCS_BASE_ADDRESS_REMAP	dev/gt64240reg.h	636;"	d
PCI_0DAC_BOOTCS_BASE_ADDRESS_REMAP	dev/gt64260reg.h	627;"	d
PCI_0DAC_CPU_BAR_SIZE	dev/gt64240reg.h	584;"	d
PCI_0DAC_CPU_BAR_SIZE	dev/gt64260reg.h	575;"	d
PCI_0DAC_CPU_BASE_ADDRESS_REMAP	dev/gt64240reg.h	646;"	d
PCI_0DAC_CPU_BASE_ADDRESS_REMAP	dev/gt64260reg.h	637;"	d
PCI_0DAC_CS_0_BANK_SIZE	dev/gt64240reg.h	570;"	d
PCI_0DAC_CS_0_BANK_SIZE	dev/gt64260reg.h	561;"	d
PCI_0DAC_CS_0_BASE_ADDRESS_REMAP	dev/gt64240reg.h	628;"	d
PCI_0DAC_CS_0_BASE_ADDRESS_REMAP	dev/gt64260reg.h	619;"	d
PCI_0DAC_CS_1_BANK_SIZE	dev/gt64240reg.h	572;"	d
PCI_0DAC_CS_1_BANK_SIZE	dev/gt64260reg.h	563;"	d
PCI_0DAC_CS_1_BASE_ADDRESS_REMAP	dev/gt64240reg.h	630;"	d
PCI_0DAC_CS_1_BASE_ADDRESS_REMAP	dev/gt64260reg.h	621;"	d
PCI_0DAC_CS_2_BANK_SIZE	dev/gt64240reg.h	574;"	d
PCI_0DAC_CS_2_BANK_SIZE	dev/gt64260reg.h	565;"	d
PCI_0DAC_CS_2_BASE_ADDRESS_REMAP	dev/gt64240reg.h	632;"	d
PCI_0DAC_CS_2_BASE_ADDRESS_REMAP	dev/gt64260reg.h	623;"	d
PCI_0DAC_CS_3_BANK_SIZE	dev/gt64240reg.h	576;"	d
PCI_0DAC_CS_3_BANK_SIZE	dev/gt64260reg.h	567;"	d
PCI_0DAC_CS_3_BASE_ADDRESS_REMAP	dev/gt64240reg.h	634;"	d
PCI_0DAC_CS_3_BASE_ADDRESS_REMAP	dev/gt64260reg.h	625;"	d
PCI_0DAC_P2P_MEM0_BAR_SIZE	dev/gt64240reg.h	580;"	d
PCI_0DAC_P2P_MEM0_BAR_SIZE	dev/gt64260reg.h	571;"	d
PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH	dev/gt64240reg.h	640;"	d
PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH	dev/gt64260reg.h	631;"	d
PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW	dev/gt64240reg.h	638;"	d
PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW	dev/gt64260reg.h	629;"	d
PCI_0DAC_P2P_MEM1_BAR_SIZE	dev/gt64240reg.h	582;"	d
PCI_0DAC_P2P_MEM1_BAR_SIZE	dev/gt64260reg.h	573;"	d
PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH	dev/gt64240reg.h	644;"	d
PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH	dev/gt64260reg.h	635;"	d
PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW	dev/gt64240reg.h	642;"	d
PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW	dev/gt64260reg.h	633;"	d
PCI_0DAC_SCS_0_BANK_SIZE	dev/gt64240reg.h	562;"	d
PCI_0DAC_SCS_0_BANK_SIZE	dev/gt64260reg.h	553;"	d
PCI_0DAC_SCS_0_BASE_ADDRESS_REMAP	dev/gt64240reg.h	620;"	d
PCI_0DAC_SCS_0_BASE_ADDRESS_REMAP	dev/gt64260reg.h	611;"	d
PCI_0DAC_SCS_1_BANK_SIZE	dev/gt64240reg.h	564;"	d
PCI_0DAC_SCS_1_BANK_SIZE	dev/gt64260reg.h	555;"	d
PCI_0DAC_SCS_1_BASE_ADDRESS_REMAP	dev/gt64240reg.h	622;"	d
PCI_0DAC_SCS_1_BASE_ADDRESS_REMAP	dev/gt64260reg.h	613;"	d
PCI_0DAC_SCS_2_BANK_SIZE	dev/gt64240reg.h	566;"	d
PCI_0DAC_SCS_2_BANK_SIZE	dev/gt64260reg.h	557;"	d
PCI_0DAC_SCS_2_BASE_ADDRESS_REMAP	dev/gt64240reg.h	624;"	d
PCI_0DAC_SCS_2_BASE_ADDRESS_REMAP	dev/gt64260reg.h	615;"	d
PCI_0DAC_SCS_3_BANK_SIZE	dev/gt64240reg.h	568;"	d
PCI_0DAC_SCS_3_BANK_SIZE	dev/gt64260reg.h	559;"	d
PCI_0DAC_SCS_3_BASE_ADDRESS_REMAP	dev/gt64240reg.h	626;"	d
PCI_0DAC_SCS_3_BASE_ADDRESS_REMAP	dev/gt64260reg.h	617;"	d
PCI_0ERROR_ADDRESS_HIGH	dev/gt64240reg.h	779;"	d
PCI_0ERROR_ADDRESS_HIGH	dev/gt64260reg.h	770;"	d
PCI_0ERROR_ADDRESS_HIGH	dev/mv64340reg.h	631;"	d
PCI_0ERROR_ADDRESS_LOW	dev/gt64240reg.h	778;"	d
PCI_0ERROR_ADDRESS_LOW	dev/gt64260reg.h	769;"	d
PCI_0ERROR_ADDRESS_LOW	dev/mv64340reg.h	630;"	d
PCI_0ERROR_ATTRIBUTE	dev/mv64340reg.h	632;"	d
PCI_0ERROR_CAUSE	dev/gt64240reg.h	783;"	d
PCI_0ERROR_CAUSE	dev/gt64260reg.h	774;"	d
PCI_0ERROR_CAUSE	dev/mv64340reg.h	634;"	d
PCI_0ERROR_COMMAND	dev/gt64240reg.h	782;"	d
PCI_0ERROR_COMMAND	dev/gt64260reg.h	773;"	d
PCI_0ERROR_COMMAND	dev/mv64340reg.h	633;"	d
PCI_0ERROR_DATA_HIGH	dev/gt64240reg.h	781;"	d
PCI_0ERROR_DATA_HIGH	dev/gt64260reg.h	772;"	d
PCI_0ERROR_DATA_LOW	dev/gt64240reg.h	780;"	d
PCI_0ERROR_DATA_LOW	dev/gt64260reg.h	771;"	d
PCI_0ERROR_MASK	dev/gt64240reg.h	784;"	d
PCI_0ERROR_MASK	dev/gt64260reg.h	775;"	d
PCI_0ERROR_MASK	dev/mv64340reg.h	635;"	d
PCI_0EXPANSION_ROM_BAR_SIZE	dev/gt64240reg.h	586;"	d
PCI_0EXPANSION_ROM_BAR_SIZE	dev/gt64260reg.h	577;"	d
PCI_0EXPANSION_ROM_BAR_SIZE	dev/mv64340reg.h	487;"	d
PCI_0EXPANSION_ROM_BASE_ADDRESS_REMAP	dev/gt64240reg.h	648;"	d
PCI_0EXPANSION_ROM_BASE_ADDRESS_REMAP	dev/gt64260reg.h	639;"	d
PCI_0EXPANSION_ROM_BASE_ADDRESS_REMAP	dev/mv64340reg.h	521;"	d
PCI_0HIGH_INTERRUPT_CAUSE_MASK_REGISTER	dev/gt96132reg.h	280;"	d
PCI_0INTERNAL_REGISTERS_SPACE_SIZE	dev/gt96132reg.h	346;"	d
PCI_0INTERNAL_SRAM_BAR_SIZE	dev/mv64340reg.h	485;"	d
PCI_0INTERNAL_SRAM_BASE_ADDRESS_REMAP	dev/mv64340reg.h	519;"	d
PCI_0INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER	dev/gt64240reg.h	770;"	d
PCI_0INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER	dev/gt64260reg.h	761;"	d
PCI_0INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER	dev/gt96132reg.h	243;"	d
PCI_0INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER	dev/mv64340reg.h	620;"	d
PCI_0INTERRUPT_CAUSE_MASK_REGISTER	dev/gt96132reg.h	279;"	d
PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH	dev/gt64240reg.h	915;"	d
PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH	dev/gt64260reg.h	906;"	d
PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH	dev/mv64340reg.h	739;"	d
PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW	dev/gt64240reg.h	914;"	d
PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW	dev/gt64260reg.h	905;"	d
PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW	dev/mv64340reg.h	738;"	d
PCI_0I_O_ADDRESS_REMAP	dev/gt64240reg.h	195;"	d
PCI_0I_O_ADDRESS_REMAP	dev/gt64260reg.h	186;"	d
PCI_0I_O_ADDRESS_REMAP	dev/gt96132reg.h	107;"	d
PCI_0I_O_ADDRESS_REMAP	dev/mv64340reg.h	195;"	d
PCI_0I_O_BASE_ADDRESS	dev/mv64340reg.h	170;"	d
PCI_0I_O_HIGH_DECODE_ADDRESS	dev/gt64240reg.h	167;"	d
PCI_0I_O_HIGH_DECODE_ADDRESS	dev/gt64260reg.h	158;"	d
PCI_0I_O_HIGH_DECODE_ADDRESS	dev/gt96132reg.h	87;"	d
PCI_0I_O_LOW_DECODE_ADDRESS	dev/gt64240reg.h	166;"	d
PCI_0I_O_LOW_DECODE_ADDRESS	dev/gt64260reg.h	157;"	d
PCI_0I_O_LOW_DECODE_ADDRESS	dev/gt96132reg.h	86;"	d
PCI_0I_O_SIZE	dev/mv64340reg.h	171;"	d
PCI_0MEMORY0_ADDRESS_REMAP	dev/gt64240reg.h	196;"	d
PCI_0MEMORY0_ADDRESS_REMAP	dev/gt64260reg.h	187;"	d
PCI_0MEMORY0_ADDRESS_REMAP	dev/gt96132reg.h	108;"	d
PCI_0MEMORY0_ADDRESS_REMAP	dev/mv64340reg.h	196;"	d
PCI_0MEMORY0_BASE_ADDRESS	dev/mv64340reg.h	172;"	d
PCI_0MEMORY0_HIGH_ADDRESS_REMAP	dev/gt64240reg.h	197;"	d
PCI_0MEMORY0_HIGH_ADDRESS_REMAP	dev/gt64260reg.h	188;"	d
PCI_0MEMORY0_HIGH_ADDRESS_REMAP	dev/mv64340reg.h	197;"	d
PCI_0MEMORY0_HIGH_DECODE_ADDRESS	dev/gt64240reg.h	169;"	d
PCI_0MEMORY0_HIGH_DECODE_ADDRESS	dev/gt64260reg.h	160;"	d
PCI_0MEMORY0_HIGH_DECODE_ADDRESS	dev/gt96132reg.h	89;"	d
PCI_0MEMORY0_LOW_DECODE_ADDRESS	dev/gt64240reg.h	168;"	d
PCI_0MEMORY0_LOW_DECODE_ADDRESS	dev/gt64260reg.h	159;"	d
PCI_0MEMORY0_LOW_DECODE_ADDRESS	dev/gt96132reg.h	88;"	d
PCI_0MEMORY0_SIZE	dev/mv64340reg.h	173;"	d
PCI_0MEMORY1_ADDRESS_REMAP	dev/gt64240reg.h	198;"	d
PCI_0MEMORY1_ADDRESS_REMAP	dev/gt64260reg.h	189;"	d
PCI_0MEMORY1_ADDRESS_REMAP	dev/gt96132reg.h	109;"	d
PCI_0MEMORY1_ADDRESS_REMAP	dev/mv64340reg.h	198;"	d
PCI_0MEMORY1_BASE_ADDRESS	dev/mv64340reg.h	174;"	d
PCI_0MEMORY1_HIGH_ADDRESS_REMAP	dev/gt64240reg.h	199;"	d
PCI_0MEMORY1_HIGH_ADDRESS_REMAP	dev/gt64260reg.h	190;"	d
PCI_0MEMORY1_HIGH_ADDRESS_REMAP	dev/mv64340reg.h	199;"	d
PCI_0MEMORY1_HIGH_DECODE_ADDRESS	dev/gt64240reg.h	171;"	d
PCI_0MEMORY1_HIGH_DECODE_ADDRESS	dev/gt64260reg.h	162;"	d
PCI_0MEMORY1_HIGH_DECODE_ADDRESS	dev/gt96132reg.h	91;"	d
PCI_0MEMORY1_LOW_DECODE_ADDRESS	dev/gt64240reg.h	170;"	d
PCI_0MEMORY1_LOW_DECODE_ADDRESS	dev/gt64260reg.h	161;"	d
PCI_0MEMORY1_LOW_DECODE_ADDRESS	dev/gt96132reg.h	90;"	d
PCI_0MEMORY1_SIZE	dev/mv64340reg.h	175;"	d
PCI_0MEMORY2_ADDRESS_REMAP	dev/gt64240reg.h	200;"	d
PCI_0MEMORY2_ADDRESS_REMAP	dev/gt64260reg.h	191;"	d
PCI_0MEMORY2_ADDRESS_REMAP	dev/mv64340reg.h	200;"	d
PCI_0MEMORY2_BASE_ADDRESS	dev/mv64340reg.h	176;"	d
PCI_0MEMORY2_HIGH_ADDRESS_REMAP	dev/gt64240reg.h	201;"	d
PCI_0MEMORY2_HIGH_ADDRESS_REMAP	dev/gt64260reg.h	192;"	d
PCI_0MEMORY2_HIGH_ADDRESS_REMAP	dev/mv64340reg.h	201;"	d
PCI_0MEMORY2_HIGH_DECODE_ADDRESS	dev/gt64240reg.h	173;"	d
PCI_0MEMORY2_HIGH_DECODE_ADDRESS	dev/gt64260reg.h	164;"	d
PCI_0MEMORY2_LOW_DECODE_ADDRESS	dev/gt64240reg.h	172;"	d
PCI_0MEMORY2_LOW_DECODE_ADDRESS	dev/gt64260reg.h	163;"	d
PCI_0MEMORY2_SIZE	dev/mv64340reg.h	177;"	d
PCI_0MEMORY3_ADDRESS_REMAP	dev/gt64240reg.h	202;"	d
PCI_0MEMORY3_ADDRESS_REMAP	dev/gt64260reg.h	193;"	d
PCI_0MEMORY3_ADDRESS_REMAP	dev/mv64340reg.h	202;"	d
PCI_0MEMORY3_BASE_ADDRESS	dev/mv64340reg.h	178;"	d
PCI_0MEMORY3_HIGH_ADDRESS_REMAP	dev/gt64240reg.h	203;"	d
PCI_0MEMORY3_HIGH_ADDRESS_REMAP	dev/gt64260reg.h	194;"	d
PCI_0MEMORY3_HIGH_ADDRESS_REMAP	dev/mv64340reg.h	203;"	d
PCI_0MEMORY3_HIGH_DECODE_ADDRESS	dev/gt64240reg.h	175;"	d
PCI_0MEMORY3_HIGH_DECODE_ADDRESS	dev/gt64260reg.h	166;"	d
PCI_0MEMORY3_LOW_DECODE_ADDRESS	dev/gt64240reg.h	174;"	d
PCI_0MEMORY3_LOW_DECODE_ADDRESS	dev/gt64260reg.h	165;"	d
PCI_0MEMORY3_SIZE	dev/mv64340reg.h	179;"	d
PCI_0MODE	dev/gt64240reg.h	659;"	d
PCI_0MODE	dev/gt64260reg.h	650;"	d
PCI_0MODE	dev/mv64340reg.h	537;"	d
PCI_0P2P_CONFIGURATION	dev/gt64240reg.h	676;"	d
PCI_0P2P_CONFIGURATION	dev/gt64260reg.h	667;"	d
PCI_0P2P_CONFIGURATION	dev/mv64340reg.h	554;"	d
PCI_0P2P_I_O_BAR_SIZE	dev/gt64240reg.h	558;"	d
PCI_0P2P_I_O_BAR_SIZE	dev/gt64260reg.h	549;"	d
PCI_0P2P_I_O_BAR_SIZE	dev/mv64340reg.h	483;"	d
PCI_0P2P_I_O_BASE_ADDRESS_REMAP	dev/gt64240reg.h	616;"	d
PCI_0P2P_I_O_BASE_ADDRESS_REMAP	dev/gt64260reg.h	607;"	d
PCI_0P2P_I_O_BASE_ADDRESS_REMAP	dev/mv64340reg.h	517;"	d
PCI_0P2P_MEM0_BAR_SIZE	dev/gt64240reg.h	554;"	d
PCI_0P2P_MEM0_BAR_SIZE	dev/gt64260reg.h	545;"	d
PCI_0P2P_MEM0_BAR_SIZE	dev/mv64340reg.h	479;"	d
PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_HIGH	dev/gt64240reg.h	610;"	d
PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_HIGH	dev/gt64260reg.h	601;"	d
PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_HIGH	dev/mv64340reg.h	511;"	d
PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_LOW	dev/gt64240reg.h	608;"	d
PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_LOW	dev/gt64260reg.h	599;"	d
PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_LOW	dev/mv64340reg.h	509;"	d
PCI_0P2P_MEM1_BAR_SIZE	dev/gt64240reg.h	556;"	d
PCI_0P2P_MEM1_BAR_SIZE	dev/gt64260reg.h	547;"	d
PCI_0P2P_MEM1_BAR_SIZE	dev/mv64340reg.h	481;"	d
PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_HIGH	dev/gt64240reg.h	614;"	d
PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_HIGH	dev/gt64260reg.h	605;"	d
PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_HIGH	dev/mv64340reg.h	515;"	d
PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_LOW	dev/gt64240reg.h	612;"	d
PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_LOW	dev/gt64260reg.h	603;"	d
PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_LOW	dev/mv64340reg.h	513;"	d
PCI_0PREFETCH_MAX_BURST_SIZE	dev/gt96132reg.h	233;"	d
PCI_0READ_BUFFER_DISCARD_TIMER	dev/gt64240reg.h	663;"	d
PCI_0READ_BUFFER_DISCARD_TIMER	dev/gt64260reg.h	654;"	d
PCI_0READ_BUFFER_DISCARD_TIMER	dev/mv64340reg.h	541;"	d
PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_HIGH	dev/gt64240reg.h	674;"	d
PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_HIGH	dev/gt64260reg.h	665;"	d
PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_LOW	dev/gt64240reg.h	673;"	d
PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_LOW	dev/gt64260reg.h	664;"	d
PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_LOW	dev/mv64340reg.h	552;"	d
PCI_0SCS_0_BANK_SIZE	dev/gt64240reg.h	536;"	d
PCI_0SCS_0_BANK_SIZE	dev/gt64260reg.h	527;"	d
PCI_0SCS_0_BANK_SIZE	dev/mv64340reg.h	461;"	d
PCI_0SCS_0_BASE_ADDRESS_REMAP	dev/gt64240reg.h	590;"	d
PCI_0SCS_0_BASE_ADDRESS_REMAP	dev/gt64260reg.h	581;"	d
PCI_0SCS_0_BASE_ADDRESS_REMAP	dev/mv64340reg.h	491;"	d
PCI_0SCS_1_0_BANK_SIZE	dev/gt96132reg.h	228;"	d
PCI_0SCS_1_0_BASE_ADDRESS_REMAP	dev/gt96132reg.h	234;"	d
PCI_0SCS_1_BANK_SIZE	dev/gt64240reg.h	538;"	d
PCI_0SCS_1_BANK_SIZE	dev/gt64260reg.h	529;"	d
PCI_0SCS_1_BANK_SIZE	dev/mv64340reg.h	463;"	d
PCI_0SCS_1_BASE_ADDRESS_REMAP	dev/gt64240reg.h	592;"	d
PCI_0SCS_1_BASE_ADDRESS_REMAP	dev/gt64260reg.h	583;"	d
PCI_0SCS_1_BASE_ADDRESS_REMAP	dev/mv64340reg.h	493;"	d
PCI_0SCS_2_BANK_SIZE	dev/gt64240reg.h	540;"	d
PCI_0SCS_2_BANK_SIZE	dev/gt64260reg.h	531;"	d
PCI_0SCS_2_BANK_SIZE	dev/mv64340reg.h	465;"	d
PCI_0SCS_2_BASE_ADDRESS_REMAP	dev/gt64240reg.h	594;"	d
PCI_0SCS_2_BASE_ADDRESS_REMAP	dev/gt64260reg.h	585;"	d
PCI_0SCS_2_BASE_ADDRESS_REMAP	dev/mv64340reg.h	495;"	d
PCI_0SCS_3_2_BANK_SIZE	dev/gt96132reg.h	229;"	d
PCI_0SCS_3_2_BASE_ADDRESS_REMAP	dev/gt96132reg.h	235;"	d
PCI_0SCS_3_BANK_SIZE	dev/gt64240reg.h	542;"	d
PCI_0SCS_3_BANK_SIZE	dev/gt64260reg.h	533;"	d
PCI_0SCS_3_BANK_SIZE	dev/mv64340reg.h	467;"	d
PCI_0SCS_3_BASE_ADDRESS_REMAP	dev/gt64240reg.h	596;"	d
PCI_0SCS_3_BASE_ADDRESS_REMAP	dev/gt64260reg.h	587;"	d
PCI_0SCS_3_BASE_ADDRESS_REMAP	dev/mv64340reg.h	497;"	d
PCI_0SELECT_CAUSE	dev/gt64240reg.h	916;"	d
PCI_0SELECT_CAUSE	dev/gt64260reg.h	907;"	d
PCI_0SELECT_CAUSE	dev/mv64340reg.h	740;"	d
PCI_0SERR0_MASK	dev/gt96132reg.h	281;"	d
PCI_0SERR_MASK	dev/gt64240reg.h	777;"	d
PCI_0SERR_MASK	dev/gt64260reg.h	768;"	d
PCI_0SERR_MASK	dev/mv64340reg.h	629;"	d
PCI_0SNOOP_CONTROL_BASE_0_HIGH	dev/gt64240reg.h	738;"	d
PCI_0SNOOP_CONTROL_BASE_0_HIGH	dev/gt64260reg.h	729;"	d
PCI_0SNOOP_CONTROL_BASE_0_LOW	dev/gt64240reg.h	737;"	d
PCI_0SNOOP_CONTROL_BASE_0_LOW	dev/gt64260reg.h	728;"	d
PCI_0SNOOP_CONTROL_BASE_1_0_HIGH	dev/gt64240reg.h	741;"	d
PCI_0SNOOP_CONTROL_BASE_1_0_HIGH	dev/gt64260reg.h	732;"	d
PCI_0SNOOP_CONTROL_BASE_1_0_LOW	dev/gt64240reg.h	740;"	d
PCI_0SNOOP_CONTROL_BASE_1_0_LOW	dev/gt64260reg.h	731;"	d
PCI_0SNOOP_CONTROL_BASE_2_0_HIGH	dev/gt64240reg.h	744;"	d
PCI_0SNOOP_CONTROL_BASE_2_0_HIGH	dev/gt64260reg.h	735;"	d
PCI_0SNOOP_CONTROL_BASE_2_0_LOW	dev/gt64240reg.h	743;"	d
PCI_0SNOOP_CONTROL_BASE_2_0_LOW	dev/gt64260reg.h	734;"	d
PCI_0SNOOP_CONTROL_BASE_3_0_HIGH	dev/gt64240reg.h	747;"	d
PCI_0SNOOP_CONTROL_BASE_3_0_HIGH	dev/gt64260reg.h	738;"	d
PCI_0SNOOP_CONTROL_BASE_3_0_LOW	dev/gt64240reg.h	746;"	d
PCI_0SNOOP_CONTROL_BASE_3_0_LOW	dev/gt64260reg.h	737;"	d
PCI_0SNOOP_CONTROL_TOP_0	dev/gt64240reg.h	739;"	d
PCI_0SNOOP_CONTROL_TOP_0	dev/gt64260reg.h	730;"	d
PCI_0SNOOP_CONTROL_TOP_1	dev/gt64240reg.h	742;"	d
PCI_0SNOOP_CONTROL_TOP_1	dev/gt64260reg.h	733;"	d
PCI_0SNOOP_CONTROL_TOP_2	dev/gt64240reg.h	745;"	d
PCI_0SNOOP_CONTROL_TOP_2	dev/gt64260reg.h	736;"	d
PCI_0SNOOP_CONTROL_TOP_3	dev/gt64240reg.h	748;"	d
PCI_0SNOOP_CONTROL_TOP_3	dev/gt64260reg.h	739;"	d
PCI_0SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID	dev/gt96132reg.h	349;"	d
PCI_0SWAPPED_CS_3_BOOTCS_BASE_ADDRESS	dev/gt96132reg.h	366;"	d
PCI_0SWAPPED_CS_3_BOOTCS_BASE_ADDRESS_REMAP	dev/gt96132reg.h	240;"	d
PCI_0SWAPPED_SCS_1_0_BASE_ADDRESS	dev/gt96132reg.h	364;"	d
PCI_0SWAPPED_SCS_1_0_BASE_ADDRESS_REMAP	dev/gt96132reg.h	238;"	d
PCI_0SWAPPED_SCS_3_2_BASE_ADDRESS	dev/gt96132reg.h	365;"	d
PCI_0SWAPPED_SCS_3_2_BASE_ADDRESS_REMAP	dev/gt96132reg.h	239;"	d
PCI_0SYNC_BARIER_VIRTUAL_REGISTER	dev/gt64240reg.h	220;"	d
PCI_0SYNC_BARIER_VIRTUAL_REGISTER	dev/gt64260reg.h	211;"	d
PCI_0SYNC_BARIER_VIRTUAL_REGISTER	dev/gt96132reg.h	101;"	d
PCI_0SYNC_BARIER_VIRTUAL_REGISTER	dev/mv64340reg.h	220;"	d
PCI_0SYNC_BARRIER_VIRTUAL_REGISTER	dev/gt64240reg.h	675;"	d
PCI_0SYNC_BARRIER_VIRTUAL_REGISTER	dev/gt64260reg.h	666;"	d
PCI_0SYNC_BARRIER_VIRTUAL_REGISTER	dev/mv64340reg.h	553;"	d
PCI_0TIMEOUT_RETRY	dev/gt64240reg.h	661;"	d
PCI_0TIMEOUT_RETRY	dev/gt64260reg.h	652;"	d
PCI_0TIMEOUT_RETRY	dev/gt96132reg.h	227;"	d
PCI_0TIMEOUT_RETRY	dev/mv64340reg.h	539;"	d
PCI_0_ACCESS_CONTROL_BASE_0_HIGH	dev/mv64360reg.h	471;"	d
PCI_0_ACCESS_CONTROL_BASE_0_LOW	dev/mv64360reg.h	470;"	d
PCI_0_ACCESS_CONTROL_BASE_1_HIGH	dev/mv64360reg.h	474;"	d
PCI_0_ACCESS_CONTROL_BASE_1_LOW	dev/mv64360reg.h	473;"	d
PCI_0_ACCESS_CONTROL_BASE_2_HIGH	dev/mv64360reg.h	477;"	d
PCI_0_ACCESS_CONTROL_BASE_2_LOW	dev/mv64360reg.h	476;"	d
PCI_0_ACCESS_CONTROL_BASE_3_HIGH	dev/mv64360reg.h	480;"	d
PCI_0_ACCESS_CONTROL_BASE_3_LOW	dev/mv64360reg.h	479;"	d
PCI_0_ACCESS_CONTROL_BASE_4_HIGH	dev/mv64360reg.h	483;"	d
PCI_0_ACCESS_CONTROL_BASE_4_LOW	dev/mv64360reg.h	482;"	d
PCI_0_ACCESS_CONTROL_BASE_5_HIGH	dev/mv64360reg.h	486;"	d
PCI_0_ACCESS_CONTROL_BASE_5_LOW	dev/mv64360reg.h	485;"	d
PCI_0_ACCESS_CONTROL_SIZE_0	dev/mv64360reg.h	472;"	d
PCI_0_ACCESS_CONTROL_SIZE_1	dev/mv64360reg.h	475;"	d
PCI_0_ACCESS_CONTROL_SIZE_2	dev/mv64360reg.h	478;"	d
PCI_0_ACCESS_CONTROL_SIZE_3	dev/mv64360reg.h	481;"	d
PCI_0_ACCESS_CONTROL_SIZE_4	dev/mv64360reg.h	484;"	d
PCI_0_ACCESS_CONTROL_SIZE_5	dev/mv64360reg.h	487;"	d
PCI_0_ADDR_DECODE_CONTROL	dev/mv64360reg.h	428;"	d
PCI_0_ARBITER	dev/gt64240reg.h	131;"	d
PCI_0_ARBITER	dev/gt64260reg.h	122;"	d
PCI_0_ARBITER	dev/mv64340reg.h	131;"	d
PCI_0_ARBITER_CONTROL	dev/mv64360reg.h	455;"	d
PCI_0_BAR_EN	dev/gt64240reg.h	129;"	d
PCI_0_BAR_EN	dev/gt64260reg.h	120;"	d
PCI_0_BAR_EN	dev/mv64340reg.h	129;"	d
PCI_0_BASE_ADDR_REG_ENABLE	dev/mv64360reg.h	382;"	d
PCI_0_COMMAND	dev/mv64360reg.h	445;"	d
PCI_0_CONFIG_ADDR	dev/mv64360reg.h	512;"	d
PCI_0_CONFIG_DATA_VIRTUAL_REG	dev/mv64360reg.h	513;"	d
PCI_0_CPU_BAR_SIZE	dev/mv64360reg.h	376;"	d
PCI_0_CPU_BASE_ADDR_REMAP_HIGH	dev/mv64360reg.h	422;"	d
PCI_0_CPU_BASE_ADDR_REMAP_LOW	dev/mv64360reg.h	420;"	d
PCI_0_CROSS_BAR_CONTROL_HIGH	dev/mv64360reg.h	459;"	d
PCI_0_CROSS_BAR_CONTROL_LOW	dev/mv64360reg.h	457;"	d
PCI_0_CROSS_BAR_TIMEOUT	dev/mv64360reg.h	461;"	d
PCI_0_CS_0_BANK_SIZE	dev/mv64360reg.h	352;"	d
PCI_0_CS_0_BASE_ADDR_REMAP	dev/mv64360reg.h	384;"	d
PCI_0_CS_0_BASE_HIGH_ADDR_REMAP	dev/mv64360reg.h	392;"	d
PCI_0_CS_1_BANK_SIZE	dev/mv64360reg.h	354;"	d
PCI_0_CS_1_BASE_ADDR_REMAP	dev/mv64360reg.h	386;"	d
PCI_0_CS_1_BASE_HIGH_ADDR_REMAP	dev/mv64360reg.h	394;"	d
PCI_0_CS_2_BANK_SIZE	dev/mv64360reg.h	356;"	d
PCI_0_CS_2_BASE_ADDR_REMAP	dev/mv64360reg.h	388;"	d
PCI_0_CS_2_BASE_HIGH_ADDR_REMAP	dev/mv64360reg.h	396;"	d
PCI_0_CS_3_BANK_SIZE	dev/mv64360reg.h	358;"	d
PCI_0_CS_3_BASE_ADDR_REMAP	dev/mv64360reg.h	390;"	d
PCI_0_CS_3_BASE_HIGH_ADDR_REMAP	dev/mv64360reg.h	398;"	d
PCI_0_DEVCS_0_BANK_SIZE	dev/mv64360reg.h	360;"	d
PCI_0_DEVCS_0_BASE_ADDR_REMAP	dev/mv64360reg.h	400;"	d
PCI_0_DEVCS_1_BANK_SIZE	dev/mv64360reg.h	362;"	d
PCI_0_DEVCS_1_BASE_ADDR_REMAP	dev/mv64360reg.h	402;"	d
PCI_0_DEVCS_2_BANK_SIZE	dev/mv64360reg.h	364;"	d
PCI_0_DEVCS_2_BASE_ADDR_REMAP	dev/mv64360reg.h	404;"	d
PCI_0_DEVCS_3_BANK_SIZE	dev/mv64360reg.h	366;"	d
PCI_0_DEVCS_3_BASE_ADDR_REMAP	dev/mv64360reg.h	406;"	d
PCI_0_DEVCS_BOOTCS_BASE_ADDR_REMAP	dev/mv64360reg.h	408;"	d
PCI_0_DEVCS_BOOT_BANK_SIZE	dev/mv64360reg.h	368;"	d
PCI_0_DLL_STATUS_AND_COMMAND	dev/mv64360reg.h	441;"	d
PCI_0_ERROR_ADDR_HIGH	dev/mv64360reg.h	527;"	d
PCI_0_ERROR_ADDR_LOW	dev/mv64360reg.h	525;"	d
PCI_0_ERROR_ATTRIBUTE	dev/mv64360reg.h	529;"	d
PCI_0_ERROR_CAUSE	dev/mv64360reg.h	533;"	d
PCI_0_ERROR_COMMAND	dev/mv64360reg.h	531;"	d
PCI_0_ERROR_MASK	dev/mv64360reg.h	535;"	d
PCI_0_EXPANSION_ROM_BAR_SIZE	dev/mv64360reg.h	380;"	d
PCI_0_EXPANSION_ROM_BASE_ADDR_REMAP	dev/mv64360reg.h	426;"	d
PCI_0_HEADERS_RETARGET_BASE	dev/mv64360reg.h	432;"	d
PCI_0_HEADERS_RETARGET_CONTROL	dev/mv64360reg.h	430;"	d
PCI_0_HEADERS_RETARGET_HIGH	dev/mv64360reg.h	434;"	d
PCI_0_INTEGRATED_SRAM_BAR_SIZE	dev/mv64360reg.h	378;"	d
PCI_0_INTEGRATED_SRAM_BASE_ADDR_REMAP	dev/mv64360reg.h	424;"	d
PCI_0_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG	dev/mv64360reg.h	516;"	d
PCI_0_IO_ADDR_REMAP	dev/mv64360reg.h	144;"	d
PCI_0_IO_BASE_ADDR	dev/mv64360reg.h	107;"	d
PCI_0_IO_SIZE	dev/mv64360reg.h	108;"	d
PCI_0_MEMORY0_BASE_ADDR	dev/mv64360reg.h	109;"	d
PCI_0_MEMORY0_HIGH_ADDR_REMAP	dev/mv64360reg.h	146;"	d
PCI_0_MEMORY0_LOW_ADDR_REMAP	dev/mv64360reg.h	145;"	d
PCI_0_MEMORY0_SIZE	dev/mv64360reg.h	110;"	d
PCI_0_MEMORY1_BASE_ADDR	dev/mv64360reg.h	111;"	d
PCI_0_MEMORY1_HIGH_ADDR_REMAP	dev/mv64360reg.h	148;"	d
PCI_0_MEMORY1_LOW_ADDR_REMAP	dev/mv64360reg.h	147;"	d
PCI_0_MEMORY1_SIZE	dev/mv64360reg.h	112;"	d
PCI_0_MEMORY2_BASE_ADDR	dev/mv64360reg.h	113;"	d
PCI_0_MEMORY2_HIGH_ADDR_REMAP	dev/mv64360reg.h	150;"	d
PCI_0_MEMORY2_LOW_ADDR_REMAP	dev/mv64360reg.h	149;"	d
PCI_0_MEMORY2_SIZE	dev/mv64360reg.h	114;"	d
PCI_0_MEMORY3_BASE_ADDR	dev/mv64360reg.h	115;"	d
PCI_0_MEMORY3_HIGH_ADDR_REMAP	dev/mv64360reg.h	152;"	d
PCI_0_MEMORY3_LOW_ADDR_REMAP	dev/mv64360reg.h	151;"	d
PCI_0_MEMORY3_SIZE	dev/mv64360reg.h	116;"	d
PCI_0_MMASK	dev/mv64360reg.h	542;"	d
PCI_0_MODE	dev/mv64360reg.h	447;"	d
PCI_0_MPP_PADS_DRIVE_CONTROL	dev/mv64360reg.h	443;"	d
PCI_0_MSI_TRIGGER_TIMER	dev/mv64360reg.h	453;"	d
PCI_0_P2P_CONFIG	dev/mv64360reg.h	467;"	d
PCI_0_P2P_I_O_BAR_SIZE	dev/mv64360reg.h	374;"	d
PCI_0_P2P_I_O_BASE_ADDR_REMAP	dev/mv64360reg.h	418;"	d
PCI_0_P2P_MEM0_BAR_SIZE	dev/mv64360reg.h	370;"	d
PCI_0_P2P_MEM0_BASE_ADDR_REMAP_HIGH	dev/mv64360reg.h	412;"	d
PCI_0_P2P_MEM0_BASE_ADDR_REMAP_LOW	dev/mv64360reg.h	410;"	d
PCI_0_P2P_MEM1_BAR_SIZE	dev/mv64360reg.h	372;"	d
PCI_0_P2P_MEM1_BASE_ADDR_REMAP_HIGH	dev/mv64360reg.h	416;"	d
PCI_0_P2P_MEM1_BASE_ADDR_REMAP_LOW	dev/mv64360reg.h	414;"	d
PCI_0_READ_BUFFER_DISCARD_TIMER	dev/mv64360reg.h	451;"	d
PCI_0_RETRY	dev/mv64360reg.h	449;"	d
PCI_0_SERR_MASK	dev/mv64360reg.h	523;"	d
PCI_0_SYNC_BARRIER_TRIGGER_REG	dev/mv64360reg.h	463;"	d
PCI_0_SYNC_BARRIER_VIRTUAL_REG	dev/mv64360reg.h	465;"	d
PCI_0_TIME_OUT	dev/gt64240reg.h	127;"	d
PCI_0_TIME_OUT	dev/gt64260reg.h	118;"	d
PCI_0_TIME_OUT	dev/mv64340reg.h	127;"	d
PCI_1ACCESS_CONTROL_BASE_0_HIGH	dev/gt64240reg.h	709;"	d
PCI_1ACCESS_CONTROL_BASE_0_HIGH	dev/gt64260reg.h	700;"	d
PCI_1ACCESS_CONTROL_BASE_0_HIGH	dev/mv64340reg.h	586;"	d
PCI_1ACCESS_CONTROL_BASE_0_LOW	dev/gt64240reg.h	708;"	d
PCI_1ACCESS_CONTROL_BASE_0_LOW	dev/gt64260reg.h	699;"	d
PCI_1ACCESS_CONTROL_BASE_0_LOW	dev/mv64340reg.h	585;"	d
PCI_1ACCESS_CONTROL_BASE_1_HIGH	dev/gt64240reg.h	712;"	d
PCI_1ACCESS_CONTROL_BASE_1_HIGH	dev/gt64260reg.h	703;"	d
PCI_1ACCESS_CONTROL_BASE_1_HIGH	dev/mv64340reg.h	589;"	d
PCI_1ACCESS_CONTROL_BASE_1_LOW	dev/gt64240reg.h	711;"	d
PCI_1ACCESS_CONTROL_BASE_1_LOW	dev/gt64260reg.h	702;"	d
PCI_1ACCESS_CONTROL_BASE_1_LOW	dev/mv64340reg.h	588;"	d
PCI_1ACCESS_CONTROL_BASE_2_HIGH	dev/gt64240reg.h	715;"	d
PCI_1ACCESS_CONTROL_BASE_2_HIGH	dev/gt64260reg.h	706;"	d
PCI_1ACCESS_CONTROL_BASE_2_HIGH	dev/mv64340reg.h	592;"	d
PCI_1ACCESS_CONTROL_BASE_2_LOW	dev/gt64240reg.h	714;"	d
PCI_1ACCESS_CONTROL_BASE_2_LOW	dev/gt64260reg.h	705;"	d
PCI_1ACCESS_CONTROL_BASE_2_LOW	dev/mv64340reg.h	591;"	d
PCI_1ACCESS_CONTROL_BASE_3_HIGH	dev/gt64240reg.h	718;"	d
PCI_1ACCESS_CONTROL_BASE_3_HIGH	dev/gt64260reg.h	709;"	d
PCI_1ACCESS_CONTROL_BASE_3_HIGH	dev/mv64340reg.h	595;"	d
PCI_1ACCESS_CONTROL_BASE_3_LOW	dev/gt64240reg.h	717;"	d
PCI_1ACCESS_CONTROL_BASE_3_LOW	dev/gt64260reg.h	708;"	d
PCI_1ACCESS_CONTROL_BASE_3_LOW	dev/mv64340reg.h	594;"	d
PCI_1ACCESS_CONTROL_BASE_4_HIGH	dev/gt64240reg.h	721;"	d
PCI_1ACCESS_CONTROL_BASE_4_HIGH	dev/gt64260reg.h	712;"	d
PCI_1ACCESS_CONTROL_BASE_4_HIGH	dev/mv64340reg.h	598;"	d
PCI_1ACCESS_CONTROL_BASE_4_LOW	dev/gt64240reg.h	720;"	d
PCI_1ACCESS_CONTROL_BASE_4_LOW	dev/gt64260reg.h	711;"	d
PCI_1ACCESS_CONTROL_BASE_4_LOW	dev/mv64340reg.h	597;"	d
PCI_1ACCESS_CONTROL_BASE_5_HIGH	dev/gt64240reg.h	724;"	d
PCI_1ACCESS_CONTROL_BASE_5_HIGH	dev/gt64260reg.h	715;"	d
PCI_1ACCESS_CONTROL_BASE_5_HIGH	dev/mv64340reg.h	601;"	d
PCI_1ACCESS_CONTROL_BASE_5_LOW	dev/gt64240reg.h	723;"	d
PCI_1ACCESS_CONTROL_BASE_5_LOW	dev/gt64260reg.h	714;"	d
PCI_1ACCESS_CONTROL_BASE_5_LOW	dev/mv64340reg.h	600;"	d
PCI_1ACCESS_CONTROL_BASE_6_HIGH	dev/gt64240reg.h	727;"	d
PCI_1ACCESS_CONTROL_BASE_6_HIGH	dev/gt64260reg.h	718;"	d
PCI_1ACCESS_CONTROL_BASE_6_HIGH	dev/mv64340reg.h	604;"	d
PCI_1ACCESS_CONTROL_BASE_6_LOW	dev/gt64240reg.h	726;"	d
PCI_1ACCESS_CONTROL_BASE_6_LOW	dev/gt64260reg.h	717;"	d
PCI_1ACCESS_CONTROL_BASE_6_LOW	dev/mv64340reg.h	603;"	d
PCI_1ACCESS_CONTROL_BASE_7_HIGH	dev/gt64240reg.h	730;"	d
PCI_1ACCESS_CONTROL_BASE_7_HIGH	dev/gt64260reg.h	721;"	d
PCI_1ACCESS_CONTROL_BASE_7_HIGH	dev/mv64340reg.h	607;"	d
PCI_1ACCESS_CONTROL_BASE_7_LOW	dev/gt64240reg.h	729;"	d
PCI_1ACCESS_CONTROL_BASE_7_LOW	dev/gt64260reg.h	720;"	d
PCI_1ACCESS_CONTROL_BASE_7_LOW	dev/mv64340reg.h	606;"	d
PCI_1ACCESS_CONTROL_TOP_0	dev/gt64240reg.h	710;"	d
PCI_1ACCESS_CONTROL_TOP_0	dev/gt64260reg.h	701;"	d
PCI_1ACCESS_CONTROL_TOP_0	dev/mv64340reg.h	587;"	d
PCI_1ACCESS_CONTROL_TOP_1	dev/gt64240reg.h	713;"	d
PCI_1ACCESS_CONTROL_TOP_1	dev/gt64260reg.h	704;"	d
PCI_1ACCESS_CONTROL_TOP_1	dev/mv64340reg.h	590;"	d
PCI_1ACCESS_CONTROL_TOP_2	dev/gt64240reg.h	716;"	d
PCI_1ACCESS_CONTROL_TOP_2	dev/gt64260reg.h	707;"	d
PCI_1ACCESS_CONTROL_TOP_2	dev/mv64340reg.h	593;"	d
PCI_1ACCESS_CONTROL_TOP_3	dev/gt64240reg.h	719;"	d
PCI_1ACCESS_CONTROL_TOP_3	dev/gt64260reg.h	710;"	d
PCI_1ACCESS_CONTROL_TOP_3	dev/mv64340reg.h	596;"	d
PCI_1ACCESS_CONTROL_TOP_4	dev/gt64240reg.h	722;"	d
PCI_1ACCESS_CONTROL_TOP_4	dev/gt64260reg.h	713;"	d
PCI_1ACCESS_CONTROL_TOP_4	dev/mv64340reg.h	599;"	d
PCI_1ACCESS_CONTROL_TOP_5	dev/gt64240reg.h	725;"	d
PCI_1ACCESS_CONTROL_TOP_5	dev/gt64260reg.h	716;"	d
PCI_1ACCESS_CONTROL_TOP_5	dev/mv64340reg.h	602;"	d
PCI_1ACCESS_CONTROL_TOP_6	dev/gt64240reg.h	728;"	d
PCI_1ACCESS_CONTROL_TOP_6	dev/gt64260reg.h	719;"	d
PCI_1ACCESS_CONTROL_TOP_6	dev/mv64340reg.h	605;"	d
PCI_1ACCESS_CONTROL_TOP_7	dev/gt64240reg.h	731;"	d
PCI_1ACCESS_CONTROL_TOP_7	dev/gt64260reg.h	722;"	d
PCI_1ACCESS_CONTROL_TOP_7	dev/mv64340reg.h	608;"	d
PCI_1ADDRESS_DECODE_CONTROL	dev/gt64240reg.h	651;"	d
PCI_1ADDRESS_DECODE_CONTROL	dev/gt64260reg.h	642;"	d
PCI_1ADDRESS_DECODE_CONTROL	dev/mv64340reg.h	524;"	d
PCI_1ARBITER_CONTROL	dev/gt64240reg.h	668;"	d
PCI_1ARBITER_CONTROL	dev/gt64260reg.h	659;"	d
PCI_1ARBITER_CONTROL	dev/gt96132reg.h	358;"	d
PCI_1ARBITER_CONTROL	dev/mv64340reg.h	546;"	d
PCI_1BASE_ADDRESS_REGISTERS_ENABLE	dev/gt64240reg.h	589;"	d
PCI_1BASE_ADDRESS_REGISTERS_ENABLE	dev/gt64260reg.h	580;"	d
PCI_1BASE_ADDRESS_REGISTERS_ENABLE	dev/gt96132reg.h	250;"	d
PCI_1BASE_ADDRESS_REGISTERS_ENABLE	dev/mv64340reg.h	490;"	d
PCI_1COMMAND	dev/gt64240reg.h	658;"	d
PCI_1COMMAND	dev/gt64260reg.h	649;"	d
PCI_1COMMAND	dev/gt96132reg.h	244;"	d
PCI_1COMMAND	dev/mv64340reg.h	536;"	d
PCI_1CONFIGURATION_ADDRESS	dev/gt64240reg.h	768;"	d
PCI_1CONFIGURATION_ADDRESS	dev/gt64260reg.h	759;"	d
PCI_1CONFIGURATION_ADDRESS	dev/gt96132reg.h	259;"	d
PCI_1CONFIGURATION_ADDRESS	dev/mv64340reg.h	618;"	d
PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER	dev/gt64240reg.h	769;"	d
PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER	dev/gt64260reg.h	760;"	d
PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER	dev/gt96132reg.h	260;"	d
PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER	dev/mv64340reg.h	619;"	d
PCI_1CPU_BAR_SIZE	dev/gt64240reg.h	561;"	d
PCI_1CPU_BAR_SIZE	dev/gt64260reg.h	552;"	d
PCI_1CPU_BASE_ADDRESS_REMAP	dev/gt64240reg.h	619;"	d
PCI_1CPU_BASE_ADDRESS_REMAP	dev/gt64260reg.h	610;"	d
PCI_1CROSS_BAR_CONTROL_HIGH	dev/gt64240reg.h	702;"	d
PCI_1CROSS_BAR_CONTROL_HIGH	dev/gt64260reg.h	693;"	d
PCI_1CROSS_BAR_CONTROL_HIGH	dev/mv64340reg.h	580;"	d
PCI_1CROSS_BAR_CONTROL_LOW	dev/gt64240reg.h	701;"	d
PCI_1CROSS_BAR_CONTROL_LOW	dev/gt64260reg.h	692;"	d
PCI_1CROSS_BAR_CONTROL_LOW	dev/mv64340reg.h	579;"	d
PCI_1CROSS_BAR_TIMEOUT	dev/gt64240reg.h	703;"	d
PCI_1CROSS_BAR_TIMEOUT	dev/gt64260reg.h	694;"	d
PCI_1CROSS_BAR_TIMEOUT	dev/mv64340reg.h	581;"	d
PCI_1CS_0_BANK_SIZE	dev/gt64240reg.h	545;"	d
PCI_1CS_0_BANK_SIZE	dev/gt64260reg.h	536;"	d
PCI_1CS_0_BANK_SIZE	dev/mv64340reg.h	470;"	d
PCI_1CS_0_BASE_ADDRESS_REMAP	dev/gt64240reg.h	599;"	d
PCI_1CS_0_BASE_ADDRESS_REMAP	dev/gt64260reg.h	590;"	d
PCI_1CS_0_BASE_ADDRESS_REMAP	dev/mv64340reg.h	500;"	d
PCI_1CS_1_BANK_SIZE	dev/gt64240reg.h	547;"	d
PCI_1CS_1_BANK_SIZE	dev/gt64260reg.h	538;"	d
PCI_1CS_1_BANK_SIZE	dev/mv64340reg.h	472;"	d
PCI_1CS_1_BASE_ADDRESS_REMAP	dev/gt64240reg.h	601;"	d
PCI_1CS_1_BASE_ADDRESS_REMAP	dev/gt64260reg.h	592;"	d
PCI_1CS_1_BASE_ADDRESS_REMAP	dev/mv64340reg.h	502;"	d
PCI_1CS_2_0_BANK_SIZE	dev/gt96132reg.h	248;"	d
PCI_1CS_2_0_BASE_ADDRESS_REMAP	dev/gt96132reg.h	254;"	d
PCI_1CS_2_BANK_SIZE	dev/gt64240reg.h	549;"	d
PCI_1CS_2_BANK_SIZE	dev/gt64260reg.h	540;"	d
PCI_1CS_2_BANK_SIZE	dev/mv64340reg.h	474;"	d
PCI_1CS_2_BASE_ADDRESS_REMAP	dev/gt64240reg.h	603;"	d
PCI_1CS_2_BASE_ADDRESS_REMAP	dev/gt64260reg.h	594;"	d
PCI_1CS_2_BASE_ADDRESS_REMAP	dev/mv64340reg.h	504;"	d
PCI_1CS_3_BANK_SIZE	dev/gt64240reg.h	551;"	d
PCI_1CS_3_BANK_SIZE	dev/gt64260reg.h	542;"	d
PCI_1CS_3_BANK_SIZE	dev/mv64340reg.h	476;"	d
PCI_1CS_3_BASE_ADDRESS_REMAP	dev/gt64240reg.h	605;"	d
PCI_1CS_3_BASE_ADDRESS_REMAP	dev/gt64260reg.h	596;"	d
PCI_1CS_3_BASE_ADDRESS_REMAP	dev/mv64340reg.h	506;"	d
PCI_1CS_3_BOOTCS_ADDRESS_REMAP	dev/gt96132reg.h	255;"	d
PCI_1CS_3_BOOTCS_BANK_SIZE	dev/gt96132reg.h	249;"	d
PCI_1CS_BOOTCS_BASE_ADDRESS_REMAP	dev/gt64240reg.h	607;"	d
PCI_1CS_BOOTCS_BASE_ADDRESS_REMAP	dev/gt64260reg.h	598;"	d
PCI_1CS_BOOTCS_BASE_ADDRESS_REMAP	dev/mv64340reg.h	508;"	d
PCI_1CS_BOOT_BANK_SIZE	dev/gt64240reg.h	553;"	d
PCI_1CS_BOOT_BANK_SIZE	dev/gt64260reg.h	544;"	d
PCI_1CS_BOOT_BANK_SIZE	dev/mv64340reg.h	478;"	d
PCI_1DAC_BOOTCS_BANK_SIZE	dev/gt64240reg.h	579;"	d
PCI_1DAC_BOOTCS_BANK_SIZE	dev/gt64260reg.h	570;"	d
PCI_1DAC_BOOTCS_BASE_ADDRESS_REMAP	dev/gt64240reg.h	637;"	d
PCI_1DAC_BOOTCS_BASE_ADDRESS_REMAP	dev/gt64260reg.h	628;"	d
PCI_1DAC_CPU_BAR_SIZE	dev/gt64240reg.h	585;"	d
PCI_1DAC_CPU_BAR_SIZE	dev/gt64260reg.h	576;"	d
PCI_1DAC_CPU_BASE_ADDRESS_REMAP	dev/gt64240reg.h	647;"	d
PCI_1DAC_CPU_BASE_ADDRESS_REMAP	dev/gt64260reg.h	638;"	d
PCI_1DAC_CS_0_BANK_SIZE	dev/gt64240reg.h	571;"	d
PCI_1DAC_CS_0_BANK_SIZE	dev/gt64260reg.h	562;"	d
PCI_1DAC_CS_0_BASE_ADDRESS_REMAP	dev/gt64240reg.h	629;"	d
PCI_1DAC_CS_0_BASE_ADDRESS_REMAP	dev/gt64260reg.h	620;"	d
PCI_1DAC_CS_1_BANK_SIZE	dev/gt64240reg.h	573;"	d
PCI_1DAC_CS_1_BANK_SIZE	dev/gt64260reg.h	564;"	d
PCI_1DAC_CS_1_BASE_ADDRESS_REMAP	dev/gt64240reg.h	631;"	d
PCI_1DAC_CS_1_BASE_ADDRESS_REMAP	dev/gt64260reg.h	622;"	d
PCI_1DAC_CS_2_BANK_SIZE	dev/gt64240reg.h	575;"	d
PCI_1DAC_CS_2_BANK_SIZE	dev/gt64260reg.h	566;"	d
PCI_1DAC_CS_2_BASE_ADDRESS_REMAP	dev/gt64240reg.h	633;"	d
PCI_1DAC_CS_2_BASE_ADDRESS_REMAP	dev/gt64260reg.h	624;"	d
PCI_1DAC_CS_3_BANK_SIZE	dev/gt64240reg.h	577;"	d
PCI_1DAC_CS_3_BANK_SIZE	dev/gt64260reg.h	568;"	d
PCI_1DAC_CS_3_BASE_ADDRESS_REMAP	dev/gt64240reg.h	635;"	d
PCI_1DAC_CS_3_BASE_ADDRESS_REMAP	dev/gt64260reg.h	626;"	d
PCI_1DAC_P2P_MEM0_BAR_SIZE	dev/gt64240reg.h	581;"	d
PCI_1DAC_P2P_MEM0_BAR_SIZE	dev/gt64260reg.h	572;"	d
PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH	dev/gt64240reg.h	641;"	d
PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH	dev/gt64260reg.h	632;"	d
PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW	dev/gt64240reg.h	639;"	d
PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW	dev/gt64260reg.h	630;"	d
PCI_1DAC_P2P_MEM1_BAR_SIZE	dev/gt64240reg.h	583;"	d
PCI_1DAC_P2P_MEM1_BAR_SIZE	dev/gt64260reg.h	574;"	d
PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH	dev/gt64240reg.h	645;"	d
PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH	dev/gt64260reg.h	636;"	d
PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW	dev/gt64240reg.h	643;"	d
PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW	dev/gt64260reg.h	634;"	d
PCI_1DAC_SCS_0_BANK_SIZE	dev/gt64240reg.h	563;"	d
PCI_1DAC_SCS_0_BANK_SIZE	dev/gt64260reg.h	554;"	d
PCI_1DAC_SCS_0_BASE_ADDRESS_REMAP	dev/gt64240reg.h	621;"	d
PCI_1DAC_SCS_0_BASE_ADDRESS_REMAP	dev/gt64260reg.h	612;"	d
PCI_1DAC_SCS_1_BANK_SIZE	dev/gt64240reg.h	565;"	d
PCI_1DAC_SCS_1_BANK_SIZE	dev/gt64260reg.h	556;"	d
PCI_1DAC_SCS_1_BASE_ADDRESS_REMAP	dev/gt64240reg.h	623;"	d
PCI_1DAC_SCS_1_BASE_ADDRESS_REMAP	dev/gt64260reg.h	614;"	d
PCI_1DAC_SCS_2_BANK_SIZE	dev/gt64240reg.h	567;"	d
PCI_1DAC_SCS_2_BANK_SIZE	dev/gt64260reg.h	558;"	d
PCI_1DAC_SCS_2_BASE_ADDRESS_REMAP	dev/gt64240reg.h	625;"	d
PCI_1DAC_SCS_2_BASE_ADDRESS_REMAP	dev/gt64260reg.h	616;"	d
PCI_1DAC_SCS_3_BANK_SIZE	dev/gt64240reg.h	569;"	d
PCI_1DAC_SCS_3_BANK_SIZE	dev/gt64260reg.h	560;"	d
PCI_1DAC_SCS_3_BASE_ADDRESS_REMAP	dev/gt64240reg.h	627;"	d
PCI_1DAC_SCS_3_BASE_ADDRESS_REMAP	dev/gt64260reg.h	618;"	d
PCI_1ERROR_ADDRESS_HIGH	dev/gt64240reg.h	787;"	d
PCI_1ERROR_ADDRESS_HIGH	dev/gt64260reg.h	778;"	d
PCI_1ERROR_ADDRESS_HIGH	dev/mv64340reg.h	639;"	d
PCI_1ERROR_ADDRESS_LOW	dev/gt64240reg.h	786;"	d
PCI_1ERROR_ADDRESS_LOW	dev/gt64260reg.h	777;"	d
PCI_1ERROR_ADDRESS_LOW	dev/mv64340reg.h	638;"	d
PCI_1ERROR_ATTRIBUTE	dev/mv64340reg.h	640;"	d
PCI_1ERROR_CAUSE	dev/gt64240reg.h	791;"	d
PCI_1ERROR_CAUSE	dev/gt64260reg.h	782;"	d
PCI_1ERROR_CAUSE	dev/mv64340reg.h	642;"	d
PCI_1ERROR_COMMAND	dev/gt64240reg.h	790;"	d
PCI_1ERROR_COMMAND	dev/gt64260reg.h	781;"	d
PCI_1ERROR_COMMAND	dev/mv64340reg.h	641;"	d
PCI_1ERROR_DATA_HIGH	dev/gt64240reg.h	789;"	d
PCI_1ERROR_DATA_HIGH	dev/gt64260reg.h	780;"	d
PCI_1ERROR_DATA_LOW	dev/gt64240reg.h	788;"	d
PCI_1ERROR_DATA_LOW	dev/gt64260reg.h	779;"	d
PCI_1ERROR_MASK	dev/gt64240reg.h	792;"	d
PCI_1ERROR_MASK	dev/gt64260reg.h	783;"	d
PCI_1ERROR_MASK	dev/mv64340reg.h	643;"	d
PCI_1EXPANSION_ROM_BAR_SIZE	dev/gt64240reg.h	587;"	d
PCI_1EXPANSION_ROM_BAR_SIZE	dev/gt64260reg.h	578;"	d
PCI_1EXPANSION_ROM_BAR_SIZE	dev/mv64340reg.h	488;"	d
PCI_1EXPANSION_ROM_BASE_ADDRESS_REMAP	dev/gt64240reg.h	649;"	d
PCI_1EXPANSION_ROM_BASE_ADDRESS_REMAP	dev/gt64260reg.h	640;"	d
PCI_1EXPANSION_ROM_BASE_ADDRESS_REMAP	dev/mv64340reg.h	522;"	d
PCI_1INTERNAL_REGISTERS_SPACE_SIZE	dev/gt96132reg.h	347;"	d
PCI_1INTERNAL_SRAM_BAR_SIZE	dev/mv64340reg.h	486;"	d
PCI_1INTERNAL_SRAM_BASE_ADDRESS_REMAP	dev/mv64340reg.h	520;"	d
PCI_1INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER	dev/gt64240reg.h	771;"	d
PCI_1INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER	dev/gt64260reg.h	762;"	d
PCI_1INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER	dev/gt96132reg.h	261;"	d
PCI_1INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER	dev/mv64340reg.h	621;"	d
PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH	dev/gt64240reg.h	918;"	d
PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH	dev/gt64260reg.h	909;"	d
PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH	dev/mv64340reg.h	742;"	d
PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW	dev/gt64240reg.h	917;"	d
PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW	dev/gt64260reg.h	908;"	d
PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW	dev/mv64340reg.h	741;"	d
PCI_1I_O_ADDRESS_REMAP	dev/gt64240reg.h	205;"	d
PCI_1I_O_ADDRESS_REMAP	dev/gt64260reg.h	196;"	d
PCI_1I_O_ADDRESS_REMAP	dev/gt96132reg.h	110;"	d
PCI_1I_O_ADDRESS_REMAP	dev/mv64340reg.h	205;"	d
PCI_1I_O_BASE_ADDRESS	dev/mv64340reg.h	181;"	d
PCI_1I_O_HIGH_DECODE_ADDRESS	dev/gt64240reg.h	178;"	d
PCI_1I_O_HIGH_DECODE_ADDRESS	dev/gt64260reg.h	169;"	d
PCI_1I_O_HIGH_DECODE_ADDRESS	dev/gt96132reg.h	93;"	d
PCI_1I_O_LOW_DECODE_ADDRESS	dev/gt64240reg.h	177;"	d
PCI_1I_O_LOW_DECODE_ADDRESS	dev/gt64260reg.h	168;"	d
PCI_1I_O_LOW_DECODE_ADDRESS	dev/gt96132reg.h	92;"	d
PCI_1I_O_SIZE	dev/mv64340reg.h	182;"	d
PCI_1MEMORY0_ADDRESS_REMAP	dev/gt64240reg.h	206;"	d
PCI_1MEMORY0_ADDRESS_REMAP	dev/gt64260reg.h	197;"	d
PCI_1MEMORY0_ADDRESS_REMAP	dev/gt96132reg.h	111;"	d
PCI_1MEMORY0_ADDRESS_REMAP	dev/mv64340reg.h	206;"	d
PCI_1MEMORY0_BASE_ADDRESS	dev/mv64340reg.h	183;"	d
PCI_1MEMORY0_HIGH_ADDRESS_REMAP	dev/gt64240reg.h	207;"	d
PCI_1MEMORY0_HIGH_ADDRESS_REMAP	dev/gt64260reg.h	198;"	d
PCI_1MEMORY0_HIGH_ADDRESS_REMAP	dev/mv64340reg.h	207;"	d
PCI_1MEMORY0_HIGH_DECODE_ADDRESS	dev/gt64240reg.h	180;"	d
PCI_1MEMORY0_HIGH_DECODE_ADDRESS	dev/gt64260reg.h	171;"	d
PCI_1MEMORY0_HIGH_DECODE_ADDRESS	dev/gt96132reg.h	95;"	d
PCI_1MEMORY0_LOW_DECODE_ADDRESS	dev/gt64240reg.h	179;"	d
PCI_1MEMORY0_LOW_DECODE_ADDRESS	dev/gt64260reg.h	170;"	d
PCI_1MEMORY0_LOW_DECODE_ADDRESS	dev/gt96132reg.h	94;"	d
PCI_1MEMORY0_SIZE	dev/mv64340reg.h	184;"	d
PCI_1MEMORY1_ADDRESS_REMAP	dev/gt64240reg.h	208;"	d
PCI_1MEMORY1_ADDRESS_REMAP	dev/gt64260reg.h	199;"	d
PCI_1MEMORY1_ADDRESS_REMAP	dev/gt96132reg.h	112;"	d
PCI_1MEMORY1_ADDRESS_REMAP	dev/mv64340reg.h	208;"	d
PCI_1MEMORY1_BASE_ADDRESS	dev/mv64340reg.h	185;"	d
PCI_1MEMORY1_HIGH_ADDRESS_REMAP	dev/gt64240reg.h	209;"	d
PCI_1MEMORY1_HIGH_ADDRESS_REMAP	dev/gt64260reg.h	200;"	d
PCI_1MEMORY1_HIGH_ADDRESS_REMAP	dev/mv64340reg.h	209;"	d
PCI_1MEMORY1_HIGH_DECODE_ADDRESS	dev/gt64240reg.h	182;"	d
PCI_1MEMORY1_HIGH_DECODE_ADDRESS	dev/gt64260reg.h	173;"	d
PCI_1MEMORY1_HIGH_DECODE_ADDRESS	dev/gt96132reg.h	97;"	d
PCI_1MEMORY1_LOW_DECODE_ADDRESS	dev/gt64240reg.h	181;"	d
PCI_1MEMORY1_LOW_DECODE_ADDRESS	dev/gt64260reg.h	172;"	d
PCI_1MEMORY1_LOW_DECODE_ADDRESS	dev/gt96132reg.h	96;"	d
PCI_1MEMORY1_SIZE	dev/mv64340reg.h	186;"	d
PCI_1MEMORY2_ADDRESS_REMAP	dev/gt64240reg.h	210;"	d
PCI_1MEMORY2_ADDRESS_REMAP	dev/gt64260reg.h	201;"	d
PCI_1MEMORY2_ADDRESS_REMAP	dev/mv64340reg.h	210;"	d
PCI_1MEMORY2_BASE_ADDRESS	dev/mv64340reg.h	187;"	d
PCI_1MEMORY2_HIGH_ADDRESS_REMAP	dev/gt64240reg.h	211;"	d
PCI_1MEMORY2_HIGH_ADDRESS_REMAP	dev/gt64260reg.h	202;"	d
PCI_1MEMORY2_HIGH_ADDRESS_REMAP	dev/mv64340reg.h	211;"	d
PCI_1MEMORY2_HIGH_DECODE_ADDRESS	dev/gt64240reg.h	184;"	d
PCI_1MEMORY2_HIGH_DECODE_ADDRESS	dev/gt64260reg.h	175;"	d
PCI_1MEMORY2_LOW_DECODE_ADDRESS	dev/gt64240reg.h	183;"	d
PCI_1MEMORY2_LOW_DECODE_ADDRESS	dev/gt64260reg.h	174;"	d
PCI_1MEMORY2_SIZE	dev/mv64340reg.h	188;"	d
PCI_1MEMORY3_ADDRESS_REMAP	dev/gt64240reg.h	212;"	d
PCI_1MEMORY3_ADDRESS_REMAP	dev/gt64260reg.h	203;"	d
PCI_1MEMORY3_ADDRESS_REMAP	dev/mv64340reg.h	212;"	d
PCI_1MEMORY3_BASE_ADDRESS	dev/mv64340reg.h	189;"	d
PCI_1MEMORY3_HIGH_ADDRESS_REMAP	dev/gt64240reg.h	213;"	d
PCI_1MEMORY3_HIGH_ADDRESS_REMAP	dev/gt64260reg.h	204;"	d
PCI_1MEMORY3_HIGH_ADDRESS_REMAP	dev/mv64340reg.h	213;"	d
PCI_1MEMORY3_HIGH_DECODE_ADDRESS	dev/gt64240reg.h	186;"	d
PCI_1MEMORY3_HIGH_DECODE_ADDRESS	dev/gt64260reg.h	177;"	d
PCI_1MEMORY3_LOW_DECODE_ADDRESS	dev/gt64240reg.h	185;"	d
PCI_1MEMORY3_LOW_DECODE_ADDRESS	dev/gt64260reg.h	176;"	d
PCI_1MEMORY3_SIZE	dev/mv64340reg.h	190;"	d
PCI_1MODE	dev/gt64240reg.h	660;"	d
PCI_1MODE	dev/gt64260reg.h	651;"	d
PCI_1MODE	dev/mv64340reg.h	538;"	d
PCI_1P2P_CONFIGURATION	dev/gt64240reg.h	707;"	d
PCI_1P2P_CONFIGURATION	dev/gt64260reg.h	698;"	d
PCI_1P2P_CONFIGURATION	dev/mv64340reg.h	584;"	d
PCI_1P2P_I_O_BAR_SIZE	dev/gt64240reg.h	559;"	d
PCI_1P2P_I_O_BAR_SIZE	dev/gt64260reg.h	550;"	d
PCI_1P2P_I_O_BAR_SIZE	dev/mv64340reg.h	484;"	d
PCI_1P2P_I_O_BASE_ADDRESS_REMAP	dev/gt64240reg.h	617;"	d
PCI_1P2P_I_O_BASE_ADDRESS_REMAP	dev/gt64260reg.h	608;"	d
PCI_1P2P_I_O_BASE_ADDRESS_REMAP	dev/mv64340reg.h	518;"	d
PCI_1P2P_MEM0_BAR_SIZE	dev/gt64240reg.h	555;"	d
PCI_1P2P_MEM0_BAR_SIZE	dev/gt64260reg.h	546;"	d
PCI_1P2P_MEM0_BAR_SIZE	dev/mv64340reg.h	480;"	d
PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_HIGH	dev/gt64240reg.h	611;"	d
PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_HIGH	dev/gt64260reg.h	602;"	d
PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_HIGH	dev/mv64340reg.h	512;"	d
PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_LOW	dev/gt64240reg.h	609;"	d
PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_LOW	dev/gt64260reg.h	600;"	d
PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_LOW	dev/mv64340reg.h	510;"	d
PCI_1P2P_MEM1_BAR_SIZE	dev/gt64240reg.h	557;"	d
PCI_1P2P_MEM1_BAR_SIZE	dev/gt64260reg.h	548;"	d
PCI_1P2P_MEM1_BAR_SIZE	dev/mv64340reg.h	482;"	d
PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_HIGH	dev/gt64240reg.h	615;"	d
PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_HIGH	dev/gt64260reg.h	606;"	d
PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_HIGH	dev/mv64340reg.h	516;"	d
PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_LOW	dev/gt64240reg.h	613;"	d
PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_LOW	dev/gt64260reg.h	604;"	d
PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_LOW	dev/mv64340reg.h	514;"	d
PCI_1PREFETCH_MAX_BURST_SIZE	dev/gt96132reg.h	251;"	d
PCI_1READ_BUFFER_DISCARD_TIMER	dev/gt64240reg.h	664;"	d
PCI_1READ_BUFFER_DISCARD_TIMER	dev/gt64260reg.h	655;"	d
PCI_1READ_BUFFER_DISCARD_TIMER	dev/mv64340reg.h	542;"	d
PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_HIGH	dev/gt64240reg.h	705;"	d
PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_HIGH	dev/gt64260reg.h	696;"	d
PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_LOW	dev/gt64240reg.h	704;"	d
PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_LOW	dev/gt64260reg.h	695;"	d
PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_LOW	dev/mv64340reg.h	582;"	d
PCI_1SCS_0_BANK_SIZE	dev/gt64240reg.h	537;"	d
PCI_1SCS_0_BANK_SIZE	dev/gt64260reg.h	528;"	d
PCI_1SCS_0_BANK_SIZE	dev/mv64340reg.h	462;"	d
PCI_1SCS_0_BASE_ADDRESS_REMAP	dev/gt64240reg.h	591;"	d
PCI_1SCS_0_BASE_ADDRESS_REMAP	dev/gt64260reg.h	582;"	d
PCI_1SCS_0_BASE_ADDRESS_REMAP	dev/mv64340reg.h	492;"	d
PCI_1SCS_1_0_BANK_SIZE	dev/gt96132reg.h	246;"	d
PCI_1SCS_1_0_BASE_ADDRESS	dev/gt96132reg.h	339;"	d
PCI_1SCS_1_0_BASE_ADDRESS_REMAP	dev/gt96132reg.h	252;"	d
PCI_1SCS_1_BANK_SIZE	dev/gt64240reg.h	539;"	d
PCI_1SCS_1_BANK_SIZE	dev/gt64260reg.h	530;"	d
PCI_1SCS_1_BANK_SIZE	dev/mv64340reg.h	464;"	d
PCI_1SCS_1_BASE_ADDRESS_REMAP	dev/gt64240reg.h	593;"	d
PCI_1SCS_1_BASE_ADDRESS_REMAP	dev/gt64260reg.h	584;"	d
PCI_1SCS_1_BASE_ADDRESS_REMAP	dev/mv64340reg.h	494;"	d
PCI_1SCS_2_BANK_SIZE	dev/gt64240reg.h	541;"	d
PCI_1SCS_2_BANK_SIZE	dev/gt64260reg.h	532;"	d
PCI_1SCS_2_BANK_SIZE	dev/mv64340reg.h	466;"	d
PCI_1SCS_2_BASE_ADDRESS_REMAP	dev/gt64240reg.h	595;"	d
PCI_1SCS_2_BASE_ADDRESS_REMAP	dev/gt64260reg.h	586;"	d
PCI_1SCS_2_BASE_ADDRESS_REMAP	dev/mv64340reg.h	496;"	d
PCI_1SCS_3_2_BANK_SIZE	dev/gt96132reg.h	247;"	d
PCI_1SCS_3_2_BASE_ADDRESS	dev/gt96132reg.h	340;"	d
PCI_1SCS_3_2_BASE_ADDRESS_REMAP	dev/gt96132reg.h	253;"	d
PCI_1SCS_3_BANK_SIZE	dev/gt64240reg.h	543;"	d
PCI_1SCS_3_BANK_SIZE	dev/gt64260reg.h	534;"	d
PCI_1SCS_3_BANK_SIZE	dev/mv64340reg.h	468;"	d
PCI_1SCS_3_BASE_ADDRESS_REMAP	dev/gt64240reg.h	597;"	d
PCI_1SCS_3_BASE_ADDRESS_REMAP	dev/gt64260reg.h	588;"	d
PCI_1SCS_3_BASE_ADDRESS_REMAP	dev/mv64340reg.h	498;"	d
PCI_1SELECT_CAUSE	dev/gt64240reg.h	919;"	d
PCI_1SELECT_CAUSE	dev/gt64260reg.h	910;"	d
PCI_1SELECT_CAUSE	dev/mv64340reg.h	743;"	d
PCI_1SERR0_MASK	dev/gt96132reg.h	282;"	d
PCI_1SERR_MASK	dev/gt64240reg.h	785;"	d
PCI_1SERR_MASK	dev/gt64260reg.h	776;"	d
PCI_1SERR_MASK	dev/mv64340reg.h	637;"	d
PCI_1SNOOP_CONTROL_BASE_0_HIGH	dev/gt64240reg.h	750;"	d
PCI_1SNOOP_CONTROL_BASE_0_HIGH	dev/gt64260reg.h	741;"	d
PCI_1SNOOP_CONTROL_BASE_0_LOW	dev/gt64240reg.h	749;"	d
PCI_1SNOOP_CONTROL_BASE_0_LOW	dev/gt64260reg.h	740;"	d
PCI_1SNOOP_CONTROL_BASE_1_0_HIGH	dev/gt64240reg.h	753;"	d
PCI_1SNOOP_CONTROL_BASE_1_0_HIGH	dev/gt64260reg.h	744;"	d
PCI_1SNOOP_CONTROL_BASE_1_0_LOW	dev/gt64240reg.h	752;"	d
PCI_1SNOOP_CONTROL_BASE_1_0_LOW	dev/gt64260reg.h	743;"	d
PCI_1SNOOP_CONTROL_BASE_2_0_HIGH	dev/gt64240reg.h	756;"	d
PCI_1SNOOP_CONTROL_BASE_2_0_HIGH	dev/gt64260reg.h	747;"	d
PCI_1SNOOP_CONTROL_BASE_2_0_LOW	dev/gt64240reg.h	755;"	d
PCI_1SNOOP_CONTROL_BASE_2_0_LOW	dev/gt64260reg.h	746;"	d
PCI_1SNOOP_CONTROL_BASE_3_0_HIGH	dev/gt64240reg.h	759;"	d
PCI_1SNOOP_CONTROL_BASE_3_0_HIGH	dev/gt64260reg.h	750;"	d
PCI_1SNOOP_CONTROL_BASE_3_0_LOW	dev/gt64240reg.h	758;"	d
PCI_1SNOOP_CONTROL_BASE_3_0_LOW	dev/gt64260reg.h	749;"	d
PCI_1SNOOP_CONTROL_TOP_0	dev/gt64240reg.h	751;"	d
PCI_1SNOOP_CONTROL_TOP_0	dev/gt64260reg.h	742;"	d
PCI_1SNOOP_CONTROL_TOP_1	dev/gt64240reg.h	754;"	d
PCI_1SNOOP_CONTROL_TOP_1	dev/gt64260reg.h	745;"	d
PCI_1SNOOP_CONTROL_TOP_2	dev/gt64240reg.h	757;"	d
PCI_1SNOOP_CONTROL_TOP_2	dev/gt64260reg.h	748;"	d
PCI_1SNOOP_CONTROL_TOP_3	dev/gt64240reg.h	760;"	d
PCI_1SNOOP_CONTROL_TOP_3	dev/gt64260reg.h	751;"	d
PCI_1SWAPPED_CS_3_BOOTCS_BASE_ADDRESS	dev/gt96132reg.h	369;"	d
PCI_1SWAPPED_CS_3_BOOTCS_BASE_ADDRESS_REMAP	dev/gt96132reg.h	258;"	d
PCI_1SWAPPED_SCS_1_0_BASE_ADDRESS	dev/gt96132reg.h	367;"	d
PCI_1SWAPPED_SCS_1_0_BASE_ADDRESS_REMAP	dev/gt96132reg.h	256;"	d
PCI_1SWAPPED_SCS_3_2_BASE_ADDRESS	dev/gt96132reg.h	368;"	d
PCI_1SWAPPED_SCS_3_2_BASE_ADDRESS_REMAP	dev/gt96132reg.h	257;"	d
PCI_1SYNC_BARIER_VIRTUAL_REGISTER	dev/gt64240reg.h	221;"	d
PCI_1SYNC_BARIER_VIRTUAL_REGISTER	dev/gt64260reg.h	212;"	d
PCI_1SYNC_BARIER_VIRTUAL_REGISTER	dev/gt96132reg.h	102;"	d
PCI_1SYNC_BARIER_VIRTUAL_REGISTER	dev/mv64340reg.h	221;"	d
PCI_1SYNC_BARRIER_VIRTUAL_REGISTER	dev/gt64240reg.h	706;"	d
PCI_1SYNC_BARRIER_VIRTUAL_REGISTER	dev/gt64260reg.h	697;"	d
PCI_1SYNC_BARRIER_VIRTUAL_REGISTER	dev/mv64340reg.h	583;"	d
PCI_1TIMEOUT_RETRY	dev/gt64240reg.h	662;"	d
PCI_1TIMEOUT_RETRY	dev/gt64260reg.h	653;"	d
PCI_1TIMEOUT_RETRY	dev/gt96132reg.h	245;"	d
PCI_1TIMEOUT_RETRY	dev/mv64340reg.h	540;"	d
PCI_1_ACCESS_CONTROL_BASE_0_HIGH	dev/mv64360reg.h	490;"	d
PCI_1_ACCESS_CONTROL_BASE_0_LOW	dev/mv64360reg.h	489;"	d
PCI_1_ACCESS_CONTROL_BASE_1_HIGH	dev/mv64360reg.h	493;"	d
PCI_1_ACCESS_CONTROL_BASE_1_LOW	dev/mv64360reg.h	492;"	d
PCI_1_ACCESS_CONTROL_BASE_2_HIGH	dev/mv64360reg.h	496;"	d
PCI_1_ACCESS_CONTROL_BASE_2_LOW	dev/mv64360reg.h	495;"	d
PCI_1_ACCESS_CONTROL_BASE_3_HIGH	dev/mv64360reg.h	499;"	d
PCI_1_ACCESS_CONTROL_BASE_3_LOW	dev/mv64360reg.h	498;"	d
PCI_1_ACCESS_CONTROL_BASE_4_HIGH	dev/mv64360reg.h	502;"	d
PCI_1_ACCESS_CONTROL_BASE_4_LOW	dev/mv64360reg.h	501;"	d
PCI_1_ACCESS_CONTROL_BASE_5_HIGH	dev/mv64360reg.h	505;"	d
PCI_1_ACCESS_CONTROL_BASE_5_LOW	dev/mv64360reg.h	504;"	d
PCI_1_ACCESS_CONTROL_SIZE_0	dev/mv64360reg.h	491;"	d
PCI_1_ACCESS_CONTROL_SIZE_1	dev/mv64360reg.h	494;"	d
PCI_1_ACCESS_CONTROL_SIZE_2	dev/mv64360reg.h	497;"	d
PCI_1_ACCESS_CONTROL_SIZE_3	dev/mv64360reg.h	500;"	d
PCI_1_ACCESS_CONTROL_SIZE_4	dev/mv64360reg.h	503;"	d
PCI_1_ACCESS_CONTROL_SIZE_5	dev/mv64360reg.h	506;"	d
PCI_1_ADDR_DECODE_CONTROL	dev/mv64360reg.h	429;"	d
PCI_1_ARBITER	dev/gt64240reg.h	132;"	d
PCI_1_ARBITER	dev/gt64260reg.h	123;"	d
PCI_1_ARBITER	dev/mv64340reg.h	132;"	d
PCI_1_ARBITER_CONTROL	dev/mv64360reg.h	456;"	d
PCI_1_BAR_EN	dev/gt64240reg.h	130;"	d
PCI_1_BAR_EN	dev/gt64260reg.h	121;"	d
PCI_1_BAR_EN	dev/mv64340reg.h	130;"	d
PCI_1_BASE_ADDR_REG_ENABLE	dev/mv64360reg.h	383;"	d
PCI_1_COMMAND	dev/mv64360reg.h	446;"	d
PCI_1_CONFIG_ADDR	dev/mv64360reg.h	514;"	d
PCI_1_CONFIG_DATA_VIRTUAL_REG	dev/mv64360reg.h	515;"	d
PCI_1_CPU_BAR_SIZE	dev/mv64360reg.h	377;"	d
PCI_1_CPU_BASE_ADDR_REMAP_HIGH	dev/mv64360reg.h	423;"	d
PCI_1_CPU_BASE_ADDR_REMAP_LOW	dev/mv64360reg.h	421;"	d
PCI_1_CROSS_BAR_CONTROL_HIGH	dev/mv64360reg.h	460;"	d
PCI_1_CROSS_BAR_CONTROL_LOW	dev/mv64360reg.h	458;"	d
PCI_1_CROSS_BAR_TIMEOUT	dev/mv64360reg.h	462;"	d
PCI_1_CS_0_BANK_SIZE	dev/mv64360reg.h	353;"	d
PCI_1_CS_0_BASE_ADDR_REMAP	dev/mv64360reg.h	385;"	d
PCI_1_CS_0_BASE_HIGH_ADDR_REMAP	dev/mv64360reg.h	393;"	d
PCI_1_CS_1_BANK_SIZE	dev/mv64360reg.h	355;"	d
PCI_1_CS_1_BASE_ADDR_REMAP	dev/mv64360reg.h	387;"	d
PCI_1_CS_1_BASE_HIGH_ADDR_REMAP	dev/mv64360reg.h	395;"	d
PCI_1_CS_2_BANK_SIZE	dev/mv64360reg.h	357;"	d
PCI_1_CS_2_BASE_ADDR_REMAP	dev/mv64360reg.h	389;"	d
PCI_1_CS_2_BASE_HIGH_ADDR_REMAP	dev/mv64360reg.h	397;"	d
PCI_1_CS_3_BANK_SIZE	dev/mv64360reg.h	359;"	d
PCI_1_CS_3_BASE_ADDR_REMAP	dev/mv64360reg.h	391;"	d
PCI_1_CS_3_BASE_HIGH_ADDR_REMAP	dev/mv64360reg.h	399;"	d
PCI_1_DEVCS_0_BANK_SIZE	dev/mv64360reg.h	361;"	d
PCI_1_DEVCS_0_BASE_ADDR_REMAP	dev/mv64360reg.h	401;"	d
PCI_1_DEVCS_1_BANK_SIZE	dev/mv64360reg.h	363;"	d
PCI_1_DEVCS_1_BASE_ADDR_REMAP	dev/mv64360reg.h	403;"	d
PCI_1_DEVCS_2_BANK_SIZE	dev/mv64360reg.h	365;"	d
PCI_1_DEVCS_2_BASE_ADDR_REMAP	dev/mv64360reg.h	405;"	d
PCI_1_DEVCS_3_BANK_SIZE	dev/mv64360reg.h	367;"	d
PCI_1_DEVCS_3_BASE_ADDR_REMAP	dev/mv64360reg.h	407;"	d
PCI_1_DEVCS_BOOTCS_BASE_ADDR_REMAP	dev/mv64360reg.h	409;"	d
PCI_1_DEVCS_BOOT_BANK_SIZE	dev/mv64360reg.h	369;"	d
PCI_1_DLL_STATUS_AND_COMMAND	dev/mv64360reg.h	442;"	d
PCI_1_ERROR_ADDR_HIGH	dev/mv64360reg.h	528;"	d
PCI_1_ERROR_ADDR_LOW	dev/mv64360reg.h	526;"	d
PCI_1_ERROR_ATTRIBUTE	dev/mv64360reg.h	530;"	d
PCI_1_ERROR_CAUSE	dev/mv64360reg.h	534;"	d
PCI_1_ERROR_COMMAND	dev/mv64360reg.h	532;"	d
PCI_1_ERROR_MASK	dev/mv64360reg.h	536;"	d
PCI_1_EXPANSION_ROM_BAR_SIZE	dev/mv64360reg.h	381;"	d
PCI_1_EXPANSION_ROM_BASE_ADDR_REMAP	dev/mv64360reg.h	427;"	d
PCI_1_HEADERS_RETARGET_BASE	dev/mv64360reg.h	433;"	d
PCI_1_HEADERS_RETARGET_CONTROL	dev/mv64360reg.h	431;"	d
PCI_1_HEADERS_RETARGET_HIGH	dev/mv64360reg.h	435;"	d
PCI_1_INTEGRATED_SRAM_BAR_SIZE	dev/mv64360reg.h	379;"	d
PCI_1_INTEGRATED_SRAM_BASE_ADDR_REMAP	dev/mv64360reg.h	425;"	d
PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG	dev/mv64360reg.h	517;"	d
PCI_1_IO_ADDR_REMAP	dev/mv64360reg.h	154;"	d
PCI_1_IO_BASE_ADDR	dev/mv64360reg.h	119;"	d
PCI_1_IO_HIGH	dev/gt64240reg.h	122;"	d
PCI_1_IO_HIGH	dev/gt64260reg.h	113;"	d
PCI_1_IO_HIGH	dev/mv64340reg.h	122;"	d
PCI_1_IO_LOW	dev/gt64240reg.h	121;"	d
PCI_1_IO_LOW	dev/gt64260reg.h	112;"	d
PCI_1_IO_LOW	dev/mv64340reg.h	121;"	d
PCI_1_IO_SIZE	dev/mv64360reg.h	120;"	d
PCI_1_MEM1_HIGH	dev/gt64240reg.h	126;"	d
PCI_1_MEM1_HIGH	dev/gt64260reg.h	117;"	d
PCI_1_MEM1_HIGH	dev/mv64340reg.h	126;"	d
PCI_1_MEM1_LOW	dev/gt64240reg.h	125;"	d
PCI_1_MEM1_LOW	dev/gt64260reg.h	116;"	d
PCI_1_MEM1_LOW	dev/mv64340reg.h	125;"	d
PCI_1_MEMORY0_BASE_ADDR	dev/mv64360reg.h	121;"	d
PCI_1_MEMORY0_HIGH_ADDR_REMAP	dev/mv64360reg.h	156;"	d
PCI_1_MEMORY0_LOW_ADDR_REMAP	dev/mv64360reg.h	155;"	d
PCI_1_MEMORY0_SIZE	dev/mv64360reg.h	122;"	d
PCI_1_MEMORY1_BASE_ADDR	dev/mv64360reg.h	123;"	d
PCI_1_MEMORY1_HIGH_ADDR_REMAP	dev/mv64360reg.h	158;"	d
PCI_1_MEMORY1_LOW_ADDR_REMAP	dev/mv64360reg.h	157;"	d
PCI_1_MEMORY1_SIZE	dev/mv64360reg.h	124;"	d
PCI_1_MEMORY2_BASE_ADDR	dev/mv64360reg.h	125;"	d
PCI_1_MEMORY2_HIGH_ADDR_REMAP	dev/mv64360reg.h	160;"	d
PCI_1_MEMORY2_LOW_ADDR_REMAP	dev/mv64360reg.h	159;"	d
PCI_1_MEMORY2_SIZE	dev/mv64360reg.h	126;"	d
PCI_1_MEMORY3_BASE_ADDR	dev/mv64360reg.h	127;"	d
PCI_1_MEMORY3_HIGH_ADDR_REMAP	dev/mv64360reg.h	162;"	d
PCI_1_MEMORY3_LOW_ADDR_REMAP	dev/mv64360reg.h	161;"	d
PCI_1_MEMORY3_SIZE	dev/mv64360reg.h	128;"	d
PCI_1_MMASK	dev/mv64360reg.h	543;"	d
PCI_1_MODE	dev/mv64360reg.h	448;"	d
PCI_1_MPP_PADS_DRIVE_CONTROL	dev/mv64360reg.h	444;"	d
PCI_1_MSI_TRIGGER_TIMER	dev/mv64360reg.h	454;"	d
PCI_1_P2P_CONFIG	dev/mv64360reg.h	468;"	d
PCI_1_P2P_I_O_BAR_SIZE	dev/mv64360reg.h	375;"	d
PCI_1_P2P_I_O_BASE_ADDR_REMAP	dev/mv64360reg.h	419;"	d
PCI_1_P2P_MEM0_BAR_SIZE	dev/mv64360reg.h	371;"	d
PCI_1_P2P_MEM0_BASE_ADDR_REMAP_HIGH	dev/mv64360reg.h	413;"	d
PCI_1_P2P_MEM0_BASE_ADDR_REMAP_LOW	dev/mv64360reg.h	411;"	d
PCI_1_P2P_MEM1_BAR_SIZE	dev/mv64360reg.h	373;"	d
PCI_1_P2P_MEM1_BASE_ADDR_REMAP_HIGH	dev/mv64360reg.h	417;"	d
PCI_1_P2P_MEM1_BASE_ADDR_REMAP_LOW	dev/mv64360reg.h	415;"	d
PCI_1_READ_BUFFER_DISCARD_TIMER	dev/mv64360reg.h	452;"	d
PCI_1_RETRY	dev/mv64360reg.h	450;"	d
PCI_1_SERR_MASK	dev/mv64360reg.h	524;"	d
PCI_1_SYNC_BARRIER_TRIGGER_REG	dev/mv64360reg.h	464;"	d
PCI_1_SYNC_BARRIER_VIRTUAL_REG	dev/mv64360reg.h	466;"	d
PCI_1_TIME_OUT	dev/gt64240reg.h	128;"	d
PCI_1_TIME_OUT	dev/gt64260reg.h	119;"	d
PCI_1_TIME_OUT	dev/mv64340reg.h	128;"	d
PCI_ACCESS_CONTROL_BASE_0_HIGH	dev/gt64420reg.h	496;"	d
PCI_ACCESS_CONTROL_BASE_0_LOW	dev/gt64420reg.h	495;"	d
PCI_ACCESS_CONTROL_BASE_1_HIGH	dev/gt64420reg.h	499;"	d
PCI_ACCESS_CONTROL_BASE_1_LOW	dev/gt64420reg.h	498;"	d
PCI_ACCESS_CONTROL_BASE_2_HIGH	dev/gt64420reg.h	502;"	d
PCI_ACCESS_CONTROL_BASE_2_LOW	dev/gt64420reg.h	501;"	d
PCI_ACCESS_CONTROL_BASE_3_HIGH	dev/gt64420reg.h	505;"	d
PCI_ACCESS_CONTROL_BASE_3_LOW	dev/gt64420reg.h	504;"	d
PCI_ACCESS_CONTROL_BASE_4_HIGH	dev/gt64420reg.h	508;"	d
PCI_ACCESS_CONTROL_BASE_4_LOW	dev/gt64420reg.h	507;"	d
PCI_ACCESS_CONTROL_BASE_5_HIGH	dev/gt64420reg.h	511;"	d
PCI_ACCESS_CONTROL_BASE_5_LOW	dev/gt64420reg.h	510;"	d
PCI_ACCESS_CONTROL_SIZE_0	dev/gt64420reg.h	497;"	d
PCI_ACCESS_CONTROL_SIZE_1	dev/gt64420reg.h	500;"	d
PCI_ACCESS_CONTROL_SIZE_2	dev/gt64420reg.h	503;"	d
PCI_ACCESS_CONTROL_SIZE_3	dev/gt64420reg.h	506;"	d
PCI_ACCESS_CONTROL_SIZE_4	dev/gt64420reg.h	509;"	d
PCI_ACCESS_CONTROL_SIZE_5	dev/gt64420reg.h	512;"	d
PCI_ADDRESS_DECODE_CONTROL	dev/gt64420reg.h	477;"	d
PCI_ARBITER	dev/gt64420reg.h	116;"	d
PCI_ARBITER_CONTROL	dev/gt64420reg.h	488;"	d
PCI_BAR_EN	dev/gt64420reg.h	115;"	d
PCI_BASE_ADDRESS_REGISTERS_ENABLE	dev/gt64420reg.h	466;"	d
PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE	dev/gt64240reg.h	819;"	d
PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE	dev/gt64260reg.h	810;"	d
PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE	dev/gt64420reg.h	546;"	d
PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE	dev/gt96132reg.h	336;"	d
PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE	dev/mv64340reg.h	656;"	d
PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE	dev/mv64360reg.h	552;"	d
PCI_BOOTCS_BASE_ADDRESS	dev/gt64240reg.h	848;"	d
PCI_BOOTCS_BASE_ADDRESS	dev/gt64260reg.h	839;"	d
PCI_BOOTCS_BASE_ADDRESS_HIGH	dev/gt64420reg.h	592;"	d
PCI_BOOTCS_BASE_ADDRESS_HIGH	dev/mv64340reg.h	714;"	d
PCI_BOOTCS_BASE_ADDRESS_LOW	dev/gt64420reg.h	591;"	d
PCI_BOOTCS_BASE_ADDRESS_LOW	dev/mv64340reg.h	713;"	d
PCI_BOOT_CS_BASE_ADDR_HIGH	dev/mv64360reg.h	606;"	d
PCI_BOOT_CS_BASE_ADDR_LOW	dev/mv64360reg.h	605;"	d
PCI_CAPABILTY_LIST_POINTER	dev/gt64240reg.h	828;"	d
PCI_CAPABILTY_LIST_POINTER	dev/gt64260reg.h	819;"	d
PCI_CAPABILTY_LIST_POINTER	dev/gt64420reg.h	555;"	d
PCI_CAPABILTY_LIST_POINTER	dev/mv64340reg.h	665;"	d
PCI_CAPABILTY_LIST_POINTER	dev/mv64360reg.h	562;"	d
PCI_CLASS_CODE_AND_REVISION_ID	dev/gt64240reg.h	818;"	d
PCI_CLASS_CODE_AND_REVISION_ID	dev/gt64260reg.h	809;"	d
PCI_CLASS_CODE_AND_REVISION_ID	dev/gt64420reg.h	545;"	d
PCI_CLASS_CODE_AND_REVISION_ID	dev/gt96132reg.h	335;"	d
PCI_CLASS_CODE_AND_REVISION_ID	dev/mv64340reg.h	655;"	d
PCI_CLASS_CODE_AND_REVISION_ID	dev/mv64360reg.h	551;"	d
PCI_COMMAND	dev/gt64420reg.h	483;"	d
PCI_COMPACT_PCI_HOT_SWAP	dev/mv64360reg.h	575;"	d
PCI_COMPACT_PCI_HOT_SWAP_CAPABILITY	dev/gt64240reg.h	838;"	d
PCI_COMPACT_PCI_HOT_SWAP_CAPABILITY	dev/gt64260reg.h	829;"	d
PCI_COMPACT_PCI_HOT_SWAP_CAPABILITY	dev/gt64420reg.h	565;"	d
PCI_COMPACT_PCI_HOT_SWAP_CAPABILITY	dev/mv64340reg.h	677;"	d
PCI_CONFIGURATION_ADDRESS	dev/gt64420reg.h	519;"	d
PCI_CONFIGURATION_DATA_VIRTUAL_REGISTER	dev/gt64420reg.h	520;"	d
PCI_CPU_BASE_ADDRESS	dev/gt64240reg.h	857;"	d
PCI_CPU_BASE_ADDRESS	dev/gt64260reg.h	848;"	d
PCI_CPU_BASE_ADDR_HIGH	dev/mv64360reg.h	608;"	d
PCI_CPU_BASE_ADDR_LOW	dev/mv64360reg.h	607;"	d
PCI_CROSS_BAR_CONTROL_HIGH	dev/gt64420reg.h	491;"	d
PCI_CROSS_BAR_CONTROL_LOW	dev/gt64420reg.h	490;"	d
PCI_CROSS_BAR_TIMEOUT	dev/gt64420reg.h	492;"	d
PCI_CS_0_BANK_SIZE	dev/gt64420reg.h	456;"	d
PCI_CS_0_BASE_ADDRESS	dev/gt64240reg.h	844;"	d
PCI_CS_0_BASE_ADDRESS	dev/gt64260reg.h	835;"	d
PCI_CS_0_BASE_ADDRESS_HIGH	dev/gt64420reg.h	548;"	d
PCI_CS_0_BASE_ADDRESS_HIGH	dev/mv64340reg.h	699;"	d
PCI_CS_0_BASE_ADDRESS_LOW	dev/gt64420reg.h	547;"	d
PCI_CS_0_BASE_ADDRESS_LOW	dev/mv64340reg.h	698;"	d
PCI_CS_0_BASE_ADDRESS_REMAP	dev/gt64420reg.h	467;"	d
PCI_CS_1_BANK_SIZE	dev/gt64420reg.h	457;"	d
PCI_CS_1_BASE_ADDRESS	dev/gt64240reg.h	845;"	d
PCI_CS_1_BASE_ADDRESS	dev/gt64260reg.h	836;"	d
PCI_CS_1_BASE_ADDRESS_HIGH	dev/gt64420reg.h	550;"	d
PCI_CS_1_BASE_ADDRESS_HIGH	dev/mv64340reg.h	701;"	d
PCI_CS_1_BASE_ADDRESS_LOW	dev/gt64420reg.h	549;"	d
PCI_CS_1_BASE_ADDRESS_LOW	dev/mv64340reg.h	700;"	d
PCI_CS_1_BASE_ADDRESS_REMAP	dev/gt64420reg.h	468;"	d
PCI_CS_2_0_BASE_ADDRESS	dev/gt96132reg.h	341;"	d
PCI_CS_2_BANK_SIZE	dev/gt64420reg.h	458;"	d
PCI_CS_2_BASE_ADDRESS	dev/gt64240reg.h	846;"	d
PCI_CS_2_BASE_ADDRESS	dev/gt64260reg.h	837;"	d
PCI_CS_2_BASE_ADDRESS_HIGH	dev/gt64420reg.h	572;"	d
PCI_CS_2_BASE_ADDRESS_HIGH	dev/mv64340reg.h	703;"	d
PCI_CS_2_BASE_ADDRESS_LOW	dev/gt64420reg.h	571;"	d
PCI_CS_2_BASE_ADDRESS_LOW	dev/mv64340reg.h	702;"	d
PCI_CS_2_BASE_ADDRESS_REMAP	dev/gt64420reg.h	469;"	d
PCI_CS_3_BANK_SIZE	dev/gt64420reg.h	459;"	d
PCI_CS_3_BASE_ADDRESS	dev/gt64240reg.h	847;"	d
PCI_CS_3_BASE_ADDRESS	dev/gt64260reg.h	838;"	d
PCI_CS_3_BASE_ADDRESS_HIGH	dev/gt64420reg.h	574;"	d
PCI_CS_3_BASE_ADDRESS_HIGH	dev/mv64340reg.h	712;"	d
PCI_CS_3_BASE_ADDRESS_LOW	dev/gt64420reg.h	573;"	d
PCI_CS_3_BASE_ADDRESS_LOW	dev/mv64340reg.h	711;"	d
PCI_CS_3_BASE_ADDRESS_REMAP	dev/gt64420reg.h	470;"	d
PCI_CS_3_BOOTCS_BASE_ADDRESS	dev/gt96132reg.h	342;"	d
PCI_DAC_BOOTCS_BASE_ADDRESS_HIGH	dev/gt64240reg.h	901;"	d
PCI_DAC_BOOTCS_BASE_ADDRESS_HIGH	dev/gt64260reg.h	892;"	d
PCI_DAC_BOOTCS_BASE_ADDRESS_LOW	dev/gt64240reg.h	900;"	d
PCI_DAC_BOOTCS_BASE_ADDRESS_LOW	dev/gt64260reg.h	891;"	d
PCI_DAC_CPU_BASE_ADDRESS_HIGH	dev/gt64240reg.h	903;"	d
PCI_DAC_CPU_BASE_ADDRESS_HIGH	dev/gt64260reg.h	894;"	d
PCI_DAC_CPU_BASE_ADDRESS_LOW	dev/gt64240reg.h	902;"	d
PCI_DAC_CPU_BASE_ADDRESS_LOW	dev/gt64260reg.h	893;"	d
PCI_DAC_CS_0_BASE_ADDRESS_HIGH	dev/gt64240reg.h	888;"	d
PCI_DAC_CS_0_BASE_ADDRESS_HIGH	dev/gt64260reg.h	879;"	d
PCI_DAC_CS_0_BASE_ADDRESS_LOW	dev/gt64240reg.h	887;"	d
PCI_DAC_CS_0_BASE_ADDRESS_LOW	dev/gt64260reg.h	878;"	d
PCI_DAC_CS_1_BASE_ADDRESS_HIGH	dev/gt64240reg.h	890;"	d
PCI_DAC_CS_1_BASE_ADDRESS_HIGH	dev/gt64260reg.h	881;"	d
PCI_DAC_CS_1_BASE_ADDRESS_LOW	dev/gt64240reg.h	889;"	d
PCI_DAC_CS_1_BASE_ADDRESS_LOW	dev/gt64260reg.h	880;"	d
PCI_DAC_CS_2_BASE_ADDRESS_HIGH	dev/gt64240reg.h	892;"	d
PCI_DAC_CS_2_BASE_ADDRESS_HIGH	dev/gt64260reg.h	883;"	d
PCI_DAC_CS_2_BASE_ADDRESS_LOW	dev/gt64240reg.h	891;"	d
PCI_DAC_CS_2_BASE_ADDRESS_LOW	dev/gt64260reg.h	882;"	d
PCI_DAC_CS_3_BASE_ADDRESS_HIGH	dev/gt64240reg.h	899;"	d
PCI_DAC_CS_3_BASE_ADDRESS_HIGH	dev/gt64260reg.h	890;"	d
PCI_DAC_CS_3_BASE_ADDRESS_LOW	dev/gt64240reg.h	898;"	d
PCI_DAC_CS_3_BASE_ADDRESS_LOW	dev/gt64260reg.h	889;"	d
PCI_DAC_P2P_MEM0_BASE_ADDRESS_HIGH	dev/gt64240reg.h	868;"	d
PCI_DAC_P2P_MEM0_BASE_ADDRESS_HIGH	dev/gt64260reg.h	859;"	d
PCI_DAC_P2P_MEM0_BASE_ADDRESS_LOW	dev/gt64240reg.h	867;"	d
PCI_DAC_P2P_MEM0_BASE_ADDRESS_LOW	dev/gt64260reg.h	858;"	d
PCI_DAC_P2P_MEM1_BASE_ADDRESS_HIGH	dev/gt64240reg.h	880;"	d
PCI_DAC_P2P_MEM1_BASE_ADDRESS_HIGH	dev/gt64260reg.h	871;"	d
PCI_DAC_P2P_MEM1_BASE_ADDRESS_LOW	dev/gt64240reg.h	879;"	d
PCI_DAC_P2P_MEM1_BASE_ADDRESS_LOW	dev/gt64260reg.h	870;"	d
PCI_DAC_SCS_0_BASE_ADDRESS_HIGH	dev/gt64240reg.h	864;"	d
PCI_DAC_SCS_0_BASE_ADDRESS_HIGH	dev/gt64260reg.h	855;"	d
PCI_DAC_SCS_0_BASE_ADDRESS_LOW	dev/gt64240reg.h	863;"	d
PCI_DAC_SCS_0_BASE_ADDRESS_LOW	dev/gt64260reg.h	854;"	d
PCI_DAC_SCS_1_BASE_ADDRESS_HIGH	dev/gt64240reg.h	866;"	d
PCI_DAC_SCS_1_BASE_ADDRESS_HIGH	dev/gt64260reg.h	857;"	d
PCI_DAC_SCS_1_BASE_ADDRESS_LOW	dev/gt64240reg.h	865;"	d
PCI_DAC_SCS_1_BASE_ADDRESS_LOW	dev/gt64260reg.h	856;"	d
PCI_DAC_SCS_2_BASE_ADDRESS_HIGH	dev/gt64240reg.h	876;"	d
PCI_DAC_SCS_2_BASE_ADDRESS_HIGH	dev/gt64260reg.h	867;"	d
PCI_DAC_SCS_2_BASE_ADDRESS_LOW	dev/gt64240reg.h	875;"	d
PCI_DAC_SCS_2_BASE_ADDRESS_LOW	dev/gt64260reg.h	866;"	d
PCI_DAC_SCS_3_BASE_ADDRESS_HIGH	dev/gt64240reg.h	878;"	d
PCI_DAC_SCS_3_BASE_ADDRESS_HIGH	dev/gt64260reg.h	869;"	d
PCI_DAC_SCS_3_BASE_ADDRESS_LOW	dev/gt64240reg.h	877;"	d
PCI_DAC_SCS_3_BASE_ADDRESS_LOW	dev/gt64260reg.h	868;"	d
PCI_DEVCS_0_BANK_SIZE	dev/gt64420reg.h	460;"	d
PCI_DEVCS_0_BASE_ADDRESS_HIGH	dev/gt64420reg.h	581;"	d
PCI_DEVCS_0_BASE_ADDRESS_LOW	dev/gt64420reg.h	580;"	d
PCI_DEVCS_0_BASE_ADDRESS_REMAP	dev/gt64420reg.h	471;"	d
PCI_DEVCS_0_BASE_ADDR_HIGH	dev/mv64360reg.h	593;"	d
PCI_DEVCS_0_BASE_ADDR_LOW	dev/mv64360reg.h	592;"	d
PCI_DEVCS_1_BANK_SIZE	dev/gt64420reg.h	461;"	d
PCI_DEVCS_1_BASE_ADDRESS_HIGH	dev/gt64420reg.h	583;"	d
PCI_DEVCS_1_BASE_ADDRESS_LOW	dev/gt64420reg.h	582;"	d
PCI_DEVCS_1_BASE_ADDRESS_REMAP	dev/gt64420reg.h	472;"	d
PCI_DEVCS_1_BASE_ADDR_HIGH	dev/mv64360reg.h	595;"	d
PCI_DEVCS_1_BASE_ADDR_LOW	dev/mv64360reg.h	594;"	d
PCI_DEVCS_2_BANK_SIZE	dev/gt64420reg.h	462;"	d
PCI_DEVCS_2_BASE_ADDRESS_HIGH	dev/gt64420reg.h	585;"	d
PCI_DEVCS_2_BASE_ADDRESS_LOW	dev/gt64420reg.h	584;"	d
PCI_DEVCS_2_BASE_ADDRESS_REMAP	dev/gt64420reg.h	473;"	d
PCI_DEVCS_2_BASE_ADDR_HIGH	dev/mv64360reg.h	597;"	d
PCI_DEVCS_2_BASE_ADDR_LOW	dev/mv64360reg.h	596;"	d
PCI_DEVCS_3_BANK_SIZE	dev/gt64420reg.h	463;"	d
PCI_DEVCS_3_BASE_ADDRESS_HIGH	dev/gt64420reg.h	590;"	d
PCI_DEVCS_3_BASE_ADDRESS_LOW	dev/gt64420reg.h	589;"	d
PCI_DEVCS_3_BASE_ADDRESS_REMAP	dev/gt64420reg.h	474;"	d
PCI_DEVCS_3_BASE_ADDR_HIGH	dev/mv64360reg.h	604;"	d
PCI_DEVCS_3_BASE_ADDR_LOW	dev/mv64360reg.h	603;"	d
PCI_DEVCS_BOOTCS_BASE_ADDRESS_REMAP	dev/gt64420reg.h	475;"	d
PCI_DEVCS_BOOT_BANK_SIZE	dev/gt64420reg.h	464;"	d
PCI_DEVICE_AND_VENDOR_ID	dev/gt64240reg.h	814;"	d
PCI_DEVICE_AND_VENDOR_ID	dev/gt64260reg.h	805;"	d
PCI_DEVICE_AND_VENDOR_ID	dev/gt64420reg.h	542;"	d
PCI_DEVICE_AND_VENDOR_ID	dev/gt96132reg.h	333;"	d
PCI_DEVICE_AND_VENDOR_ID	dev/mv64340reg.h	651;"	d
PCI_DEVICE_AND_VENDOR_ID	dev/mv64360reg.h	549;"	d
PCI_DEV_NO_M1543C	dev/m1543reg.h	34;"	d
PCI_DEV_NO_M1543C_PMU	dev/m1543reg.h	63;"	d
PCI_ERROR_ADDRESS_HIGH	dev/gt64420reg.h	529;"	d
PCI_ERROR_ADDRESS_LOW	dev/gt64420reg.h	528;"	d
PCI_ERROR_CAUSE	dev/gt64420reg.h	533;"	d
PCI_ERROR_COMMAND	dev/gt64420reg.h	532;"	d
PCI_ERROR_DATA_HIGH	dev/gt64420reg.h	531;"	d
PCI_ERROR_DATA_LOW	dev/gt64420reg.h	530;"	d
PCI_ERROR_MASK	dev/gt64420reg.h	534;"	d
PCI_EXPANSION_ROM_BAR_SIZE	dev/gt64420reg.h	465;"	d
PCI_EXPANSION_ROM_BASE_ADDRESS_REGISTER	dev/gt64240reg.h	827;"	d
PCI_EXPANSION_ROM_BASE_ADDRESS_REGISTER	dev/gt64260reg.h	818;"	d
PCI_EXPANSION_ROM_BASE_ADDRESS_REGISTER	dev/gt64420reg.h	554;"	d
PCI_EXPANSION_ROM_BASE_ADDRESS_REGISTER	dev/mv64340reg.h	664;"	d
PCI_EXPANSION_ROM_BASE_ADDRESS_REMAP	dev/gt64420reg.h	476;"	d
PCI_EXPANSION_ROM_BASE_ADDR_REG	dev/mv64360reg.h	561;"	d
PCI_INTEGRATED_SRAM_BASE_ADDRESS_HIGH	dev/mv64340reg.h	690;"	d
PCI_INTEGRATED_SRAM_BASE_ADDRESS_LOW	dev/mv64340reg.h	689;"	d
PCI_INTERGRATED_SRAM_BASE_ADDR_HIGH	dev/mv64360reg.h	586;"	d
PCI_INTERGRATED_SRAM_BASE_ADDR_LOW	dev/mv64360reg.h	585;"	d
PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS	dev/gt64240reg.h	825;"	d
PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS	dev/gt64260reg.h	816;"	d
PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS	dev/gt96132reg.h	344;"	d
PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS	dev/mv64340reg.h	662;"	d
PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS	dev/gt64240reg.h	824;"	d
PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS	dev/gt64260reg.h	815;"	d
PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS	dev/gt96132reg.h	343;"	d
PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS	dev/mv64340reg.h	661;"	d
PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS_HIGH	dev/gt64420reg.h	552;"	d
PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS_LOW	dev/gt64420reg.h	551;"	d
PCI_INTERNAL_REGS_ADDRESS_BASE	dev/mv64340reg.h	727;"	d
PCI_INTERNAL_REGS_I_O_MAPPED_BASE_ADDR	dev/mv64360reg.h	619;"	d
PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_HIGH	dev/mv64360reg.h	559;"	d
PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_LO	dev/mv64360reg.h	558;"	d
PCI_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER	dev/gt64420reg.h	521;"	d
PCI_INTERRUPT_PIN_AND_LINE	dev/gt64240reg.h	829;"	d
PCI_INTERRUPT_PIN_AND_LINE	dev/gt64260reg.h	820;"	d
PCI_INTERRUPT_PIN_AND_LINE	dev/gt64420reg.h	556;"	d
PCI_INTERRUPT_PIN_AND_LINE	dev/gt96132reg.h	351;"	d
PCI_INTERRUPT_PIN_AND_LINE	dev/mv64340reg.h	666;"	d
PCI_INTERRUPT_PIN_AND_LINE	dev/mv64360reg.h	563;"	d
PCI_IO_BASE	dev/gt64420reg.h	101;"	d
PCI_IO_BASE_ADDRESS	dev/gt64420reg.h	598;"	d
PCI_IO_SIZE	dev/gt64420reg.h	102;"	d
PCI_IO_SPACE_BASE	include/tgt/bonito.h	80;"	d
PCI_IO_SPACE_PCI_BASE	dev/mpc107reg.h	53;"	d
PCI_IO_SPACE_PCI_BASE	dev/mpc107reg.h	74;"	d
PCI_I_O_ADDRESS_REMAP	dev/gt64420reg.h	170;"	d
PCI_I_O_BASE_ADDRESS	dev/gt64420reg.h	156;"	d
PCI_I_O_SIZE	dev/gt64420reg.h	157;"	d
PCI_LOCAL_MEM_ISA_BASE	dev/mpc107reg.h	58;"	d
PCI_LOCAL_MEM_ISA_BASE	dev/mpc107reg.h	79;"	d
PCI_LOCAL_MEM_ISA_BASE	include/tgt/bonito.h	68;"	d
PCI_LOCAL_MEM_ISA_BASE	include/tgt/bonito.h	75;"	d
PCI_LOCAL_MEM_PCI_BASE	dev/mpc107reg.h	57;"	d
PCI_LOCAL_MEM_PCI_BASE	dev/mpc107reg.h	78;"	d
PCI_LOCAL_MEM_PCI_BASE	include/tgt/bonito.h	67;"	d
PCI_LOCAL_MEM_PCI_BASE	include/tgt/bonito.h	74;"	d
PCI_LOCAL_REG_PCI_BASE	include/tgt/bonito.h	69;"	d
PCI_LOCAL_REG_PCI_BASE	include/tgt/bonito.h	76;"	d
PCI_MEM0_BASE	dev/gt64420reg.h	103;"	d
PCI_MEM0_SIZE	dev/gt64420reg.h	104;"	d
PCI_MEMORY0_ADDRESS_REMAP	dev/gt64420reg.h	171;"	d
PCI_MEMORY0_BASE_ADDRESS	dev/gt64420reg.h	158;"	d
PCI_MEMORY0_HIGH_ADDRESS_REMAP	dev/gt64420reg.h	172;"	d
PCI_MEMORY0_SIZE	dev/gt64420reg.h	159;"	d
PCI_MEMORY1_ADDRESS_REMAP	dev/gt64420reg.h	173;"	d
PCI_MEMORY1_BASE_ADDRESS	dev/gt64420reg.h	160;"	d
PCI_MEMORY1_HIGH_ADDRESS_REMAP	dev/gt64420reg.h	174;"	d
PCI_MEMORY1_SIZE	dev/gt64420reg.h	161;"	d
PCI_MEMORY2_ADDRESS_REMAP	dev/gt64420reg.h	175;"	d
PCI_MEMORY2_BASE_ADDRESS	dev/gt64420reg.h	162;"	d
PCI_MEMORY2_HIGH_ADDRESS_REMAP	dev/gt64420reg.h	176;"	d
PCI_MEMORY2_SIZE	dev/gt64420reg.h	163;"	d
PCI_MEMORY3_ADDRESS_REMAP	dev/gt64420reg.h	177;"	d
PCI_MEMORY3_BASE_ADDRESS	dev/gt64420reg.h	164;"	d
PCI_MEMORY3_HIGH_ADDRESS_REMAP	dev/gt64420reg.h	178;"	d
PCI_MEMORY3_SIZE	dev/gt64420reg.h	165;"	d
PCI_MEM_SPACE_PCI_BASE	dev/mpc107reg.h	56;"	d
PCI_MEM_SPACE_PCI_BASE	dev/mpc107reg.h	77;"	d
PCI_MEM_SPACE_PCI_BASE	include/tgt/bonito.h	66;"	d
PCI_MEM_SPACE_PCI_BASE	include/tgt/bonito.h	73;"	d
PCI_MODE	dev/gt64420reg.h	484;"	d
PCI_MSI_MESSAGE_ADDR	dev/mv64360reg.h	570;"	d
PCI_MSI_MESSAGE_ADDRESS	dev/gt64240reg.h	835;"	d
PCI_MSI_MESSAGE_ADDRESS	dev/gt64260reg.h	826;"	d
PCI_MSI_MESSAGE_ADDRESS	dev/gt64420reg.h	562;"	d
PCI_MSI_MESSAGE_ADDRESS	dev/mv64340reg.h	672;"	d
PCI_MSI_MESSAGE_CONTROL	dev/gt64240reg.h	834;"	d
PCI_MSI_MESSAGE_CONTROL	dev/gt64260reg.h	825;"	d
PCI_MSI_MESSAGE_CONTROL	dev/gt64420reg.h	561;"	d
PCI_MSI_MESSAGE_CONTROL	dev/mv64340reg.h	671;"	d
PCI_MSI_MESSAGE_CONTROL	dev/mv64360reg.h	569;"	d
PCI_MSI_MESSAGE_DATA	dev/gt64240reg.h	837;"	d
PCI_MSI_MESSAGE_DATA	dev/gt64260reg.h	828;"	d
PCI_MSI_MESSAGE_DATA	dev/gt64420reg.h	564;"	d
PCI_MSI_MESSAGE_DATA	dev/mv64340reg.h	674;"	d
PCI_MSI_MESSAGE_DATA	dev/mv64360reg.h	572;"	d
PCI_MSI_MESSAGE_UPPER_ADDR	dev/mv64360reg.h	571;"	d
PCI_MSI_MESSAGE_UPPER_ADDRESS	dev/gt64240reg.h	836;"	d
PCI_MSI_MESSAGE_UPPER_ADDRESS	dev/gt64260reg.h	827;"	d
PCI_MSI_MESSAGE_UPPER_ADDRESS	dev/gt64420reg.h	563;"	d
PCI_MSI_MESSAGE_UPPER_ADDRESS	dev/mv64340reg.h	673;"	d
PCI_P2P_I_O_BASE_ADDR	dev/mv64360reg.h	618;"	d
PCI_P2P_I_O_BASE_ADDRESS	dev/gt64240reg.h	856;"	d
PCI_P2P_I_O_BASE_ADDRESS	dev/gt64260reg.h	847;"	d
PCI_P2P_I_O_BASE_ADDRESS	dev/mv64340reg.h	726;"	d
PCI_P2P_MEM0_BASE_ADDRESS	dev/gt64240reg.h	854;"	d
PCI_P2P_MEM0_BASE_ADDRESS	dev/gt64260reg.h	845;"	d
PCI_P2P_MEM0_BASE_ADDRESS_HIGH	dev/mv64340reg.h	723;"	d
PCI_P2P_MEM0_BASE_ADDRESS_LOW	dev/mv64340reg.h	722;"	d
PCI_P2P_MEM0_BASE_ADDR_HIGH	dev/mv64360reg.h	615;"	d
PCI_P2P_MEM0_BASE_ADDR_LOW	dev/mv64360reg.h	614;"	d
PCI_P2P_MEM1_BASE_ADDRESS	dev/gt64240reg.h	855;"	d
PCI_P2P_MEM1_BASE_ADDRESS	dev/gt64260reg.h	846;"	d
PCI_P2P_MEM1_BASE_ADDRESS_HIGH	dev/mv64340reg.h	725;"	d
PCI_P2P_MEM1_BASE_ADDRESS_LOW	dev/mv64340reg.h	724;"	d
PCI_P2P_MEM1_BASE_ADDR_HIGH	dev/mv64360reg.h	617;"	d
PCI_P2P_MEM1_BASE_ADDR_LOW	dev/mv64360reg.h	616;"	d
PCI_POWER_MANAGEMENT_CAPABILITY	dev/gt64240reg.h	830;"	d
PCI_POWER_MANAGEMENT_CAPABILITY	dev/gt64260reg.h	821;"	d
PCI_POWER_MANAGEMENT_CAPABILITY	dev/gt64420reg.h	557;"	d
PCI_POWER_MANAGEMENT_CAPABILITY	dev/mv64340reg.h	667;"	d
PCI_POWER_MANAGEMENT_CAPABILITY	dev/mv64360reg.h	565;"	d
PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL	dev/gt64240reg.h	831;"	d
PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL	dev/gt64260reg.h	822;"	d
PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL	dev/gt64420reg.h	558;"	d
PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL	dev/mv64340reg.h	668;"	d
PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL	dev/mv64360reg.h	566;"	d
PCI_READ_BUFFER_DISCARD_TIMER	dev/gt64420reg.h	486;"	d
PCI_SCS_0_BASE_ADDRESS	dev/gt64240reg.h	820;"	d
PCI_SCS_0_BASE_ADDRESS	dev/gt64260reg.h	811;"	d
PCI_SCS_0_BASE_ADDRESS_HIGH	dev/mv64340reg.h	658;"	d
PCI_SCS_0_BASE_ADDRESS_LOW	dev/mv64340reg.h	657;"	d
PCI_SCS_0_BASE_ADDR_HIGH	dev/mv64360reg.h	555;"	d
PCI_SCS_0_BASE_ADDR_LOW	dev/mv64360reg.h	554;"	d
PCI_SCS_1_0_BASE_ADDRESS	dev/gt96132reg.h	337;"	d
PCI_SCS_1_BASE_ADDRESS	dev/gt64240reg.h	821;"	d
PCI_SCS_1_BASE_ADDRESS	dev/gt64260reg.h	812;"	d
PCI_SCS_1_BASE_ADDRESS_HIGH	dev/mv64340reg.h	660;"	d
PCI_SCS_1_BASE_ADDRESS_LOW	dev/mv64340reg.h	659;"	d
PCI_SCS_1_BASE_ADDR_HIGH	dev/mv64360reg.h	557;"	d
PCI_SCS_1_BASE_ADDR_LOW	dev/mv64360reg.h	556;"	d
PCI_SCS_2_BASE_ADDRESS	dev/gt64240reg.h	822;"	d
PCI_SCS_2_BASE_ADDRESS	dev/gt64260reg.h	813;"	d
PCI_SCS_2_BASE_ADDRESS_HIGH	dev/mv64340reg.h	686;"	d
PCI_SCS_2_BASE_ADDRESS_LOW	dev/mv64340reg.h	685;"	d
PCI_SCS_2_BASE_ADDR_HIGH	dev/mv64360reg.h	582;"	d
PCI_SCS_2_BASE_ADDR_LOW	dev/mv64360reg.h	581;"	d
PCI_SCS_3_2_BASE_ADDRESS	dev/gt96132reg.h	338;"	d
PCI_SCS_3_BASE_ADDRESS	dev/gt64240reg.h	823;"	d
PCI_SCS_3_BASE_ADDRESS	dev/gt64260reg.h	814;"	d
PCI_SCS_3_BASE_ADDRESS_HIGH	dev/mv64340reg.h	688;"	d
PCI_SCS_3_BASE_ADDRESS_LOW	dev/mv64340reg.h	687;"	d
PCI_SCS_3_BASE_ADDR_HIGH	dev/mv64360reg.h	584;"	d
PCI_SCS_3_BASE_ADDR_LOW	dev/mv64360reg.h	583;"	d
PCI_SERR_MASK	dev/gt64420reg.h	527;"	d
PCI_STATUS_AND_COMMAND	dev/gt64240reg.h	815;"	d
PCI_STATUS_AND_COMMAND	dev/gt64260reg.h	806;"	d
PCI_STATUS_AND_COMMAND	dev/gt64420reg.h	543;"	d
PCI_STATUS_AND_COMMAND	dev/gt96132reg.h	334;"	d
PCI_STATUS_AND_COMMAND	dev/mv64340reg.h	652;"	d
PCI_STATUS_AND_COMMAND	dev/mv64360reg.h	550;"	d
PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID	dev/gt64240reg.h	826;"	d
PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID	dev/gt64260reg.h	817;"	d
PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID	dev/gt64420reg.h	553;"	d
PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID	dev/mv64340reg.h	663;"	d
PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID	dev/mv64360reg.h	560;"	d
PCI_SYNC_BARRIER_TRIGER_REGISTER	dev/gt64420reg.h	493;"	d
PCI_SYNC_BARRIER_VIRTUAL_REGISTER	dev/gt64420reg.h	494;"	d
PCI_TIMEOUT_RETRY	dev/gt64420reg.h	485;"	d
PCI_TIME_OUT	dev/gt64420reg.h	114;"	d
PCI_VPD_ADDR	dev/mv64360reg.h	567;"	d
PCI_VPD_ADDRESS	dev/gt64240reg.h	832;"	d
PCI_VPD_ADDRESS	dev/gt64260reg.h	823;"	d
PCI_VPD_ADDRESS	dev/gt64420reg.h	559;"	d
PCI_VPD_ADDRESS	dev/mv64340reg.h	669;"	d
PCI_VPD_DATA	dev/gt64240reg.h	833;"	d
PCI_VPD_DATA	dev/gt64260reg.h	824;"	d
PCI_VPD_DATA	dev/gt64420reg.h	560;"	d
PCI_VPD_DATA	dev/mv64340reg.h	670;"	d
PCI_VPD_DATA	dev/mv64360reg.h	568;"	d
PCI_X_COMMAND	dev/mv64340reg.h	675;"	d
PCI_X_COMMAND	dev/mv64360reg.h	573;"	d
PCI_X_STATUS	dev/mv64340reg.h	676;"	d
PCI_X_STATUS	dev/mv64360reg.h	574;"	d
PDP_ENDIAN	include/arpa/nameser.h	268;"	d
PFLASH_H	include/pflash.h	36;"	d
PFLASH_MAX_TIMEOUT	dev/flash.c	42;"	d	file:
PHYS_TO_UNCACHED	include/tgt/bonito.h	2;"	d
PORT_ROUTING_REGISTER	dev/gt96132reg.h	795;"	d
PPC_MSR_FP	include/powerpc.h	124;"	d
PRELIM	include/arpa/ftp.h	47;"	d
PRESET_DICT	include/linux/zutil.h	55;"	d
PRID_JADE	include/prid.h	50;"	d
PRID_LR33010	include/prid.h	61;"	d
PRID_LR33K	include/prid.h	29;"	d
PRID_R10000	include/prid.h	34;"	d
PRID_R10010	include/prid.h	62;"	d
PRID_R2000	include/prid.h	25;"	d
PRID_R2010	include/prid.h	57;"	d
PRID_R2360	include/prid.h	56;"	d
PRID_R3000	include/prid.h	26;"	d
PRID_R3010	include/prid.h	58;"	d
PRID_R3900	include/prid.h	42;"	d
PRID_R3910	include/prid.h	69;"	d
PRID_R3IDT	include/prid.h	31;"	d
PRID_R3IDT_R3041	include/prid.h	32;"	d
PRID_R3IDT_R36100	include/prid.h	33;"	d
PRID_R3SONY	include/prid.h	68;"	d
PRID_R4000	include/prid.h	28;"	d
PRID_R4010	include/prid.h	60;"	d
PRID_R4100	include/prid.h	37;"	d
PRID_R4200	include/prid.h	35;"	d
PRID_R4210	include/prid.h	63;"	d
PRID_R4300	include/prid.h	36;"	d
PRID_R4600	include/prid.h	40;"	d
PRID_R4610	include/prid.h	67;"	d
PRID_R4650	include/prid.h	43;"	d
PRID_R4700	include/prid.h	41;"	d
PRID_R5000	include/prid.h	44;"	d
PRID_R5010	include/prid.h	70;"	d
PRID_R5400	include/prid.h	49;"	d
PRID_R5400F	include/prid.h	74;"	d
PRID_R6000	include/prid.h	27;"	d
PRID_R6000A	include/prid.h	30;"	d
PRID_R6010	include/prid.h	59;"	d
PRID_R8000	include/prid.h	38;"	d
PRID_R8010	include/prid.h	65;"	d
PRID_RC3236X	include/prid.h	45;"	d
PRID_RC6447X	include/prid.h	48;"	d
PRID_RC6447XF	include/prid.h	73;"	d
PRID_RC6457X	include/prid.h	39;"	d
PRID_RC6457XF	include/prid.h	66;"	d
PRID_RM52XX	include/prid.h	47;"	d
PRID_RM52XXF	include/prid.h	72;"	d
PRID_RM7000	include/prid.h	46;"	d
PRID_RM7000F	include/prid.h	71;"	d
PRID_SOFT	include/prid.h	55;"	d
PRID_UNKF1	include/prid.h	64;"	d
PROTOCOLSIZE	include/url.h	39;"	d
PUNIT_MASTER_DEBUG_HIGH	dev/mv64360reg.h	246;"	d
PUNIT_MASTER_DEBUG_LOW	dev/mv64360reg.h	245;"	d
PUNIT_MMASK	dev/mv64360reg.h	247;"	d
PUNIT_SLAVE_DEBUG_HIGH	dev/mv64360reg.h	244;"	d
PUNIT_SLAVE_DEBUG_LOW	dev/mv64360reg.h	243;"	d
PUTLONG	include/arpa/nameser.h	384;"	d
PUTSHORT	include/arpa/nameser.h	376;"	d
PVR	include/powerpc.h	44;"	d
QFIXEDSZ	include/arpa/nameser.h	118;"	d
QUERY	include/arpa/nameser.h	133;"	d
QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE	dev/gt64240reg.h	965;"	d
QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE	dev/gt64260reg.h	956;"	d
QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE	dev/gt64420reg.h	653;"	d
QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE	dev/gt96132reg.h	412;"	d
QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE	dev/mv64340reg.h	789;"	d
QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE	dev/gt64240reg.h	942;"	d
QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE	dev/gt64260reg.h	933;"	d
QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE	dev/gt64420reg.h	630;"	d
QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE	dev/gt96132reg.h	389;"	d
QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE	dev/mv64340reg.h	766;"	d
QUEUE_CONTROL_REGISTER_CPU_SIDE	dev/gt64240reg.h	964;"	d
QUEUE_CONTROL_REGISTER_CPU_SIDE	dev/gt64260reg.h	955;"	d
QUEUE_CONTROL_REGISTER_CPU_SIDE	dev/gt64420reg.h	652;"	d
QUEUE_CONTROL_REGISTER_CPU_SIDE	dev/gt96132reg.h	411;"	d
QUEUE_CONTROL_REGISTER_CPU_SIDE	dev/mv64340reg.h	788;"	d
QUEUE_CONTROL_REGISTER_PCI_SIDE	dev/gt64240reg.h	941;"	d
QUEUE_CONTROL_REGISTER_PCI_SIDE	dev/gt64260reg.h	932;"	d
QUEUE_CONTROL_REGISTER_PCI_SIDE	dev/gt64420reg.h	629;"	d
QUEUE_CONTROL_REGISTER_PCI_SIDE	dev/gt96132reg.h	388;"	d
QUEUE_CONTROL_REGISTER_PCI_SIDE	dev/mv64340reg.h	765;"	d
Q_SIZE	include/queue.h	52;"	d
Q_SPACE	include/queue.h	54;"	d
Q_USED	include/queue.h	53;"	d
Qempty	include/queue.h	63;"	d
Qfull	include/queue.h	62;"	d
Qsize	include/queue.h	64;"	d
Qspace	include/queue.h	66;"	d
Queue	include/queue.h	/^	} Queue;$/;"	t	typeref:struct:Queue
Queue	include/queue.h	/^typedef struct Queue {$/;"	s
Qused	include/queue.h	65;"	d
RAMFILE_CPHY	include/ramfile.h	49;"	d
RAMFILE_DYNAMIC	include/ramfile.h	47;"	d
RAMFILE_RDONLY	include/ramfile.h	48;"	d
RAMFILE_STATIC	include/ramfile.h	46;"	d
RAND_MAX	include/stdlib.h	86;"	d
READ_DATA_HIGH	dev/gt64240reg.h	283;"	d
READ_DATA_HIGH	dev/gt64260reg.h	274;"	d
READ_DATA_HIGH	dev/mv64340reg.h	261;"	d
READ_DATA_LOW	dev/gt64240reg.h	282;"	d
READ_DATA_LOW	dev/gt64260reg.h	273;"	d
READ_DATA_LOW	dev/mv64340reg.h	260;"	d
READ_ID	dev/gt64240reg.h	284;"	d
READ_ID	dev/gt64260reg.h	275;"	d
READ_ID	dev/mv64340reg.h	262;"	d
RECEIVE_CLOCK_ROUTING_REGISTER	dev/gt64240reg.h	1208;"	d
RECEIVE_CLOCK_ROUTING_REGISTER	dev/gt64260reg.h	1199;"	d
RECEIVE_CLOCK_ROUTING_REGISTER	dev/gt64420reg.h	944;"	d
RECEIVE_CLOCK_ROUTING_REGISTER	dev/gt96132reg.h	289;"	d
RECEIVE_CLOCK_ROUTING_REGISTER	dev/mv64340reg.h	1058;"	d
REC_EOF	include/arpa/ftp.h	100;"	d
REC_EOR	include/arpa/ftp.h	99;"	d
REC_ESC	include/arpa/ftp.h	98;"	d
REFUSED	include/arpa/nameser.h	146;"	d
REGSZ_32	include/pmon.h	76;"	d
REGSZ_64	include/pmon.h	77;"	d
REGSZ_BOTH	include/pmon.h	78;"	d
REGSZ_DOUBLE	include/pmon.h	79;"	d
REGSZ_NONE	include/pmon.h	81;"	d
REGSZ_SINGLE	include/pmon.h	80;"	d
REG_TO_VA_l	include/ri.h	57;"	d
RES_AAONLY	include/resolv.h	136;"	d
RES_DEBUG	include/resolv.h	135;"	d
RES_DEFAULT	include/resolv.h	149;"	d
RES_DEFNAMES	include/resolv.h	141;"	d
RES_DNSRCH	include/resolv.h	143;"	d
RES_IGNTC	include/resolv.h	139;"	d
RES_INIT	include/resolv.h	134;"	d
RES_INSECURE1	include/resolv.h	144;"	d
RES_INSECURE2	include/resolv.h	145;"	d
RES_MAXNDOTS	include/resolv.h	106;"	d
RES_NOALIASES	include/resolv.h	146;"	d
RES_PRF_ADD	include/resolv.h	161;"	d
RES_PRF_ANS	include/resolv.h	159;"	d
RES_PRF_AUTH	include/resolv.h	160;"	d
RES_PRF_CLASS	include/resolv.h	156;"	d
RES_PRF_CMD	include/resolv.h	157;"	d
RES_PRF_HEAD1	include/resolv.h	162;"	d
RES_PRF_HEAD2	include/resolv.h	163;"	d
RES_PRF_HEADX	include/resolv.h	165;"	d
RES_PRF_INIT	include/resolv.h	168;"	d
RES_PRF_QUERY	include/resolv.h	166;"	d
RES_PRF_QUES	include/resolv.h	158;"	d
RES_PRF_REPLY	include/resolv.h	167;"	d
RES_PRF_STATS	include/resolv.h	154;"	d
RES_PRF_TTLID	include/resolv.h	164;"	d
RES_PRIMARY	include/resolv.h	138;"	d
RES_RECURSE	include/resolv.h	140;"	d
RES_STAYOPEN	include/resolv.h	142;"	d
RES_TIMEOUT	include/resolv.h	104;"	d
RES_USEVC	include/resolv.h	137;"	d
RES_USE_INET6	include/resolv.h	147;"	d
ROUTE_MAIN_REG	dev/gt96132reg.h	792;"	d
ROUTE_RX_CLOCK_REG	dev/gt96132reg.h	793;"	d
ROUTE_TX_CLOCK_REG	dev/gt96132reg.h	794;"	d
RRFIXEDSZ	include/arpa/nameser.h	119;"	d
RRQ	include/arpa/tftp.h	50;"	d
RTC_DATA_REG	include/tgt/bonito.h	20;"	d
RTC_INDEX_REG	include/tgt/bonito.h	19;"	d
RTC_NVRAM_BASE	include/tgt/bonito.h	21;"	d
RUNIT_MMASK	dev/mv64360reg.h	346;"	d
Ramfile	include/ramfile.h	/^typedef struct Ramfile {$/;"	s
Ramfile	include/ramfile.h	/^} Ramfile;$/;"	t	typeref:struct:Ramfile
SB	include/arpa/telnet.h	50;"	d
SCS0_HIGH	dev/gt64240reg.h	114;"	d
SCS0_HIGH	dev/gt64260reg.h	105;"	d
SCS0_HIGH	dev/mv64340reg.h	114;"	d
SCS0_LOW	dev/gt64240reg.h	113;"	d
SCS0_LOW	dev/gt64260reg.h	104;"	d
SCS0_LOW	dev/mv64340reg.h	113;"	d
SCS1_HIGH	dev/gt64240reg.h	118;"	d
SCS1_HIGH	dev/gt64260reg.h	109;"	d
SCS1_HIGH	dev/mv64340reg.h	118;"	d
SCS1_LOW	dev/gt64240reg.h	117;"	d
SCS1_LOW	dev/gt64260reg.h	108;"	d
SCS1_LOW	dev/mv64340reg.h	117;"	d
SCS2_HIGH	dev/gt64240reg.h	116;"	d
SCS2_HIGH	dev/gt64260reg.h	107;"	d
SCS2_HIGH	dev/mv64340reg.h	116;"	d
SCS2_LOW	dev/gt64240reg.h	115;"	d
SCS2_LOW	dev/gt64260reg.h	106;"	d
SCS2_LOW	dev/mv64340reg.h	115;"	d
SCS3_HIGH	dev/gt64240reg.h	120;"	d
SCS3_HIGH	dev/gt64260reg.h	111;"	d
SCS3_HIGH	dev/mv64340reg.h	120;"	d
SCS3_LOW	dev/gt64240reg.h	119;"	d
SCS3_LOW	dev/gt64260reg.h	110;"	d
SCS3_LOW	dev/mv64340reg.h	119;"	d
SCS_0_BASE_ADDRESS	dev/mv64340reg.h	149;"	d
SCS_0_HIGH_DECODE_ADDRESS	dev/gt64240reg.h	146;"	d
SCS_0_HIGH_DECODE_ADDRESS	dev/gt64260reg.h	137;"	d
SCS_0_HIGH_DECODE_ADDRESS	dev/gt96132reg.h	119;"	d
SCS_0_LOW_DECODE_ADDRESS	dev/gt64240reg.h	145;"	d
SCS_0_LOW_DECODE_ADDRESS	dev/gt64260reg.h	136;"	d
SCS_0_LOW_DECODE_ADDRESS	dev/gt96132reg.h	118;"	d
SCS_0_SIZE	dev/mv64340reg.h	150;"	d
SCS_1_0_ADDRESS_REMAP	dev/gt96132reg.h	103;"	d
SCS_1_0_HIGH_DECODE_ADDRESS	dev/gt96132reg.h	79;"	d
SCS_1_0_LOW_DECODE_ADDRESS	dev/gt96132reg.h	78;"	d
SCS_1_BASE_ADDRESS	dev/mv64340reg.h	151;"	d
SCS_1_HIGH_DECODE_ADDRESS	dev/gt64240reg.h	148;"	d
SCS_1_HIGH_DECODE_ADDRESS	dev/gt64260reg.h	139;"	d
SCS_1_HIGH_DECODE_ADDRESS	dev/gt96132reg.h	121;"	d
SCS_1_LOW_DECODE_ADDRESS	dev/gt64240reg.h	147;"	d
SCS_1_LOW_DECODE_ADDRESS	dev/gt64260reg.h	138;"	d
SCS_1_LOW_DECODE_ADDRESS	dev/gt96132reg.h	120;"	d
SCS_1_SIZE	dev/mv64340reg.h	152;"	d
SCS_2_BASE_ADDRESS	dev/mv64340reg.h	153;"	d
SCS_2_HIGH_DECODE_ADDRESS	dev/gt64240reg.h	150;"	d
SCS_2_HIGH_DECODE_ADDRESS	dev/gt64260reg.h	141;"	d
SCS_2_HIGH_DECODE_ADDRESS	dev/gt96132reg.h	123;"	d
SCS_2_LOW_DECODE_ADDRESS	dev/gt64240reg.h	149;"	d
SCS_2_LOW_DECODE_ADDRESS	dev/gt64260reg.h	140;"	d
SCS_2_LOW_DECODE_ADDRESS	dev/gt96132reg.h	122;"	d
SCS_2_SIZE	dev/mv64340reg.h	154;"	d
SCS_3_2_ADDRESS_REMAP	dev/gt96132reg.h	104;"	d
SCS_3_2_HIGH_DECODE_ADDRESS	dev/gt96132reg.h	81;"	d
SCS_3_2_LOW_DECODE_ADDRESS	dev/gt96132reg.h	80;"	d
SCS_3_BASE_ADDRESS	dev/mv64340reg.h	155;"	d
SCS_3_HIGH_DECODE_ADDRESS	dev/gt64240reg.h	152;"	d
SCS_3_HIGH_DECODE_ADDRESS	dev/gt64260reg.h	143;"	d
SCS_3_HIGH_DECODE_ADDRESS	dev/gt96132reg.h	125;"	d
SCS_3_LOW_DECODE_ADDRESS	dev/gt64240reg.h	151;"	d
SCS_3_LOW_DECODE_ADDRESS	dev/gt64260reg.h	142;"	d
SCS_3_LOW_DECODE_ADDRESS	dev/gt96132reg.h	124;"	d
SCS_3_SIZE	dev/mv64340reg.h	156;"	d
SDMA_CAUSE	dev/gt64240reg.h	1177;"	d
SDMA_CAUSE	dev/gt64260reg.h	1168;"	d
SDMA_CAUSE	dev/gt64420reg.h	913;"	d
SDMA_CAUSE	dev/mv64340reg.h	1027;"	d
SDMA_CAUSE_REG	dev/gt64420reg.h	1037;"	d
SDMA_CAUSE_REG	dev/mv64360reg.h	908;"	d
SDMA_CAUSE_REGISTER	dev/gt96132reg.h	298;"	d
SDMA_COMMAND_REG	dev/gt64420reg.h	1032;"	d
SDMA_COMMAND_REG	dev/mv64360reg.h	903;"	d
SDMA_CONFIG_REG	dev/gt64420reg.h	1031;"	d
SDMA_CONFIG_REG	dev/mv64360reg.h	902;"	d
SDMA_CURRENT_RX_DESCRIPTOR_POINTER	dev/gt64420reg.h	1033;"	d
SDMA_CURRENT_RX_DESCRIPTOR_POINTER	dev/mv64360reg.h	904;"	d
SDMA_CURRENT_TX_DESCRIPTOR_POINTER	dev/gt64420reg.h	1034;"	d
SDMA_CURRENT_TX_DESCRIPTOR_POINTER	dev/mv64360reg.h	905;"	d
SDMA_FIRST_TX_DESCRIPTOR_POINTER	dev/gt64420reg.h	1035;"	d
SDMA_FIRST_TX_DESCRIPTOR_POINTER	dev/mv64360reg.h	906;"	d
SDMA_G0_CHAN0_1ST_TX_DESC_PTR	dev/gt96132reg.h	493;"	d
SDMA_G0_CHAN0_COMM_REG	dev/gt96132reg.h	488;"	d
SDMA_G0_CHAN0_CONFIG_REG	dev/gt96132reg.h	487;"	d
SDMA_G0_CHAN0_CURR_RX_DESC_PTR	dev/gt96132reg.h	490;"	d
SDMA_G0_CHAN0_CURR_TX_DESC_PTR	dev/gt96132reg.h	492;"	d
SDMA_G0_CHAN0_RX_DESC_BASE	dev/gt96132reg.h	489;"	d
SDMA_G0_CHAN0_TX_DESC_BASE	dev/gt96132reg.h	491;"	d
SDMA_G0_CHAN1_1ST_TX_DESC_PTR	dev/gt96132reg.h	500;"	d
SDMA_G0_CHAN1_COMM_REG	dev/gt96132reg.h	495;"	d
SDMA_G0_CHAN1_CONFIG_REG	dev/gt96132reg.h	494;"	d
SDMA_G0_CHAN1_CURR_RX_DESC_PTR	dev/gt96132reg.h	497;"	d
SDMA_G0_CHAN1_CURR_TX_DESC_PTR	dev/gt96132reg.h	499;"	d
SDMA_G0_CHAN1_RX_DESC_BASE	dev/gt96132reg.h	496;"	d
SDMA_G0_CHAN1_TX_DESC_BASE	dev/gt96132reg.h	498;"	d
SDMA_G0_CHAN2_1ST_TX_DESC_PTR	dev/gt96132reg.h	507;"	d
SDMA_G0_CHAN2_COMM_REG	dev/gt96132reg.h	502;"	d
SDMA_G0_CHAN2_CONFIG_REG	dev/gt96132reg.h	501;"	d
SDMA_G0_CHAN2_CURR_RX_DESC_PTR	dev/gt96132reg.h	504;"	d
SDMA_G0_CHAN2_CURR_TX_DESC_PTR	dev/gt96132reg.h	506;"	d
SDMA_G0_CHAN2_RX_DESC_BASE	dev/gt96132reg.h	503;"	d
SDMA_G0_CHAN2_TX_DESC_BASE	dev/gt96132reg.h	505;"	d
SDMA_G0_CHAN3_1ST_TX_DESC_PTR	dev/gt96132reg.h	514;"	d
SDMA_G0_CHAN3_COMM_REG	dev/gt96132reg.h	509;"	d
SDMA_G0_CHAN3_CONFIG_REG	dev/gt96132reg.h	508;"	d
SDMA_G0_CHAN3_CURR_RX_DESC_PTR	dev/gt96132reg.h	511;"	d
SDMA_G0_CHAN3_CURR_TX_DESC_PTR	dev/gt96132reg.h	513;"	d
SDMA_G0_CHAN3_RX_DESC_BASE	dev/gt96132reg.h	510;"	d
SDMA_G0_CHAN3_TX_DESC_BASE	dev/gt96132reg.h	512;"	d
SDMA_G0_CHAN4_1ST_TX_DESC_PTR	dev/gt96132reg.h	521;"	d
SDMA_G0_CHAN4_COMM_REG	dev/gt96132reg.h	516;"	d
SDMA_G0_CHAN4_CONFIG_REG	dev/gt96132reg.h	515;"	d
SDMA_G0_CHAN4_CURR_RX_DESC_PTR	dev/gt96132reg.h	518;"	d
SDMA_G0_CHAN4_CURR_TX_DESC_PTR	dev/gt96132reg.h	520;"	d
SDMA_G0_CHAN4_RX_DESC_BASE	dev/gt96132reg.h	517;"	d
SDMA_G0_CHAN4_TX_DESC_BASE	dev/gt96132reg.h	519;"	d
SDMA_G0_CHAN5_1ST_TX_DESC_PTR	dev/gt96132reg.h	528;"	d
SDMA_G0_CHAN5_COMM_REG	dev/gt96132reg.h	523;"	d
SDMA_G0_CHAN5_CONFIG_REG	dev/gt96132reg.h	522;"	d
SDMA_G0_CHAN5_CURR_RX_DESC_PTR	dev/gt96132reg.h	525;"	d
SDMA_G0_CHAN5_CURR_TX_DESC_PTR	dev/gt96132reg.h	527;"	d
SDMA_G0_CHAN5_RX_DESC_BASE	dev/gt96132reg.h	524;"	d
SDMA_G0_CHAN5_TX_DESC_BASE	dev/gt96132reg.h	526;"	d
SDMA_G0_CHAN6_1ST_TX_DESC_PTR	dev/gt96132reg.h	535;"	d
SDMA_G0_CHAN6_COMM_REG	dev/gt96132reg.h	530;"	d
SDMA_G0_CHAN6_CONFIG_REG	dev/gt96132reg.h	529;"	d
SDMA_G0_CHAN6_CURR_RX_DESC_PTR	dev/gt96132reg.h	532;"	d
SDMA_G0_CHAN6_CURR_TX_DESC_PTR	dev/gt96132reg.h	534;"	d
SDMA_G0_CHAN6_RX_DESC_BASE	dev/gt96132reg.h	531;"	d
SDMA_G0_CHAN6_TX_DESC_BASE	dev/gt96132reg.h	533;"	d
SDMA_G0_CHAN7_1ST_TX_DESC_PTR	dev/gt96132reg.h	542;"	d
SDMA_G0_CHAN7_COMM_REG	dev/gt96132reg.h	537;"	d
SDMA_G0_CHAN7_CONFIG_REG	dev/gt96132reg.h	536;"	d
SDMA_G0_CHAN7_CURR_RX_DESC_PTR	dev/gt96132reg.h	539;"	d
SDMA_G0_CHAN7_CURR_TX_DESC_PTR	dev/gt96132reg.h	541;"	d
SDMA_G0_CHAN7_RX_DESC_BASE	dev/gt96132reg.h	538;"	d
SDMA_G0_CHAN7_TX_DESC_BASE	dev/gt96132reg.h	540;"	d
SDMA_G1_CHAN0_1ST_TX_DESC_PTR	dev/gt96132reg.h	550;"	d
SDMA_G1_CHAN0_COMM_REG	dev/gt96132reg.h	545;"	d
SDMA_G1_CHAN0_CONFIG_REG	dev/gt96132reg.h	544;"	d
SDMA_G1_CHAN0_CURR_RX_DESC_PTR	dev/gt96132reg.h	547;"	d
SDMA_G1_CHAN0_CURR_TX_DESC_PTR	dev/gt96132reg.h	549;"	d
SDMA_G1_CHAN0_RX_DESC_BASE	dev/gt96132reg.h	546;"	d
SDMA_G1_CHAN0_TX_DESC_BASE	dev/gt96132reg.h	548;"	d
SDMA_G1_CHAN1_1ST_TX_DESC_PTR	dev/gt96132reg.h	557;"	d
SDMA_G1_CHAN1_COMM_REG	dev/gt96132reg.h	552;"	d
SDMA_G1_CHAN1_CONFIG_REG	dev/gt96132reg.h	551;"	d
SDMA_G1_CHAN1_CURR_RX_DESC_PTR	dev/gt96132reg.h	554;"	d
SDMA_G1_CHAN1_CURR_TX_DESC_PTR	dev/gt96132reg.h	556;"	d
SDMA_G1_CHAN1_RX_DESC_BASE	dev/gt96132reg.h	553;"	d
SDMA_G1_CHAN1_TX_DESC_BASE	dev/gt96132reg.h	555;"	d
SDMA_G1_CHAN2_1ST_TX_DESC_PTR	dev/gt96132reg.h	564;"	d
SDMA_G1_CHAN2_COMM_REG	dev/gt96132reg.h	559;"	d
SDMA_G1_CHAN2_CONFIG_REG	dev/gt96132reg.h	558;"	d
SDMA_G1_CHAN2_CURR_RX_DESC_PTR	dev/gt96132reg.h	561;"	d
SDMA_G1_CHAN2_CURR_TX_DESC_PTR	dev/gt96132reg.h	563;"	d
SDMA_G1_CHAN2_RX_DESC_BASE	dev/gt96132reg.h	560;"	d
SDMA_G1_CHAN2_TX_DESC_BASE	dev/gt96132reg.h	562;"	d
SDMA_G1_CHAN3_1ST_TX_DESC_PTR	dev/gt96132reg.h	571;"	d
SDMA_G1_CHAN3_COMM_REG	dev/gt96132reg.h	566;"	d
SDMA_G1_CHAN3_CONFIG_REG	dev/gt96132reg.h	565;"	d
SDMA_G1_CHAN3_CURR_RX_DESC_PTR	dev/gt96132reg.h	568;"	d
SDMA_G1_CHAN3_CURR_TX_DESC_PTR	dev/gt96132reg.h	570;"	d
SDMA_G1_CHAN3_RX_DESC_BASE	dev/gt96132reg.h	567;"	d
SDMA_G1_CHAN3_TX_DESC_BASE	dev/gt96132reg.h	569;"	d
SDMA_G1_CHAN4_1ST_TX_DESC_PTR	dev/gt96132reg.h	578;"	d
SDMA_G1_CHAN4_COMM_REG	dev/gt96132reg.h	573;"	d
SDMA_G1_CHAN4_CONFIG_REG	dev/gt96132reg.h	572;"	d
SDMA_G1_CHAN4_CURR_RX_DESC_PTR	dev/gt96132reg.h	575;"	d
SDMA_G1_CHAN4_CURR_TX_DESC_PTR	dev/gt96132reg.h	577;"	d
SDMA_G1_CHAN4_RX_DESC_BASE	dev/gt96132reg.h	574;"	d
SDMA_G1_CHAN4_TX_DESC_BASE	dev/gt96132reg.h	576;"	d
SDMA_G1_CHAN5_1ST_TX_DESC_PTR	dev/gt96132reg.h	585;"	d
SDMA_G1_CHAN5_COMM_REG	dev/gt96132reg.h	580;"	d
SDMA_G1_CHAN5_CONFIG_REG	dev/gt96132reg.h	579;"	d
SDMA_G1_CHAN5_CURR_RX_DESC_PTR	dev/gt96132reg.h	582;"	d
SDMA_G1_CHAN5_CURR_TX_DESC_PTR	dev/gt96132reg.h	584;"	d
SDMA_G1_CHAN5_RX_DESC_BASE	dev/gt96132reg.h	581;"	d
SDMA_G1_CHAN5_TX_DESC_BASE	dev/gt96132reg.h	583;"	d
SDMA_G1_CHAN6_1ST_TX_DESC_PTR	dev/gt96132reg.h	592;"	d
SDMA_G1_CHAN6_COMM_REG	dev/gt96132reg.h	587;"	d
SDMA_G1_CHAN6_CONFIG_REG	dev/gt96132reg.h	586;"	d
SDMA_G1_CHAN6_CURR_RX_DESC_PTR	dev/gt96132reg.h	589;"	d
SDMA_G1_CHAN6_CURR_TX_DESC_PTR	dev/gt96132reg.h	591;"	d
SDMA_G1_CHAN6_RX_DESC_BASE	dev/gt96132reg.h	588;"	d
SDMA_G1_CHAN6_TX_DESC_BASE	dev/gt96132reg.h	590;"	d
SDMA_G1_CHAN7_1ST_TX_DESC_PTR	dev/gt96132reg.h	599;"	d
SDMA_G1_CHAN7_COMM_REG	dev/gt96132reg.h	594;"	d
SDMA_G1_CHAN7_CONFIG_REG	dev/gt96132reg.h	593;"	d
SDMA_G1_CHAN7_CURR_RX_DESC_PTR	dev/gt96132reg.h	596;"	d
SDMA_G1_CHAN7_CURR_TX_DESC_PTR	dev/gt96132reg.h	598;"	d
SDMA_G1_CHAN7_RX_DESC_BASE	dev/gt96132reg.h	595;"	d
SDMA_G1_CHAN7_TX_DESC_BASE	dev/gt96132reg.h	597;"	d
SDMA_GROUP_CONFIGURATION_REGISTER	dev/gt64240reg.h	1133;"	d
SDMA_GROUP_CONFIGURATION_REGISTER	dev/gt64260reg.h	1124;"	d
SDMA_GROUP_CONFIGURATION_REGISTER	dev/gt64420reg.h	869;"	d
SDMA_GROUP_CONFIGURATION_REGISTER	dev/mv64340reg.h	983;"	d
SDMA_GROUP_CONFIG_REG	dev/gt96132reg.h	485;"	d
SDMA_MASK	dev/gt64240reg.h	1178;"	d
SDMA_MASK	dev/gt64260reg.h	1169;"	d
SDMA_MASK	dev/gt64420reg.h	914;"	d
SDMA_MASK	dev/mv64340reg.h	1028;"	d
SDMA_MASK_REG	dev/gt64420reg.h	1038;"	d
SDMA_MASK_REG	dev/mv64360reg.h	909;"	d
SDMA_MASK_REGISTER	dev/gt96132reg.h	299;"	d
SDRAM_ADDRESS_CONTROL	dev/mv64340reg.h	281;"	d
SDRAM_ADDRESS_DECODE	dev/gt64240reg.h	298;"	d
SDRAM_ADDRESS_DECODE	dev/gt64260reg.h	289;"	d
SDRAM_ADDRESS_DECODE	dev/gt64420reg.h	230;"	d
SDRAM_ADDRESS_DECODE	dev/gt96132reg.h	145;"	d
SDRAM_ADDRESS_PADS_CALIBRATION	dev/mv64340reg.h	289;"	d
SDRAM_ADDR_CONTROL	dev/mv64360reg.h	271;"	d
SDRAM_AND_DEVICE_ERROR_ADDRESS	dev/gt64240reg.h	322;"	d
SDRAM_AND_DEVICE_ERROR_ADDRESS	dev/gt64260reg.h	313;"	d
SDRAM_AND_DEVICE_ERROR_ADDRESS	dev/gt64420reg.h	243;"	d
SDRAM_AND_DEVICE_ERROR_ADDRESS	dev/mv64340reg.h	304;"	d
SDRAM_BANK0PARAMETERS	dev/gt64240reg.h	310;"	d
SDRAM_BANK0PARAMETERS	dev/gt64260reg.h	301;"	d
SDRAM_BANK0PARAMETERS	dev/gt96132reg.h	151;"	d
SDRAM_BANK1PARAMETERS	dev/gt64240reg.h	311;"	d
SDRAM_BANK1PARAMETERS	dev/gt64260reg.h	302;"	d
SDRAM_BANK1PARAMETERS	dev/gt96132reg.h	152;"	d
SDRAM_BANK2PARAMETERS	dev/gt64240reg.h	312;"	d
SDRAM_BANK2PARAMETERS	dev/gt64260reg.h	303;"	d
SDRAM_BANK2PARAMETERS	dev/gt96132reg.h	153;"	d
SDRAM_BANK3PARAMETERS	dev/gt64240reg.h	313;"	d
SDRAM_BANK3PARAMETERS	dev/gt64260reg.h	304;"	d
SDRAM_BANK3PARAMETERS	dev/gt96132reg.h	154;"	d
SDRAM_CALCULATED_ECC	dev/gt64240reg.h	324;"	d
SDRAM_CALCULATED_ECC	dev/gt64260reg.h	315;"	d
SDRAM_CALCULATED_ECC	dev/gt64420reg.h	245;"	d
SDRAM_CALCULATED_ECC	dev/mv64340reg.h	306;"	d
SDRAM_CALCULATED_ECC	dev/mv64360reg.h	290;"	d
SDRAM_CNFG	dev/gt64240reg.h	92;"	d
SDRAM_CNFG	dev/gt64260reg.h	83;"	d
SDRAM_CNFG	dev/gt64420reg.h	94;"	d
SDRAM_CNFG	dev/mv64340reg.h	92;"	d
SDRAM_CONFIG	dev/mv64360reg.h	266;"	d
SDRAM_CONFIGURATION	dev/gt64240reg.h	296;"	d
SDRAM_CONFIGURATION	dev/gt64260reg.h	287;"	d
SDRAM_CONFIGURATION	dev/gt64420reg.h	228;"	d
SDRAM_CONFIGURATION	dev/gt96132reg.h	143;"	d
SDRAM_CONFIGURATION	dev/mv64340reg.h	276;"	d
SDRAM_CROSSBAR_CONTROL_HIGH	dev/mv64340reg.h	287;"	d
SDRAM_CROSSBAR_CONTROL_LOW	dev/mv64340reg.h	286;"	d
SDRAM_CROSSBAR_TIMEOUT	dev/mv64340reg.h	288;"	d
SDRAM_CROSS_BAR_CONTROL_HIGH	dev/gt64240reg.h	301;"	d
SDRAM_CROSS_BAR_CONTROL_HIGH	dev/gt64260reg.h	292;"	d
SDRAM_CROSS_BAR_CONTROL_HIGH	dev/gt64420reg.h	232;"	d
SDRAM_CROSS_BAR_CONTROL_HIGH	dev/mv64360reg.h	277;"	d
SDRAM_CROSS_BAR_CONTROL_LOW	dev/gt64240reg.h	300;"	d
SDRAM_CROSS_BAR_CONTROL_LOW	dev/gt64260reg.h	291;"	d
SDRAM_CROSS_BAR_CONTROL_LOW	dev/gt64420reg.h	231;"	d
SDRAM_CROSS_BAR_CONTROL_LOW	dev/mv64360reg.h	276;"	d
SDRAM_CROSS_BAR_TIMEOUT	dev/gt64240reg.h	302;"	d
SDRAM_CROSS_BAR_TIMEOUT	dev/gt64260reg.h	293;"	d
SDRAM_CROSS_BAR_TIMEOUT	dev/gt64420reg.h	233;"	d
SDRAM_CROSS_BAR_TIMEOUT	dev/mv64360reg.h	278;"	d
SDRAM_DATA_PADS_CALIBRATION	dev/mv64340reg.h	290;"	d
SDRAM_DATA_PADS_CALIBRATION	dev/mv64360reg.h	280;"	d
SDRAM_ECC_CONTROL	dev/gt64240reg.h	325;"	d
SDRAM_ECC_CONTROL	dev/gt64260reg.h	316;"	d
SDRAM_ECC_CONTROL	dev/gt64420reg.h	246;"	d
SDRAM_ECC_CONTROL	dev/mv64340reg.h	307;"	d
SDRAM_ECC_CONTROL	dev/mv64360reg.h	291;"	d
SDRAM_ECC_ERROR_COUNTER	dev/gt64240reg.h	326;"	d
SDRAM_ECC_ERROR_COUNTER	dev/gt64260reg.h	317;"	d
SDRAM_ECC_ERROR_COUNTER	dev/mv64340reg.h	308;"	d
SDRAM_ECC_ERROR_COUNTER	dev/mv64360reg.h	292;"	d
SDRAM_ERROR_ADDR	dev/mv64360reg.h	288;"	d
SDRAM_ERROR_DATA_HIGH	dev/gt64240reg.h	321;"	d
SDRAM_ERROR_DATA_HIGH	dev/gt64260reg.h	312;"	d
SDRAM_ERROR_DATA_HIGH	dev/gt64420reg.h	242;"	d
SDRAM_ERROR_DATA_HIGH	dev/mv64340reg.h	303;"	d
SDRAM_ERROR_DATA_HIGH	dev/mv64360reg.h	287;"	d
SDRAM_ERROR_DATA_LOW	dev/gt64240reg.h	320;"	d
SDRAM_ERROR_DATA_LOW	dev/gt64260reg.h	311;"	d
SDRAM_ERROR_DATA_LOW	dev/gt64420reg.h	241;"	d
SDRAM_ERROR_DATA_LOW	dev/mv64340reg.h	302;"	d
SDRAM_ERROR_DATA_LOW	dev/mv64360reg.h	286;"	d
SDRAM_MODE	dev/mv64340reg.h	284;"	d
SDRAM_MODE	dev/mv64360reg.h	274;"	d
SDRAM_OPEN_PAGES_CONTROL	dev/mv64340reg.h	282;"	d
SDRAM_OPEN_PAGES_CONTROL	dev/mv64360reg.h	272;"	d
SDRAM_OPERATION	dev/mv64340reg.h	283;"	d
SDRAM_OPERATION	dev/mv64360reg.h	273;"	d
SDRAM_OPERATION_MODE	dev/gt64240reg.h	297;"	d
SDRAM_OPERATION_MODE	dev/gt64260reg.h	288;"	d
SDRAM_OPERATION_MODE	dev/gt64420reg.h	229;"	d
SDRAM_OPERATION_MODE	dev/gt96132reg.h	144;"	d
SDRAM_PARA0	dev/gt64240reg.h	93;"	d
SDRAM_PARA0	dev/gt64260reg.h	84;"	d
SDRAM_PARA0	dev/mv64340reg.h	93;"	d
SDRAM_PARA1	dev/gt64240reg.h	94;"	d
SDRAM_PARA1	dev/gt64260reg.h	85;"	d
SDRAM_PARA1	dev/mv64340reg.h	94;"	d
SDRAM_PARA2	dev/gt64240reg.h	95;"	d
SDRAM_PARA2	dev/gt64260reg.h	86;"	d
SDRAM_PARA2	dev/mv64340reg.h	95;"	d
SDRAM_PARA3	dev/gt64240reg.h	96;"	d
SDRAM_PARA3	dev/gt64260reg.h	87;"	d
SDRAM_PARA3	dev/mv64340reg.h	96;"	d
SDRAM_RECEIVED_ECC	dev/gt64240reg.h	323;"	d
SDRAM_RECEIVED_ECC	dev/gt64260reg.h	314;"	d
SDRAM_RECEIVED_ECC	dev/gt64420reg.h	244;"	d
SDRAM_RECEIVED_ECC	dev/mv64340reg.h	305;"	d
SDRAM_RECEIVED_ECC	dev/mv64360reg.h	289;"	d
SDRAM_TIMING_CONTROL_HIGH	dev/mv64360reg.h	270;"	d
SDRAM_TIMING_CONTROL_LOW	dev/mv64360reg.h	269;"	d
SDRAM_TIMING_HIGH	dev/gt64420reg.h	235;"	d
SDRAM_TIMING_HIGH	dev/mv64340reg.h	280;"	d
SDRAM_TIMING_LOW	dev/gt64420reg.h	234;"	d
SDRAM_TIMING_LOW	dev/mv64340reg.h	279;"	d
SDRAM_TIMING_PARAMETERS	dev/gt64240reg.h	303;"	d
SDRAM_TIMING_PARAMETERS	dev/gt64260reg.h	294;"	d
SDRAM_UMA_CONTROL	dev/gt64240reg.h	299;"	d
SDRAM_UMA_CONTROL	dev/gt64260reg.h	290;"	d
SDRAM_XTENDED_MODE	dev/mv64340reg.h	285;"	d
SE	include/arpa/telnet.h	60;"	d
SEGSIZE	include/arpa/tftp.h	45;"	d
SELECT_CAUSE_REGISTER	dev/gt64420reg.h	611;"	d
SEND_ESC_SEQ	dev/kbd.c	182;"	d	file:
SERIAL_CAUSE_REGISTER	dev/gt96132reg.h	291;"	d
SERIAL_INIT_CONTROL	dev/mv64360reg.h	1092;"	d
SERIAL_INIT_LAST_DATA	dev/gt64240reg.h	1019;"	d
SERIAL_INIT_LAST_DATA	dev/gt64260reg.h	1010;"	d
SERIAL_INIT_LAST_DATA	dev/mv64340reg.h	958;"	d
SERIAL_INIT_LAST_DATA	dev/mv64360reg.h	1091;"	d
SERIAL_INIT_PCI_HIGH_ADDRESS	dev/gt64240reg.h	1018;"	d
SERIAL_INIT_PCI_HIGH_ADDRESS	dev/gt64260reg.h	1009;"	d
SERIAL_INIT_PCI_HIGH_ADDRESS	dev/mv64340reg.h	957;"	d
SERIAL_INIT_STATUS	dev/mv64360reg.h	1093;"	d
SERIAL_INIT_STATUS_AND_CONTROL	dev/gt64240reg.h	1020;"	d
SERIAL_INIT_STATUS_AND_CONTROL	dev/gt64260reg.h	1011;"	d
SERIAL_INIT_STATUS_AND_CONTROL	dev/mv64340reg.h	959;"	d
SERIAL_PORT_MULTIPLEX	dev/gt64240reg.h	1250;"	d
SERIAL_PORT_MULTIPLEX	dev/gt64260reg.h	1241;"	d
SERIAL_PORT_MULTIPLEX	dev/gt64420reg.h	986;"	d
SERINT0_MASK_REGISTER	dev/gt96132reg.h	292;"	d
SERINT1_MASK_REGISTER	dev/gt96132reg.h	293;"	d
SERVFAIL	include/arpa/nameser.h	143;"	d
SER_PORTS_MUX	dev/gt64240reg.h	137;"	d
SER_PORTS_MUX	dev/gt64260reg.h	128;"	d
SER_PORTS_MUX	dev/gt64420reg.h	121;"	d
SER_PORTS_MUX	dev/mv64340reg.h	137;"	d
SETINTR	include/termio.h	11;"	d
SETNCNE	include/termio.h	16;"	d
SETSANE	include/termio.h	12;"	d
SETTERM	include/termio.h	15;"	d
SETWIDE	dev/flash.c	56;"	d	file:
SETWIDE	dev/flash_amd.c	71;"	d	file:
SETWIDE	dev/flash_int.c	72;"	d	file:
SETWIDE	dev/flash_sst.c	72;"	d	file:
SETWIDE	dev/flash_st.c	69;"	d	file:
SETWIDE	dev/flash_winbond.c	72;"	d	file:
SIGALRM	include/ri.h	244;"	d
SIGBUS	include/ri.h	240;"	d
SIGCLD	include/ri.h	246;"	d
SIGEMT	include/ri.h	237;"	d
SIGFPE	include/ri.h	238;"	d
SIGHUP	include/ri.h	232;"	d
SIGILL	include/ri.h	235;"	d
SIGINT	include/ri.h	233;"	d
SIGKILL	include/ri.h	239;"	d
SIGPIPE	include/ri.h	243;"	d
SIGPOLL	include/ri.h	248;"	d
SIGPWR	include/ri.h	247;"	d
SIGQUIT	include/ri.h	234;"	d
SIGSEGV	include/ri.h	241;"	d
SIGSYS	include/ri.h	242;"	d
SIGTERM	include/ri.h	245;"	d
SIGTRAP	include/ri.h	236;"	d
SLC_ABORT	include/arpa/telnet.h	191;"	d
SLC_ACK	include/arpa/telnet.h	252;"	d
SLC_AO	include/arpa/telnet.h	188;"	d
SLC_AYT	include/arpa/telnet.h	189;"	d
SLC_BRK	include/arpa/telnet.h	186;"	d
SLC_CANTCHANGE	include/arpa/telnet.h	243;"	d
SLC_DEFAULT	include/arpa/telnet.h	245;"	d
SLC_EBOL	include/arpa/telnet.h	213;"	d
SLC_EC	include/arpa/telnet.h	194;"	d
SLC_ECR	include/arpa/telnet.h	211;"	d
SLC_EEOL	include/arpa/telnet.h	214;"	d
SLC_EL	include/arpa/telnet.h	195;"	d
SLC_EOF	include/arpa/telnet.h	192;"	d
SLC_EOR	include/arpa/telnet.h	190;"	d
SLC_EW	include/arpa/telnet.h	196;"	d
SLC_EWR	include/arpa/telnet.h	212;"	d
SLC_FLAGS	include/arpa/telnet.h	249;"	d
SLC_FLUSHIN	include/arpa/telnet.h	253;"	d
SLC_FLUSHOUT	include/arpa/telnet.h	254;"	d
SLC_FORW1	include/arpa/telnet.h	201;"	d
SLC_FORW2	include/arpa/telnet.h	202;"	d
SLC_FUNC	include/arpa/telnet.h	248;"	d
SLC_INSRT	include/arpa/telnet.h	209;"	d
SLC_IP	include/arpa/telnet.h	187;"	d
SLC_LEVELBITS	include/arpa/telnet.h	246;"	d
SLC_LNEXT	include/arpa/telnet.h	198;"	d
SLC_MCBOL	include/arpa/telnet.h	207;"	d
SLC_MCEOL	include/arpa/telnet.h	208;"	d
SLC_MCL	include/arpa/telnet.h	203;"	d
SLC_MCR	include/arpa/telnet.h	204;"	d
SLC_MCWL	include/arpa/telnet.h	205;"	d
SLC_MCWR	include/arpa/telnet.h	206;"	d
SLC_NAME	include/arpa/telnet.h	240;"	d
SLC_NAMELIST	include/arpa/telnet.h	222;"	d
SLC_NAMES	include/arpa/telnet.h	236;"	d
SLC_NAME_OK	include/arpa/telnet.h	239;"	d
SLC_NOSUPPORT	include/arpa/telnet.h	242;"	d
SLC_OVER	include/arpa/telnet.h	210;"	d
SLC_RP	include/arpa/telnet.h	197;"	d
SLC_SUSP	include/arpa/telnet.h	193;"	d
SLC_SYNCH	include/arpa/telnet.h	185;"	d
SLC_VALUE	include/arpa/telnet.h	250;"	d
SLC_VARIABLE	include/arpa/telnet.h	244;"	d
SLC_XOFF	include/arpa/telnet.h	200;"	d
SLC_XON	include/arpa/telnet.h	199;"	d
SLOW_DOWN_IO	include/tgt/io.h	9;"	d
SMP_CPU0_DOORBELL	dev/mv64360reg.h	189;"	d
SMP_CPU0_DOORBELL_CLEAR	dev/mv64360reg.h	190;"	d
SMP_CPU0_DOORBELL_MASK	dev/mv64360reg.h	193;"	d
SMP_CPU1_DOORBELL	dev/mv64360reg.h	191;"	d
SMP_CPU1_DOORBELL_CLEAR	dev/mv64360reg.h	192;"	d
SMP_CPU1_DOORBELL_MASK	dev/mv64360reg.h	194;"	d
SMP_SEMAPHOR0	dev/mv64360reg.h	195;"	d
SMP_SEMAPHOR1	dev/mv64360reg.h	196;"	d
SMP_SEMAPHOR2	dev/mv64360reg.h	197;"	d
SMP_SEMAPHOR3	dev/mv64360reg.h	198;"	d
SMP_SEMAPHOR4	dev/mv64360reg.h	199;"	d
SMP_SEMAPHOR5	dev/mv64360reg.h	200;"	d
SMP_SEMAPHOR6	dev/mv64360reg.h	201;"	d
SMP_SEMAPHOR7	dev/mv64360reg.h	202;"	d
SMP_WHO_AM_I	dev/mv64360reg.h	188;"	d
SNOOP_BASE_ADDRESS_0	dev/gt64240reg.h	250;"	d
SNOOP_BASE_ADDRESS_0	dev/gt64260reg.h	241;"	d
SNOOP_BASE_ADDRESS_1	dev/gt64240reg.h	252;"	d
SNOOP_BASE_ADDRESS_1	dev/gt64260reg.h	243;"	d
SNOOP_BASE_ADDRESS_2	dev/gt64240reg.h	254;"	d
SNOOP_BASE_ADDRESS_2	dev/gt64260reg.h	245;"	d
SNOOP_BASE_ADDRESS_3	dev/gt64240reg.h	256;"	d
SNOOP_BASE_ADDRESS_3	dev/gt64260reg.h	247;"	d
SNOOP_TOP_ADDRESS_0	dev/gt64240reg.h	251;"	d
SNOOP_TOP_ADDRESS_0	dev/gt64260reg.h	242;"	d
SNOOP_TOP_ADDRESS_1	dev/gt64240reg.h	253;"	d
SNOOP_TOP_ADDRESS_1	dev/gt64260reg.h	244;"	d
SNOOP_TOP_ADDRESS_2	dev/gt64240reg.h	255;"	d
SNOOP_TOP_ADDRESS_2	dev/gt64260reg.h	246;"	d
SNOOP_TOP_ADDRESS_3	dev/gt64240reg.h	257;"	d
SNOOP_TOP_ADDRESS_3	dev/gt64260reg.h	248;"	d
SPRG0	include/powerpc.h	40;"	d
SPRG1	include/powerpc.h	41;"	d
SPRG2	include/powerpc.h	42;"	d
SPRG3	include/powerpc.h	43;"	d
SRAM_ADDR	dev/mv64360reg.h	302;"	d
SRAM_ADDRESS	dev/mv64340reg.h	294;"	d
SRAM_CONFIG	dev/mv64360reg.h	253;"	d
SRAM_DATA0	dev/mv64340reg.h	295;"	d
SRAM_DATA0	dev/mv64360reg.h	303;"	d
SRAM_DATA1	dev/mv64360reg.h	304;"	d
SRAM_DATA2	dev/mv64360reg.h	305;"	d
SRAM_ERROR_ADDR	dev/mv64360reg.h	256;"	d
SRAM_ERROR_ADDR_HIGH	dev/mv64360reg.h	257;"	d
SRAM_ERROR_CAUSE	dev/mv64360reg.h	255;"	d
SRAM_ERROR_DATA_HIGH	dev/mv64360reg.h	259;"	d
SRAM_ERROR_DATA_LOW	dev/mv64360reg.h	258;"	d
SRAM_ERROR_DATA_PARITY	dev/mv64360reg.h	260;"	d
SRAM_TEST_MODE	dev/mv64360reg.h	254;"	d
SST_CMDOFFS	include/pflash.h	122;"	d
SST_CMDOFFS1	include/pflash.h	123;"	d
SST_CMDOFFS2	include/pflash.h	124;"	d
STATIC_TREES	include/linux/zutil.h	47;"	d
STATUS	include/arpa/nameser.h	135;"	d
STDC	include/linux/zconf.h	19;"	d
STDERR	include/termio.h	85;"	d
STDERR_FILENO	include/unistd.h	48;"	d
STDIN	include/termio.h	83;"	d
STDIN_FILENO	include/unistd.h	46;"	d
STDOUT	include/termio.h	84;"	d
STDOUT_FILENO	include/unistd.h	47;"	d
STOPMAX	include/debugger.h	37;"	d
STORED_BLOCK	include/linux/zutil.h	46;"	d
STRU_F	include/arpa/ftp.h	78;"	d
STRU_P	include/arpa/ftp.h	80;"	d
STRU_R	include/arpa/ftp.h	79;"	d
SUSP	include/arpa/telnet.h	63;"	d
SYNCH	include/arpa/telnet.h	66;"	d
Stopentry	include/pmon.h	/^typedef struct Stopentry {$/;"	s
Stopentry	include/pmon.h	/^} Stopentry;$/;"	t	typeref:struct:Stopentry
TARGET_FLASH_DEVICES_8	include/tgt/pflash_tgt.h	50;"	d
TCGETA	include/termio.h	8;"	d
TCSETAF	include/termio.h	9;"	d
TCSETAW	include/termio.h	10;"	d
TELCMD	include/arpa/telnet.h	83;"	d
TELCMD_FIRST	include/arpa/telnet.h	79;"	d
TELCMD_LAST	include/arpa/telnet.h	80;"	d
TELCMD_OK	include/arpa/telnet.h	81;"	d
TELOPT	include/arpa/telnet.h	147;"	d
TELOPT_3270REGIME	include/arpa/telnet.h	115;"	d
TELOPT_AUTHENTICATION	include/arpa/telnet.h	123;"	d
TELOPT_BINARY	include/arpa/telnet.h	86;"	d
TELOPT_BM	include/arpa/telnet.h	105;"	d
TELOPT_DET	include/arpa/telnet.h	106;"	d
TELOPT_ECHO	include/arpa/telnet.h	87;"	d
TELOPT_ENCRYPT	include/arpa/telnet.h	124;"	d
TELOPT_EOR	include/arpa/telnet.h	111;"	d
TELOPT_EXOPL	include/arpa/telnet.h	126;"	d
TELOPT_FIRST	include/arpa/telnet.h	144;"	d
TELOPT_LAST	include/arpa/telnet.h	145;"	d
TELOPT_LFLOW	include/arpa/telnet.h	119;"	d
TELOPT_LINEMODE	include/arpa/telnet.h	120;"	d
TELOPT_LOGOUT	include/arpa/telnet.h	104;"	d
TELOPT_NAMS	include/arpa/telnet.h	90;"	d
TELOPT_NAOCRD	include/arpa/telnet.h	96;"	d
TELOPT_NAOFFD	include/arpa/telnet.h	99;"	d
TELOPT_NAOHTD	include/arpa/telnet.h	98;"	d
TELOPT_NAOHTS	include/arpa/telnet.h	97;"	d
TELOPT_NAOL	include/arpa/telnet.h	94;"	d
TELOPT_NAOLFD	include/arpa/telnet.h	102;"	d
TELOPT_NAOP	include/arpa/telnet.h	95;"	d
TELOPT_NAOVTD	include/arpa/telnet.h	101;"	d
TELOPT_NAOVTS	include/arpa/telnet.h	100;"	d
TELOPT_NAWS	include/arpa/telnet.h	117;"	d
TELOPT_NEW_ENVIRON	include/arpa/telnet.h	125;"	d
TELOPT_OK	include/arpa/telnet.h	146;"	d
TELOPT_OLD_ENVIRON	include/arpa/telnet.h	122;"	d
TELOPT_OUTMRK	include/arpa/telnet.h	113;"	d
TELOPT_RCP	include/arpa/telnet.h	88;"	d
TELOPT_RCTE	include/arpa/telnet.h	93;"	d
TELOPT_SGA	include/arpa/telnet.h	89;"	d
TELOPT_SNDLOC	include/arpa/telnet.h	109;"	d
TELOPT_STATUS	include/arpa/telnet.h	91;"	d
TELOPT_SUPDUP	include/arpa/telnet.h	107;"	d
TELOPT_SUPDUPOUTPUT	include/arpa/telnet.h	108;"	d
TELOPT_TM	include/arpa/telnet.h	92;"	d
TELOPT_TSPEED	include/arpa/telnet.h	118;"	d
TELOPT_TTYLOC	include/arpa/telnet.h	114;"	d
TELOPT_TTYPE	include/arpa/telnet.h	110;"	d
TELOPT_TUID	include/arpa/telnet.h	112;"	d
TELOPT_X3PAD	include/arpa/telnet.h	116;"	d
TELOPT_XASCII	include/arpa/telnet.h	103;"	d
TELOPT_XDISPLOC	include/arpa/telnet.h	121;"	d
TELQUAL_INFO	include/arpa/telnet.h	153;"	d
TELQUAL_IS	include/arpa/telnet.h	151;"	d
TELQUAL_NAME	include/arpa/telnet.h	155;"	d
TELQUAL_REPLY	include/arpa/telnet.h	154;"	d
TELQUAL_SEND	include/arpa/telnet.h	152;"	d
TERMTYPE	include/termio.h	18;"	d
TIMER_COUNTER0	dev/gt64240reg.h	517;"	d
TIMER_COUNTER0	dev/gt64260reg.h	508;"	d
TIMER_COUNTER0	dev/gt64420reg.h	437;"	d
TIMER_COUNTER0	dev/gt96132reg.h	216;"	d
TIMER_COUNTER0	dev/mv64340reg.h	447;"	d
TIMER_COUNTER0	dev/mv64360reg.h	1016;"	d
TIMER_COUNTER1	dev/gt64240reg.h	518;"	d
TIMER_COUNTER1	dev/gt64260reg.h	509;"	d
TIMER_COUNTER1	dev/gt64420reg.h	438;"	d
TIMER_COUNTER1	dev/gt96132reg.h	217;"	d
TIMER_COUNTER1	dev/mv64340reg.h	448;"	d
TIMER_COUNTER1	dev/mv64360reg.h	1017;"	d
TIMER_COUNTER2	dev/gt64240reg.h	519;"	d
TIMER_COUNTER2	dev/gt64260reg.h	510;"	d
TIMER_COUNTER2	dev/gt64420reg.h	439;"	d
TIMER_COUNTER2	dev/gt96132reg.h	218;"	d
TIMER_COUNTER2	dev/mv64340reg.h	449;"	d
TIMER_COUNTER2	dev/mv64360reg.h	1018;"	d
TIMER_COUNTER3	dev/gt64240reg.h	520;"	d
TIMER_COUNTER3	dev/gt64260reg.h	511;"	d
TIMER_COUNTER3	dev/gt64420reg.h	440;"	d
TIMER_COUNTER3	dev/gt96132reg.h	219;"	d
TIMER_COUNTER3	dev/mv64340reg.h	450;"	d
TIMER_COUNTER3	dev/mv64360reg.h	1019;"	d
TIMER_COUNTER4	dev/gt64240reg.h	524;"	d
TIMER_COUNTER4	dev/gt64260reg.h	515;"	d
TIMER_COUNTER4	dev/gt64420reg.h	444;"	d
TIMER_COUNTER5	dev/gt64240reg.h	525;"	d
TIMER_COUNTER5	dev/gt64260reg.h	516;"	d
TIMER_COUNTER5	dev/gt64420reg.h	445;"	d
TIMER_COUNTER6	dev/gt64240reg.h	526;"	d
TIMER_COUNTER6	dev/gt64260reg.h	517;"	d
TIMER_COUNTER6	dev/gt64420reg.h	446;"	d
TIMER_COUNTER7	dev/gt64240reg.h	527;"	d
TIMER_COUNTER7	dev/gt64260reg.h	518;"	d
TIMER_COUNTER7	dev/gt64420reg.h	447;"	d
TIMER_COUNTER_0_3_CONTROL	dev/gt64240reg.h	521;"	d
TIMER_COUNTER_0_3_CONTROL	dev/gt64260reg.h	512;"	d
TIMER_COUNTER_0_3_CONTROL	dev/gt64420reg.h	441;"	d
TIMER_COUNTER_0_3_CONTROL	dev/mv64340reg.h	451;"	d
TIMER_COUNTER_0_3_CONTROL	dev/mv64360reg.h	1020;"	d
TIMER_COUNTER_0_3_INTERRUPT_CAUSE	dev/gt64240reg.h	522;"	d
TIMER_COUNTER_0_3_INTERRUPT_CAUSE	dev/gt64260reg.h	513;"	d
TIMER_COUNTER_0_3_INTERRUPT_CAUSE	dev/gt64420reg.h	442;"	d
TIMER_COUNTER_0_3_INTERRUPT_CAUSE	dev/mv64340reg.h	452;"	d
TIMER_COUNTER_0_3_INTERRUPT_CAUSE	dev/mv64360reg.h	1021;"	d
TIMER_COUNTER_0_3_INTERRUPT_MASK	dev/gt64240reg.h	523;"	d
TIMER_COUNTER_0_3_INTERRUPT_MASK	dev/gt64260reg.h	514;"	d
TIMER_COUNTER_0_3_INTERRUPT_MASK	dev/gt64420reg.h	443;"	d
TIMER_COUNTER_0_3_INTERRUPT_MASK	dev/mv64340reg.h	453;"	d
TIMER_COUNTER_0_3_INTERRUPT_MASK	dev/mv64360reg.h	1022;"	d
TIMER_COUNTER_4_7_CONTROL	dev/gt64240reg.h	528;"	d
TIMER_COUNTER_4_7_CONTROL	dev/gt64260reg.h	519;"	d
TIMER_COUNTER_4_7_CONTROL	dev/gt64420reg.h	448;"	d
TIMER_COUNTER_4_7_INTERRUPT_CAUSE	dev/gt64240reg.h	529;"	d
TIMER_COUNTER_4_7_INTERRUPT_CAUSE	dev/gt64260reg.h	520;"	d
TIMER_COUNTER_4_7_INTERRUPT_CAUSE	dev/gt64420reg.h	449;"	d
TIMER_COUNTER_4_7_INTERRUPT_MASK	dev/gt64240reg.h	530;"	d
TIMER_COUNTER_4_7_INTERRUPT_MASK	dev/gt64260reg.h	521;"	d
TIMER_COUNTER_4_7_INTERRUPT_MASK	dev/gt64420reg.h	450;"	d
TIMER_COUNTER_CONTROL	dev/gt96132reg.h	220;"	d
TOBCD	dev/mc146818.c	66;"	d	file:
TRACE_DC	include/pmon.h	71;"	d
TRACE_DS	include/pmon.h	72;"	d
TRACE_GB	include/pmon.h	70;"	d
TRACE_NO	include/pmon.h	67;"	d
TRACE_TB	include/pmon.h	68;"	d
TRACE_TG	include/pmon.h	69;"	d
TRACE_TN	include/pmon.h	73;"	d
TRANSIENT	include/arpa/ftp.h	50;"	d
TRANSMIT_CLOCK_ROUTING_REGISTER	dev/gt64240reg.h	1209;"	d
TRANSMIT_CLOCK_ROUTING_REGISTER	dev/gt64260reg.h	1200;"	d
TRANSMIT_CLOCK_ROUTING_REGISTER	dev/gt64420reg.h	945;"	d
TRANSMIT_CLOCK_ROUTING_REGISTER	dev/gt96132reg.h	290;"	d
TRANSMIT_CLOCK_ROUTING_REGISTER	dev/mv64340reg.h	1059;"	d
TRUE	include/tgt/bonito.h	3;"	d
TRY_AGAIN	include/netdb.h	135;"	d
TT_CLR	include/termio.h	89;"	d
TT_CM	include/termio.h	88;"	d
TT_CUROFF	include/termio.h	90;"	d
TT_CURON	include/termio.h	91;"	d
TYPE_A	include/arpa/ftp.h	56;"	d
TYPE_AMD	dev/flash.c	67;"	d	file:
TYPE_E	include/arpa/ftp.h	57;"	d
TYPE_I	include/arpa/ftp.h	58;"	d
TYPE_L	include/arpa/ftp.h	59;"	d
TYPE_SST	dev/flash.c	68;"	d	file:
T_A	include/arpa/nameser.h	151;"	d
T_AAAA	include/arpa/nameser.h	178;"	d
T_AFSDB	include/arpa/nameser.h	168;"	d
T_ANY	include/arpa/nameser.h	196;"	d
T_ATMA	include/arpa/nameser.h	184;"	d
T_AXFR	include/arpa/nameser.h	193;"	d
T_CNAME	include/arpa/nameser.h	155;"	d
T_EID	include/arpa/nameser.h	181;"	d
T_GID	include/arpa/nameser.h	189;"	d
T_GPOS	include/arpa/nameser.h	177;"	d
T_HINFO	include/arpa/nameser.h	163;"	d
T_ISDN	include/arpa/nameser.h	170;"	d
T_IXFR	include/arpa/nameser.h	192;"	d
T_KEY	include/arpa/nameser.h	175;"	d
T_LOC	include/arpa/nameser.h	179;"	d
T_MAILA	include/arpa/nameser.h	195;"	d
T_MAILB	include/arpa/nameser.h	194;"	d
T_MB	include/arpa/nameser.h	157;"	d
T_MD	include/arpa/nameser.h	153;"	d
T_MF	include/arpa/nameser.h	154;"	d
T_MG	include/arpa/nameser.h	158;"	d
T_MINFO	include/arpa/nameser.h	164;"	d
T_MR	include/arpa/nameser.h	159;"	d
T_MX	include/arpa/nameser.h	165;"	d
T_NAPTR	include/arpa/nameser.h	185;"	d
T_NIMLOC	include/arpa/nameser.h	182;"	d
T_NS	include/arpa/nameser.h	152;"	d
T_NSAP	include/arpa/nameser.h	172;"	d
T_NSAP_PTR	include/arpa/nameser.h	173;"	d
T_NULL	include/arpa/nameser.h	160;"	d
T_NXT	include/arpa/nameser.h	180;"	d
T_PTR	include/arpa/nameser.h	162;"	d
T_PX	include/arpa/nameser.h	176;"	d
T_RP	include/arpa/nameser.h	167;"	d
T_RT	include/arpa/nameser.h	171;"	d
T_SIG	include/arpa/nameser.h	174;"	d
T_SOA	include/arpa/nameser.h	156;"	d
T_SRV	include/arpa/nameser.h	183;"	d
T_TXT	include/arpa/nameser.h	166;"	d
T_UID	include/arpa/nameser.h	188;"	d
T_UINFO	include/arpa/nameser.h	187;"	d
T_UNSPEC	include/arpa/nameser.h	190;"	d
T_WKS	include/arpa/nameser.h	161;"	d
T_X25	include/arpa/nameser.h	169;"	d
USERNAMESIZE	include/url.h	40;"	d
Url	include/url.h	/^struct Url {$/;"	s
VA_TO_REG_l	include/ri.h	58;"	d
VEOL	include/termio.h	59;"	d
VEOL2	include/termio.h	60;"	d
VERASE	include/termio.h	58;"	d
VINTR	include/termio.h	57;"	d
VK_CAPS_LOCK	dev/key_defs.h	9;"	d
VK_KP_DEL	dev/key_defs.h	14;"	d
VK_L_ALT	dev/key_defs.h	7;"	d
VK_L_CTRL	dev/key_defs.h	4;"	d
VK_L_SHIFT	dev/key_defs.h	5;"	d
VK_NUM_LOCK	dev/key_defs.h	10;"	d
VK_PAGE_DOWN	dev/key_defs.h	13;"	d
VK_PAGE_UP	dev/key_defs.h	12;"	d
VK_R_SHIFT	dev/key_defs.h	6;"	d
VK_SCROLL_LOCK	dev/key_defs.h	11;"	d
VTSB_BUS	include/tgt/bonito.h	466;"	d
VTSB_DEV	include/tgt/bonito.h	467;"	d
VTSB_IDE_FUNC	include/tgt/bonito.h	469;"	d
VTSB_ISA_FUNC	include/tgt/bonito.h	468;"	d
V_START	include/termio.h	61;"	d
V_STOP	include/termio.h	62;"	d
WATCHDOG_CONFIGURATION_REGISTER	dev/gt64240reg.h	1211;"	d
WATCHDOG_CONFIGURATION_REGISTER	dev/gt64260reg.h	1202;"	d
WATCHDOG_CONFIGURATION_REGISTER	dev/gt64420reg.h	947;"	d
WATCHDOG_CONFIGURATION_REGISTER	dev/mv64340reg.h	1061;"	d
WATCHDOG_CONFIG_REG	dev/mv64360reg.h	1028;"	d
WATCHDOG_VALUE_REG	dev/mv64360reg.h	1029;"	d
WATCHDOG_VALUE_REGISTER	dev/gt64240reg.h	1212;"	d
WATCHDOG_VALUE_REGISTER	dev/gt64260reg.h	1203;"	d
WATCHDOG_VALUE_REGISTER	dev/gt64420reg.h	948;"	d
WATCHDOG_VALUE_REGISTER	dev/mv64340reg.h	1062;"	d
WD_CONFIG_REG	dev/gt96132reg.h	814;"	d
WD_VALUE_REG	dev/gt96132reg.h	815;"	d
WILL	include/arpa/telnet.h	49;"	d
WINBOND_CMDOFFS	include/pflash.h	126;"	d
WINBOND_CMDOFFS1	include/pflash.h	127;"	d
WINBOND_CMDOFFS2	include/pflash.h	128;"	d
WONT	include/arpa/telnet.h	48;"	d
WRITE_BYTE_ENABLE	dev/gt64240reg.h	281;"	d
WRITE_BYTE_ENABLE	dev/gt64260reg.h	272;"	d
WRITE_BYTE_ENABLE	dev/mv64340reg.h	259;"	d
WRITE_DATA_HIGH	dev/gt64240reg.h	280;"	d
WRITE_DATA_HIGH	dev/gt64260reg.h	271;"	d
WRITE_DATA_HIGH	dev/mv64340reg.h	258;"	d
WRITE_DATA_LOW	dev/gt64240reg.h	279;"	d
WRITE_DATA_LOW	dev/gt64260reg.h	270;"	d
WRITE_DATA_LOW	dev/mv64340reg.h	257;"	d
WRQ	include/arpa/tftp.h	51;"	d
X0_ADDRESS	dev/gt64240reg.h	333;"	d
X0_ADDRESS	dev/gt64260reg.h	324;"	d
X0_ADDRESS	dev/gt64420reg.h	253;"	d
X0_ADDRESS	dev/mv64340reg.h	315;"	d
X0_COMMAND_AND_ID	dev/gt64240reg.h	334;"	d
X0_COMMAND_AND_ID	dev/gt64260reg.h	325;"	d
X0_COMMAND_AND_ID	dev/gt64420reg.h	254;"	d
X0_COMMAND_AND_ID	dev/mv64340reg.h	316;"	d
X0_READ_DATA_HIGH	dev/gt64240reg.h	339;"	d
X0_READ_DATA_HIGH	dev/gt64260reg.h	330;"	d
X0_READ_DATA_HIGH	dev/gt64420reg.h	259;"	d
X0_READ_DATA_HIGH	dev/mv64340reg.h	321;"	d
X0_READ_DATA_LOW	dev/gt64240reg.h	338;"	d
X0_READ_DATA_LOW	dev/gt64260reg.h	329;"	d
X0_READ_DATA_LOW	dev/gt64420reg.h	258;"	d
X0_READ_DATA_LOW	dev/mv64340reg.h	320;"	d
X0_READ_ID	dev/gt64240reg.h	340;"	d
X0_READ_ID	dev/gt64260reg.h	331;"	d
X0_READ_ID	dev/gt64420reg.h	260;"	d
X0_READ_ID	dev/mv64340reg.h	322;"	d
X0_SNOOP_ADDRESS	dev/gt64240reg.h	349;"	d
X0_SNOOP_ADDRESS	dev/gt64260reg.h	340;"	d
X0_SNOOP_ADDRESS	dev/gt64420reg.h	269;"	d
X0_SNOOP_ADDRESS	dev/mv64340reg.h	331;"	d
X0_SNOOP_COMMAND	dev/gt64240reg.h	350;"	d
X0_SNOOP_COMMAND	dev/gt64260reg.h	341;"	d
X0_SNOOP_COMMAND	dev/gt64420reg.h	270;"	d
X0_SNOOP_COMMAND	dev/mv64340reg.h	332;"	d
X0_WRITE_BYTE_ENABLE	dev/gt64240reg.h	337;"	d
X0_WRITE_BYTE_ENABLE	dev/gt64260reg.h	328;"	d
X0_WRITE_BYTE_ENABLE	dev/gt64420reg.h	257;"	d
X0_WRITE_BYTE_ENABLE	dev/mv64340reg.h	319;"	d
X0_WRITE_DATA_HIGH	dev/gt64240reg.h	336;"	d
X0_WRITE_DATA_HIGH	dev/gt64260reg.h	327;"	d
X0_WRITE_DATA_HIGH	dev/gt64420reg.h	256;"	d
X0_WRITE_DATA_HIGH	dev/mv64340reg.h	318;"	d
X0_WRITE_DATA_LOW	dev/gt64240reg.h	335;"	d
X0_WRITE_DATA_LOW	dev/gt64260reg.h	326;"	d
X0_WRITE_DATA_LOW	dev/gt64420reg.h	255;"	d
X0_WRITE_DATA_LOW	dev/mv64340reg.h	317;"	d
X1_ADDRESS	dev/gt64240reg.h	341;"	d
X1_ADDRESS	dev/gt64260reg.h	332;"	d
X1_ADDRESS	dev/gt64420reg.h	261;"	d
X1_ADDRESS	dev/mv64340reg.h	323;"	d
X1_COMMAND_AND_ID	dev/gt64240reg.h	342;"	d
X1_COMMAND_AND_ID	dev/gt64260reg.h	333;"	d
X1_COMMAND_AND_ID	dev/gt64420reg.h	262;"	d
X1_COMMAND_AND_ID	dev/mv64340reg.h	324;"	d
X1_READ_DATA_HIGH	dev/gt64240reg.h	347;"	d
X1_READ_DATA_HIGH	dev/gt64260reg.h	338;"	d
X1_READ_DATA_HIGH	dev/gt64420reg.h	267;"	d
X1_READ_DATA_HIGH	dev/mv64340reg.h	329;"	d
X1_READ_DATA_LOW	dev/gt64240reg.h	346;"	d
X1_READ_DATA_LOW	dev/gt64260reg.h	337;"	d
X1_READ_DATA_LOW	dev/gt64420reg.h	266;"	d
X1_READ_DATA_LOW	dev/mv64340reg.h	328;"	d
X1_READ_ID	dev/gt64240reg.h	348;"	d
X1_READ_ID	dev/gt64260reg.h	339;"	d
X1_READ_ID	dev/gt64420reg.h	268;"	d
X1_READ_ID	dev/mv64340reg.h	330;"	d
X1_SNOOP_ADDRESS	dev/gt64240reg.h	351;"	d
X1_SNOOP_ADDRESS	dev/gt64260reg.h	342;"	d
X1_SNOOP_ADDRESS	dev/gt64420reg.h	271;"	d
X1_SNOOP_ADDRESS	dev/mv64340reg.h	333;"	d
X1_SNOOP_COMMAND	dev/gt64240reg.h	352;"	d
X1_SNOOP_COMMAND	dev/gt64260reg.h	343;"	d
X1_SNOOP_COMMAND	dev/gt64420reg.h	272;"	d
X1_SNOOP_COMMAND	dev/mv64340reg.h	334;"	d
X1_WRITE_BYTE_ENABLE	dev/gt64240reg.h	345;"	d
X1_WRITE_BYTE_ENABLE	dev/gt64260reg.h	336;"	d
X1_WRITE_BYTE_ENABLE	dev/gt64420reg.h	265;"	d
X1_WRITE_BYTE_ENABLE	dev/mv64340reg.h	327;"	d
X1_WRITE_DATA_HIGH	dev/gt64240reg.h	344;"	d
X1_WRITE_DATA_HIGH	dev/gt64260reg.h	335;"	d
X1_WRITE_DATA_HIGH	dev/gt64420reg.h	264;"	d
X1_WRITE_DATA_HIGH	dev/mv64340reg.h	326;"	d
X1_WRITE_DATA_LOW	dev/gt64240reg.h	343;"	d
X1_WRITE_DATA_LOW	dev/gt64260reg.h	334;"	d
X1_WRITE_DATA_LOW	dev/gt64420reg.h	263;"	d
X1_WRITE_DATA_LOW	dev/mv64340reg.h	325;"	d
X_0_ADDRESS	dev/gt64240reg.h	275;"	d
X_0_ADDRESS	dev/gt64260reg.h	266;"	d
X_0_ADDRESS	dev/mv64340reg.h	253;"	d
X_0_COMMAND_ID	dev/gt64240reg.h	276;"	d
X_0_COMMAND_ID	dev/gt64260reg.h	267;"	d
X_0_COMMAND_ID	dev/mv64340reg.h	254;"	d
X_1_ADDRESS	dev/gt64240reg.h	277;"	d
X_1_ADDRESS	dev/gt64260reg.h	268;"	d
X_1_ADDRESS	dev/mv64340reg.h	255;"	d
X_1_COMMAND_ID	dev/gt64240reg.h	278;"	d
X_1_COMMAND_ID	dev/gt64260reg.h	269;"	d
X_1_COMMAND_ID	dev/mv64340reg.h	256;"	d
ZEXPORT	include/linux/zconf.h	61;"	d
ZEXPORTVA	include/linux/zconf.h	64;"	d
ZEXTERN	include/linux/zconf.h	67;"	d
ZLIB_VERSION	include/linux/zlib.h	40;"	d
Z_ASCII	include/linux/zlib.h	156;"	d
Z_BEST_COMPRESSION	include/linux/zlib.h	146;"	d
Z_BEST_SPEED	include/linux/zlib.h	145;"	d
Z_BINARY	include/linux/zlib.h	155;"	d
Z_BUF_ERROR	include/linux/zlib.h	138;"	d
Z_DATA_ERROR	include/linux/zlib.h	136;"	d
Z_DEFAULT_COMPRESSION	include/linux/zlib.h	147;"	d
Z_DEFAULT_STRATEGY	include/linux/zlib.h	152;"	d
Z_DEFLATED	include/linux/zlib.h	160;"	d
Z_ERRNO	include/linux/zlib.h	134;"	d
Z_FILTERED	include/linux/zlib.h	150;"	d
Z_FINISH	include/linux/zlib.h	128;"	d
Z_FULL_FLUSH	include/linux/zlib.h	127;"	d
Z_HUFFMAN_ONLY	include/linux/zlib.h	151;"	d
Z_MEM_ERROR	include/linux/zlib.h	137;"	d
Z_NEED_DICT	include/linux/zlib.h	133;"	d
Z_NO_COMPRESSION	include/linux/zlib.h	144;"	d
Z_NO_FLUSH	include/linux/zlib.h	123;"	d
Z_NULL	include/linux/zlib.h	163;"	d
Z_OK	include/linux/zlib.h	131;"	d
Z_PACKET_FLUSH	include/linux/zlib.h	125;"	d
Z_PARTIAL_FLUSH	include/linux/zlib.h	124;"	d
Z_STREAM_END	include/linux/zlib.h	132;"	d
Z_STREAM_ERROR	include/linux/zlib.h	135;"	d
Z_SYNC_FLUSH	include/linux/zlib.h	126;"	d
Z_UNKNOWN	include/linux/zlib.h	157;"	d
Z_VERSION_ERROR	include/linux/zlib.h	139;"	d
_B	include/ctype.h	56;"	d
_BSD_CLOCK_T_	include/time.h	56;"	d
_BSD_SIZE_T_	include/stddef.h	48;"	d
_BSD_SIZE_T_	include/stdio.h	15;"	d
_BSD_SIZE_T_	include/stdlib.h	49;"	d
_BSD_SIZE_T_	include/string.h	41;"	d
_BSD_SIZE_T_	include/time.h	66;"	d
_BSD_TIME_T_	include/time.h	61;"	d
_BSD_WCHAR_T_	include/stddef.h	53;"	d
_BSD_WCHAR_T_	include/stdlib.h	54;"	d
_C	include/ctype.h	54;"	d
_CDEFS_H_	include/cdefs.h	43;"	d
_CTYPE_H_	include/ctype.h	46;"	d
_DS_17285REG_H_	dev/mc146818reg.h	34;"	d
_ERR_H_	include/err.h	40;"	d
_FCNTL_H_	include/fcntl.h	4;"	d
_FTP_H_	include/arpa/ftp.h	40;"	d
_GT64240REG_H_	dev/gt64240reg.h	36;"	d
_GT64260_H_	dev/gt64260reg.h	38;"	d
_GT64420REG_H_	dev/gt64420reg.h	36;"	d
_INET_H_	include/arpa/inet.h	64;"	d
_L	include/ctype.h	50;"	d
_LINUX_ERRNO_H	include/linux/errno.h	2;"	d
_MACHINE_AUTOCONF_H_	include/autoconf.h	39;"	d
_MACHINE_MPC106REG_H_	dev/mpc106reg.h	38;"	d
_MATH_	include/math.h	3;"	d
_MIPS_PIO_H_	include/tgt/pio.h	33;"	d
_MV64340REG_H_	dev/mv64340reg.h	37;"	d
_MV64360REG_H_	dev/mv64360reg.h	36;"	d
_N	include/ctype.h	51;"	d
_NAMESER_H_	include/arpa/nameser.h	86;"	d
_NETDB_H_	include/netdb.h	73;"	d
_P	include/ctype.h	53;"	d
_PATH_HEQUIV	include/netdb.h	81;"	d
_PATH_HOSTS	include/netdb.h	82;"	d
_PATH_NETWORKS	include/netdb.h	83;"	d
_PATH_PROTOCOLS	include/netdb.h	84;"	d
_PATH_RESCONF	include/resolv.h	92;"	d
_PATH_SERVICES	include/netdb.h	85;"	d
_PMON_H_	include/pmon.h	43;"	d
_QUEUE_H_	include/queue.h	40;"	d
_RESOLV_H_	include/resolv.h	64;"	d
_S	include/ctype.h	52;"	d
_SETJMP_H_	include/setjmp.h	45;"	d
_STDDEF_H_	include/stddef.h	40;"	d
_STDIO_	include/stdio.h	3;"	d
_STDLIB_H_	include/stdlib.h	40;"	d
_STRING_H_	include/string.h	36;"	d
_SYS_TYPES_H_	include/types.h	45;"	d
_TELNET_H_	include/arpa/telnet.h	40;"	d
_TERMIO_	include/termio.h	3;"	d
_TFTP_H_	include/arpa/tftp.h	40;"	d
_TIME_H_	include/time.h	46;"	d
_U	include/ctype.h	49;"	d
_UNISTD_H_	include/unistd.h	40;"	d
_USER_SIGNAL_H	include/signal.h	40;"	d
_X	include/ctype.h	55;"	d
_ZCONF_H	include/linux/zconf.h	9;"	d
_ZLIB_H	include/linux/zlib.h	32;"	d
_Z_UTIL_H	include/linux/zutil.h	14;"	d
__32BIT__	include/linux/zconf.h	13;"	d
__BEGIN_DECLS	include/cdefs.h	56;"	d
__BEGIN_DECLS	include/cdefs.h	59;"	d
__BIND	include/arpa/nameser.h	108;"	d
__BIT_TYPES_DEFINED__	include/types.h	100;"	d
__CONCAT	include/cdefs.h	72;"	d
__CONCAT	include/cdefs.h	88;"	d
__CONCAT	include/types.h	47;"	d
__CONCAT	include/types.h	63;"	d
__CPC700_H__	dev/cpc700.h	36;"	d
__CPC700_IIC_H__	dev/cpc700_iic.h	36;"	d
__CPC710_H__	dev/cpc710.h	37;"	d
__DEBUGGER_H__	include/debugger.h	34;"	d
__DISKFS_H__	include/diskfs.h	36;"	d
__ELAN520_H__	dev/elan520.h	35;"	d
__END_DECLS	include/cdefs.h	57;"	d
__END_DECLS	include/cdefs.h	60;"	d
__EXEC_H__	include/exec.h	37;"	d
__FILE_H__	include/file.h	35;"	d
__GZIPFS_H__	include/gzipfs.h	36;"	d
__INCgt96132Rh	dev/gt96132reg.h	38;"	d
__KB	dev/flashdev.c	156;"	d	file:
__KB	dev/flashdev.c	55;"	d	file:
__KEY_DEFS_H__	dev/key_defs.h	2;"	d
__KPRINTF_ATTRIBUTE__	include/cdefs.h	50;"	d
__LINUXIO_H_	include/tgt/io.h	2;"	d
__MPC107REG_H__	dev/mpc107reg.h	39;"	d
__P	include/cdefs.h	71;"	d
__P	include/cdefs.h	87;"	d
__P	include/types.h	62;"	d
__PMONENV_H__	include/pmonenv.h	34;"	d
__RAMFILE_H__	include/ramfile.h	36;"	d
__RES	include/resolv.h	83;"	d
__SLOW_DOWN_IO	include/tgt/io.h	4;"	d
__STRING	include/cdefs.h	73;"	d
__STRING	include/cdefs.h	89;"	d
__STRING	include/types.h	48;"	d
__STRING	include/types.h	64;"	d
__SWAP_BROKEN	include/types.h	137;"	d
__SYS_ERRLIST	include/errno.h	48;"	d
__URL_H__	include/url.h	37;"	d
__attribute__	include/cdefs.h	122;"	d
__const	include/cdefs.h	75;"	d
__const	include/cdefs.h	92;"	d
__const	include/types.h	50;"	d
__const	include/types.h	67;"	d
__dead	include/cdefs.h	124;"	d
__dead	include/cdefs.h	137;"	d
__inline	include/cdefs.h	79;"	d
__inline	include/cdefs.h	82;"	d
__inline	include/cdefs.h	93;"	d
__inline	include/types.h	54;"	d
__inline	include/types.h	57;"	d
__inline	include/types.h	68;"	d
__kprintf_attribute__	include/cdefs.h	130;"	d
__kprintf_attribute__	include/cdefs.h	132;"	d
__pure	include/cdefs.h	125;"	d
__pure	include/cdefs.h	138;"	d
__res_state	include/resolv.h	/^struct __res_state {$/;"	s
__signed	include/cdefs.h	76;"	d
__signed	include/cdefs.h	94;"	d
__signed	include/types.h	51;"	d
__signed	include/types.h	69;"	d
__volatile	include/cdefs.h	77;"	d
__volatile	include/cdefs.h	95;"	d
__volatile	include/types.h	52;"	d
__volatile	include/types.h	70;"	d
_gt64120p	dev/gt64120reg.h	/^static char * const _gt64120p = (char *)PHYS_TO_UNCACHED(GT64120_BASE);$/;"	v
_matchval	env.c	/^static int _matchval (sp, value)$/;"	f	file:
_pci_break_tag	dev/cpc700.c	/^void _pci_break_tag(tag, busp, devicep, functionp)$/;"	f
_pci_break_tag	dev/cpc710.c	/^void _pci_break_tag(tag, busp, devicep, functionp)$/;"	f
_pci_break_tag	dev/mpc107.c	/^void _pci_break_tag(tag, busp, devicep, functionp)$/;"	f
_pci_conf_read	dev/cpc700.c	/^pcireg_t _pci_conf_read(tag, reg)$/;"	f
_pci_conf_read	dev/cpc710.c	/^pcireg_t _pci_conf_read(pcitag_t tag, int reg)$/;"	f
_pci_conf_read	dev/mpc107.c	/^pcireg_t _pci_conf_read(pcitag_t tag, int reg)$/;"	f
_pci_conf_readn	dev/cpc710.c	/^static pcireg_t _pci_conf_readn(pcitag_t tag, int reg, int width)$/;"	f	file:
_pci_conf_readn	dev/mpc107.c	/^static pcireg_t _pci_conf_readn(tag, reg, width)$/;"	f	file:
_pci_conf_write	dev/cpc700.c	/^void _pci_conf_write(tag, reg, data)$/;"	f
_pci_conf_write	dev/cpc710.c	/^void _pci_conf_write(pcitag_t tag, int reg, pcireg_t data)$/;"	f
_pci_conf_write	dev/mpc107.c	/^void _pci_conf_write(pcitag_t tag, int reg, pcireg_t data)$/;"	f
_pci_conf_writen	dev/cpc710.c	/^static void _pci_conf_writen(pcitag_t tag, int reg, pcireg_t data, int width)$/;"	f	file:
_pci_conf_writen	dev/mpc107.c	/^static void _pci_conf_writen(tag, reg, data, width)$/;"	f	file:
_pci_make_tag	dev/cpc700.c	/^pcitag_t _pci_make_tag(bus, device, function)$/;"	f
_pci_make_tag	dev/cpc710.c	/^pcitag_t _pci_make_tag(bus, device, function)$/;"	f
_pci_make_tag	dev/mpc107.c	/^pcitag_t _pci_make_tag(bus, device, function)$/;"	f
_physadr	include/types.h	/^typedef struct _physadr {$/;"	s
_setenv	env.c	/^static int _setenv (name, value)$/;"	f	file:
_swap_	include/tgt/pio.h	59;"	d
_tolower	include/ctype.h	106;"	d
_toupper	include/ctype.h	107;"	d
a	include/tgt/pio.h	/^	volatile u_int32_t *a;$/;"	v
a	include/tgt/pio.h	/^        volatile u_int16_t *a;$/;"	v
a	include/tgt/pio.h	/^        volatile u_int32_t *a;$/;"	v
aa	include/arpa/nameser.h	/^	unsigned	aa :1;		\/* authoritive answer *\/$/;"	m	struct:__anon3
aa	include/arpa/nameser.h	/^	unsigned	aa: 1;		\/* authoritive answer *\/$/;"	m	struct:__anon3
acknowledge	dev/kbd.c	/^static volatile unsigned char acknowledge;$/;"	v	file:
ad	include/arpa/nameser.h	/^	unsigned	ad: 1;		\/* authentic data from named *\/$/;"	m	struct:__anon3
add_op	include/ri.h	/^	add_op, addu_op, sub_op, subu_op,$/;"	e	enum:spec_op
addi_op	include/ri.h	/^	addi_op, addiu_op, slti_op, sltiu_op,$/;"	e	enum:major_op
addiu_op	include/ri.h	/^	addi_op, addiu_op, slti_op, sltiu_op,$/;"	e	enum:major_op
addr	include/pmon.h	/^    Func           *addr;$/;"	m	struct:Demo
addr	include/pmon.h	/^    unsigned long   addr;$/;"	m	struct:Bps
addr	include/pmon.h	/^    unsigned long   addr;$/;"	m	struct:Stopentry
addr	include/resolv.h	/^		struct in_addr	addr;$/;"	m	struct:__res_state::__anon4	typeref:struct:__res_state::__anon4::in_addr
addrinfo	include/netdb.h	/^struct addrinfo {$/;"	s
addu_op	include/ri.h	/^	add_op, addu_op, sub_op, subu_op,$/;"	e	enum:spec_op
adler	include/linux/zlib.h	/^    uLong   adler;      \/* adler32 value of the uncompressed data *\/$/;"	m	struct:z_stream_s
ai_addr	include/netdb.h	/^	struct sockaddr *ai_addr; \/* socket-address for socket *\/$/;"	m	struct:addrinfo	typeref:struct:addrinfo::sockaddr
ai_addrlen	include/netdb.h	/^	int ai_addrlen;		\/* length of socket-address *\/$/;"	m	struct:addrinfo
ai_canonname	include/netdb.h	/^	char *ai_canonname;	\/* canonical name for service location (iff req) *\/$/;"	m	struct:addrinfo
ai_family	include/netdb.h	/^	int ai_family;		\/* protocol family for socket *\/$/;"	m	struct:addrinfo
ai_flags	include/netdb.h	/^	int ai_flags;		\/* input flags *\/$/;"	m	struct:addrinfo
ai_next	include/netdb.h	/^	struct addrinfo *ai_next; \/* pointer to next in list *\/$/;"	m	struct:addrinfo	typeref:struct:addrinfo::addrinfo
ai_protocol	include/netdb.h	/^	int ai_protocol;	\/* protocol for socket *\/$/;"	m	struct:addrinfo
ai_socktype	include/netdb.h	/^	int ai_socktype;	\/* socket type *\/$/;"	m	struct:addrinfo
alloc_func	include/linux/zlib.h	/^typedef voidpf (*alloc_func) OF((voidpf opaque, uInt items, uInt size));$/;"	t
ancount	include/arpa/nameser.h	/^	unsigned	ancount :16;	\/* number of answer entries *\/$/;"	m	struct:__anon3
and_op	include/ri.h	/^	and_op, or_op, xor_op, nor_op,$/;"	e	enum:spec_op
andi_op	include/ri.h	/^	andi_op, ori_op, xori_op, lui_op,$/;"	e	enum:major_op
arcount	include/arpa/nameser.h	/^	unsigned	arcount :16;	\/* number of resource entries *\/$/;"	m	struct:__anon3
arg	dev/generic_poll.c	/^	void *arg;$/;"	m	struct:poll_handle	file:
argvize	lib.c	/^int argvize (char *av[], char *s)$/;"	f
authtype_names	include/arpa/telnet.h	/^char *authtype_names[] = {$/;"	v
avail_in	include/linux/zlib.h	/^    uInt     avail_in;  \/* number of bytes available at next_in *\/$/;"	m	struct:z_stream_s
avail_out	include/linux/zlib.h	/^    uInt     avail_out; \/* remaining free space at next_out *\/$/;"	m	struct:z_stream_s
b64_ntop	include/resolv.h	207;"	d
b64_pton	include/resolv.h	208;"	d
backspace_cursor	dev/vgacon.c	/^int backspace_cursor()$/;"	f
base	include/ramfile.h	/^	unsigned long base;$/;"	m	struct:Ramfile
bc_op	include/ri.h	/^	bc_op         = 0x08, cop_op        = 0x10,$/;"	e	enum:cop_op
bcf_op	include/ri.h	/^	bcf_op, bct_op, bcfl_op, bctl_op$/;"	e	enum:bcop_op
bcfl_op	include/ri.h	/^	bcf_op, bct_op, bcfl_op, bctl_op$/;"	e	enum:bcop_op
bcond_op	include/ri.h	/^	spec_op, bcond_op, j_op, jal_op,$/;"	e	enum:major_op
bcop_op	include/ri.h	/^enum bcop_op {$/;"	g
bct_op	include/ri.h	/^	bcf_op, bct_op, bcfl_op, bctl_op$/;"	e	enum:bcop_op
bctl_op	include/ri.h	/^	bcf_op, bct_op, bcfl_op, bctl_op$/;"	e	enum:bcop_op
beq_op	include/ri.h	/^	beq_op, bne_op, blez_op, bgtz_op,$/;"	e	enum:major_op
beql_op	include/ri.h	/^	beql_op, bnel_op, blezl_op, bgtzl_op,$/;"	e	enum:major_op
bgez_op	include/ri.h	/^	bltz_op, bgez_op, bltzl_op, bgezl_op,$/;"	e	enum:rt_op
bgezal_op	include/ri.h	/^	bltzal_op, bgezal_op, bltzall_op, bgezall_op$/;"	e	enum:rt_op
bgezall_op	include/ri.h	/^	bltzal_op, bgezal_op, bltzall_op, bgezall_op$/;"	e	enum:rt_op
bgezl_op	include/ri.h	/^	bltz_op, bgez_op, bltzl_op, bgezl_op,$/;"	e	enum:rt_op
bgtz_op	include/ri.h	/^	beq_op, bne_op, blez_op, bgtz_op,$/;"	e	enum:major_op
bgtzl_op	include/ri.h	/^	beql_op, bnel_op, blezl_op, bgtzl_op,$/;"	e	enum:major_op
bh_dv	include/autoconf.h	/^	struct	device *bh_dv;$/;"	m	struct:bushook	typeref:struct:bushook::device
bh_intr_disestablish	include/autoconf.h	/^	void	(*bh_intr_disestablish) __P((void *, void *));$/;"	m	struct:bushook
bh_intr_establish	include/autoconf.h	/^	void	*(*bh_intr_establish) __P((void *, u_long, int, int,$/;"	m	struct:bushook
bh_matchname	include/autoconf.h	/^	int	(*bh_matchname)	__P((struct confargs *, char *));$/;"	m	struct:bushook
bh_type	include/autoconf.h	/^	int	bh_type;$/;"	m	struct:bushook
blez_op	include/ri.h	/^	beq_op, bne_op, blez_op, bgtz_op,$/;"	e	enum:major_op
blezl_op	include/ri.h	/^	beql_op, bnel_op, blezl_op, bgtzl_op,$/;"	e	enum:major_op
bltz_op	include/ri.h	/^	bltz_op, bgez_op, bltzl_op, bgezl_op,$/;"	e	enum:rt_op
bltzal_op	include/ri.h	/^	bltzal_op, bgezal_op, bltzall_op, bgezall_op$/;"	e	enum:rt_op
bltzall_op	include/ri.h	/^	bltzal_op, bgezal_op, bltzall_op, bgezall_op$/;"	e	enum:rt_op
bltzl_op	include/ri.h	/^	bltz_op, bgez_op, bltzl_op, bgezl_op,$/;"	e	enum:rt_op
bne_op	include/ri.h	/^	beq_op, bne_op, blez_op, bgtz_op,$/;"	e	enum:major_op
bnel_op	include/ri.h	/^	beql_op, bnel_op, blezl_op, bgtzl_op,$/;"	e	enum:major_op
brate	include/termio.h	/^	int brate;$/;"	m	struct:ConfigEntry
break_op	include/ri.h	/^	syscall_op, break_op, spim_op, sync_op,$/;"	e	enum:spec_op
bus	dev/pcibrvar.h	/^	int	bus;$/;"	m	struct:pcibr_config
bushook	include/autoconf.h	/^typedef struct bushook {$/;"	s
bushook_t	include/autoconf.h	/^} bushook_t;$/;"	t	typeref:struct:bushook
bytecopy	dev/fl_nvram.c	/^static void bytecopy(char *src, char *dst, size_t size)$/;"	f	file:
c_cc	include/termio.h	/^	unsigned char c_cc[NCC];$/;"	m	struct:termio
c_cflag	include/termio.h	/^	unsigned short c_cflag;$/;"	m	struct:termio
c_iflag	include/termio.h	/^	unsigned short c_iflag;$/;"	m	struct:termio
c_ispeed	include/termio.h	/^	int	c_ispeed;$/;"	m	struct:termio
c_lflag	include/termio.h	/^	unsigned short c_lflag;$/;"	m	struct:termio
c_oflag	include/termio.h	/^	unsigned short c_oflag;$/;"	m	struct:termio
c_ospeed	include/termio.h	/^	int	c_ospeed;$/;"	m	struct:termio
ca_baseaddr	include/autoconf.h	/^	u_int ca_baseaddr;$/;"	m	struct:confargs
ca_bus	include/autoconf.h	/^	bushook_t *ca_bus;		\/* bus device resides on. *\/$/;"	m	struct:confargs
ca_intr	include/autoconf.h	/^	int32_t *ca_intr;$/;"	m	struct:confargs
ca_iot	include/autoconf.h	/^	bus_space_tag_t ca_iot;$/;"	m	struct:confargs
ca_memt	include/autoconf.h	/^	bus_space_tag_t ca_memt; \/* XXX *\/$/;"	m	struct:confargs
ca_name	include/autoconf.h	/^	char	*ca_name;		\/* Device name. *\/$/;"	m	struct:confargs
ca_nintr	include/autoconf.h	/^	int ca_nintr;$/;"	m	struct:confargs
ca_node	include/autoconf.h	/^	u_int32_t ca_node;$/;"	m	struct:confargs
ca_nreg	include/autoconf.h	/^	int ca_nreg;$/;"	m	struct:confargs
ca_reg	include/autoconf.h	/^	u_int32_t *ca_reg;$/;"	m	struct:confargs
cache_op	include/ri.h	/^	sdl_op, sdr_op, swr_op, cache_op,$/;"	e	enum:major_op
caddr_t	include/types.h	/^typedef	char *		caddr_t;	\/* core address *\/$/;"	t
cd	include/arpa/nameser.h	/^	unsigned	cd: 1;		\/* checking disabled by resolver *\/$/;"	m	struct:__anon3
cfc_op	include/ri.h	/^	cfc_op        = 0x02, mtc_op        = 0x04,$/;"	e	enum:cop_op
chan	include/termio.h	/^	int chan;$/;"	m	struct:ConfigEntry
chan	include/termio.h	/^	int chan;$/;"	m	struct:DevEntry
charf	include/linux/zconf.h	/^typedef char  FAR charf;$/;"	t
check_axs	include/ri.h	250;"	d
chgfunc	env.c	/^	int (*chgfunc) __P ((char *, char *));$/;"	m	struct:stdenv	file:
cksum	dev/fl_nvram.c	/^static int cksum(void *p, size_t s, int set)$/;"	f	file:
cksum	tgt_env.c	/^static int cksum (void *p, size_t s, int set)$/;"	f	file:
clkread	dev/mc146818.c	/^static int clkread(reg)$/;"	f	file:
clkwrite	dev/mc146818.c	/^static void clkwrite(reg, data)$/;"	f	file:
clock_t	include/time.h	/^typedef	_BSD_CLOCK_T_	clock_t;$/;"	t
close	include/diskfs.h	/^	int (*close) __P((int));$/;"	m	struct:DiskFileSystem
close	include/file.h	/^	int	(*close) (int);$/;"	m	struct:FileSystem
cmd_eset	cmd_env.c	/^int cmd_eset (ac, av)$/;"	f
cmd_help	help.c	/^static int cmd_help (int ac, char *av[])$/;"	f	file:
cmd_program	program.c	/^static int cmd_program (int ac, char *av[])$/;"	f	file:
cmd_quit	main.c	/^static cmd_quit (int ac, char *av[])$/;"	f	file:
cmd_save	program.c	/^static int cmd_save (int ac, char *av[])$/;"	f	file:
cmd_set	cmd_env.c	/^int cmd_set (ac, av)$/;"	f
cmd_unset	cmd_env.c	/^int cmd_unset (ac, av)$/;"	f
cmdlist_expand	cmdtable.c	/^void cmdlist_expand (newcmdlist, atend)$/;"	f
cmdstr	include/pmon.h	/^    char           *cmdstr;$/;"	m	struct:Bps
colcount	dev/vgacon.c	/^int colcount = 80;$/;"	v
confargs	include/autoconf.h	/^struct confargs {$/;"	s
config_type	dev/pcibrvar.h	/^	int	config_type;$/;"	m	struct:pcibr_config
const	include/cdefs.h	105;"	d
const	include/types.h	80;"	d
control_keys	dev/kbd.c	/^unsigned char control_keys = 0;$/;"	v
cop0_coi_func	include/ri.h	/^enum cop0_coi_func {$/;"	g
cop0_com_func	include/ri.h	/^enum cop0_com_func {$/;"	g
cop0_op	include/ri.h	/^	cop0_op, cop1_op, cop2_op, cop1x_op,$/;"	e	enum:major_op
cop1_fmt	include/ri.h	/^enum cop1_fmt {$/;"	g
cop1_op	include/ri.h	/^	cop0_op, cop1_op, cop2_op, cop1x_op,$/;"	e	enum:major_op
cop1_sdw_func	include/ri.h	/^enum cop1_sdw_func {$/;"	g
cop1x_func	include/ri.h	/^enum cop1x_func {$/;"	g
cop1x_op	include/ri.h	/^	cop0_op, cop1_op, cop2_op, cop1x_op,$/;"	e	enum:major_op
cop2_op	include/ri.h	/^	cop0_op, cop1_op, cop2_op, cop1x_op,$/;"	e	enum:major_op
cop_op	include/ri.h	/^	bc_op         = 0x08, cop_op        = 0x10,$/;"	e	enum:cop_op
cop_op	include/ri.h	/^enum cop_op {$/;"	g
copm_op	include/ri.h	/^	copm_op       = 0x18$/;"	e	enum:cop_op
count	include/queue.h	/^	unsigned short count;$/;"	m	struct:Queue
cp0_badvaddr	include/ri.h	/^	unsigned long cp0_badvaddr;$/;"	m	struct:pt_regs
cp0_cause	include/ri.h	/^	unsigned long cp0_cause;$/;"	m	struct:pt_regs
cp0_epc	include/ri.h	/^	unsigned long cp0_epc;$/;"	m	struct:pt_regs
cp0_status	include/ri.h	/^	unsigned long cp0_status;$/;"	m	struct:pt_regs
cpc700_iic_read	dev/cpc700_iic.c	/^int cpc700_iic_read(char *buf, int offset, int length)$/;"	f
cpc700_iic_wrdy	dev/cpc700_iic.c	/^static __inline int cpc700_iic_wrdy(volatile u_char * iic_base, int offset)$/;"	f	file:
cpc700_iic_write	dev/cpc700_iic.c	/^int cpc700_iic_write(char *buf, int offset, int length)$/;"	f
crt_data	dev/vgacon.c	12;"	d	file:
crt_index	dev/vgacon.c	11;"	d	file:
ctc_op	include/ri.h	/^	dmtc_op       = 0x05, ctc_op        = 0x06,$/;"	e	enum:cop_op
ctrl_map	dev/kbd.h	/^u_short ctrl_map[NR_KEYS] = {$/;"	v
d_fmt	include/ri.h	/^	s_fmt, d_fmt, e_fmt, q_fmt,$/;"	e	enum:cop1_fmt
dadd_op	include/ri.h	/^	dadd_op, daddu_op, dsub_op, dsubu_op,$/;"	e	enum:spec_op
daddi_op	include/ri.h	/^	daddi_op, daddiu_op, ldl_op, ldr_op,$/;"	e	enum:major_op
daddiu_op	include/ri.h	/^	daddi_op, daddiu_op, ldl_op, ldr_op,$/;"	e	enum:major_op
daddr_t	include/types.h	/^typedef	int32_t		daddr_t;	\/* disk address *\/$/;"	t
daddu_op	include/ri.h	/^	dadd_op, daddu_op, dsub_op, dsubu_op,$/;"	e	enum:spec_op
dat	include/queue.h	/^	Msg dat[1];$/;"	m	struct:Queue
data	include/file.h	/^	void  *data;$/;"	m	struct:File
data_type	include/linux/zlib.h	/^    int     data_type;  \/* best guess about the data type: ascii or binary *\/$/;"	m	struct:z_stream_s
dctr_op	include/ri.h	/^	tlbp1_op      = 0x08, dctr_op       = 0x09,$/;"	e	enum:cop0_com_func
dctw_op	include/ri.h	/^	dctw_op       = 0x0a$/;"	e	enum:cop0_com_func
ddiv_op	include/ri.h	/^	dmult_op, dmultu_op, ddiv_op, ddivu_op,$/;"	e	enum:spec_op
ddivu_op	include/ri.h	/^	dmult_op, dmultu_op, ddiv_op, ddivu_op,$/;"	e	enum:spec_op
decmod	include/pmon.h	390;"	d
defdname	include/resolv.h	/^	char	defdname[256];		\/* default domain (deprecated) *\/$/;"	m	struct:__res_state
deflateBound	include/linux/zlib.h	/^static inline unsigned long deflateBound(unsigned long s)$/;"	f
delay	tick.c	/^void delay (microseconds)$/;"	f
desc	include/pmon.h	/^	const char     *desc;$/;"	m	struct:Cmd
desc	include/pmon.h	/^    const char     *desc;$/;"	m	struct:Optdesc
devinfo	include/termio.h	/^	char *devinfo;$/;"	m	struct:ConfigEntry
devname	include/diskfs.h	/^	char *devname;$/;"	m	struct:DiskFile
devname	include/file.h	/^	char	*devname;$/;"	m	struct:FileSystem
dfs	include/diskfs.h	/^	DiskFileSystem *dfs;$/;"	m	struct:DiskFile
discoinit	dev/discouart.c	/^static int discoinit(volatile void *dp)$/;"	f	file:
discoprogram	dev/discouart.c	/^static int discoprogram(volatile void *dp, unsigned long freq, int baudrate)$/;"	f	file:
discouart	dev/discouart.c	/^int discouart(int op, struct DevEntry *dev, unsigned long param, int data)$/;"	f
div_op	include/ri.h	/^	mult_op, multu_op, div_op, divu_op,$/;"	e	enum:spec_op
div_t	include/stdlib.h	/^} div_t;$/;"	t	typeref:struct:__anon6
divu_op	include/ri.h	/^	mult_op, multu_op, div_op, divu_op,$/;"	e	enum:spec_op
dmfc_op	include/ri.h	/^	mfc_op        = 0x00, dmfc_op       = 0x01,$/;"	e	enum:cop_op
dmtc_op	include/ri.h	/^	dmtc_op       = 0x05, ctc_op        = 0x06,$/;"	e	enum:cop_op
dmult_op	include/ri.h	/^	dmult_op, dmultu_op, ddiv_op, ddivu_op,$/;"	e	enum:spec_op
dmultu_op	include/ri.h	/^	dmult_op, dmultu_op, ddiv_op, ddivu_op,$/;"	e	enum:spec_op
dn_comp	include/resolv.h	230;"	d
dn_count_labels	include/resolv.h	229;"	d
dn_expand	include/resolv.h	239;"	d
dn_skipname	include/resolv.h	211;"	d
dnsrch	include/resolv.h	/^	char	*dnsrch[MAXDNSRCH+1];	\/* components of domain to search *\/$/;"	m	struct:__res_state
do_acknowledge	dev/kbd.c	/^static int do_acknowledge (unsigned char scancode)$/;"	f	file:
do_cmd	cmdparser.c	/^void do_cmd (p)$/;"	f
do_cons	dev/kbd.c	/^	do_self, do_fn, do_spec, do_pad, do_dead, do_cons, do_cur, do_shift;$/;"	v	file:
do_cons	dev/kbd.c	/^static void do_cons (unsigned char value, char up_flag)$/;"	f	file:
do_cur	dev/kbd.c	/^	do_self, do_fn, do_spec, do_pad, do_dead, do_cons, do_cur, do_shift;$/;"	v	file:
do_cur	dev/kbd.c	/^static void do_cur (unsigned char value, char up_flag)$/;"	f	file:
do_dead	dev/kbd.c	/^	do_self, do_fn, do_spec, do_pad, do_dead, do_cons, do_cur, do_shift;$/;"	v	file:
do_dead	dev/kbd.c	/^static void do_dead (unsigned char value, char up_flag)$/;"	f	file:
do_fn	dev/kbd.c	/^	do_self, do_fn, do_spec, do_pad, do_dead, do_cons, do_cur, do_shift;$/;"	v	file:
do_fn	dev/kbd.c	/^static void do_fn (unsigned char value, char up_flag)$/;"	f	file:
do_null	dev/kbd.c	/^static void do_null ()$/;"	f	file:
do_null	dev/kbd.c	/^static void_fn do_null, enter;$/;"	v	file:
do_pad	dev/kbd.c	/^	do_self, do_fn, do_spec, do_pad, do_dead, do_cons, do_cur, do_shift;$/;"	v	file:
do_pad	dev/kbd.c	/^static void do_pad (unsigned char value, char up_flag)$/;"	f	file:
do_self	dev/kbd.c	/^	do_self, do_fn, do_spec, do_pad, do_dead, do_cons, do_cur, do_shift;$/;"	v	file:
do_self	dev/kbd.c	/^static void do_self (unsigned char value, char up_flag)$/;"	f	file:
do_setenv	env.c	/^int do_setenv (name, value, temp)$/;"	f
do_shift	dev/kbd.c	/^	do_self, do_fn, do_spec, do_pad, do_dead, do_cons, do_cur, do_shift;$/;"	v	file:
do_shift	dev/kbd.c	/^static void do_shift (unsigned char value, char up_flag)$/;"	f	file:
do_spec	dev/kbd.c	/^	do_self, do_fn, do_spec, do_pad, do_dead, do_cons, do_cur, do_shift;$/;"	v	file:
do_spec	dev/kbd.c	/^static void do_spec (unsigned char value, char up_flag)$/;"	f	file:
dotik	tick.c	/^void dotik (rate, use_ret)$/;"	f
dsll32_op	include/ri.h	/^	dsll32_op, spec8_unused_op, dsrl32_op, dsra32_op$/;"	e	enum:spec_op
dsll_op	include/ri.h	/^	dsll_op, spec7_unused_op, dsrl_op, dsra_op,$/;"	e	enum:spec_op
dsllv_op	include/ri.h	/^	dsllv_op, spec2_unused_op, dsrlv_op, dsrav_op,$/;"	e	enum:spec_op
dsra32_op	include/ri.h	/^	dsll32_op, spec8_unused_op, dsrl32_op, dsra32_op$/;"	e	enum:spec_op
dsra_op	include/ri.h	/^	dsll_op, spec7_unused_op, dsrl_op, dsra_op,$/;"	e	enum:spec_op
dsrav_op	include/ri.h	/^	dsllv_op, spec2_unused_op, dsrlv_op, dsrav_op,$/;"	e	enum:spec_op
dsrl32_op	include/ri.h	/^	dsll32_op, spec8_unused_op, dsrl32_op, dsra32_op$/;"	e	enum:spec_op
dsrl_op	include/ri.h	/^	dsll_op, spec7_unused_op, dsrl_op, dsra_op,$/;"	e	enum:spec_op
dsrlv_op	include/ri.h	/^	dsllv_op, spec2_unused_op, dsrlv_op, dsrav_op,$/;"	e	enum:spec_op
dsub_op	include/ri.h	/^	dadd_op, daddu_op, dsub_op, dsubu_op,$/;"	e	enum:spec_op
dsubu_op	include/ri.h	/^	dadd_op, daddu_op, dsub_op, dsubu_op,$/;"	e	enum:spec_op
dummy	include/linux/zlib.h	/^    struct internal_state {int dummy;}; \/* hack for buggy compilers *\/$/;"	m	struct:internal_state
e0_keys	dev/kbd.c	/^static unsigned char e0_keys[128] = {$/;"	v	file:
e_fmt	include/ri.h	/^	s_fmt, d_fmt, e_fmt, q_fmt,$/;"	e	enum:cop1_fmt
encrypt_names	include/arpa/telnet.h	/^char *encrypt_names[] = {$/;"	v
enctype_names	include/arpa/telnet.h	/^char *enctype_names[] = {$/;"	v
enter	dev/kbd.c	/^static void enter (void)$/;"	f	file:
enter	dev/kbd.c	/^static void_fn do_null, enter;$/;"	v	file:
envbuild	env.c	/^void envbuild (char **vsp, char *ssp)$/;"	f
envinit	env.c	/^void envinit ()$/;"	f
envinited	env.c	/^static int envinited = 0;$/;"	v	file:
envpair	include/pmonenv.h	/^struct envpair {$/;"	s
envsize	env.c	/^void envsize (int *ec, int *slen)$/;"	f
envvar	env.c	/^struct envpair envvar[NVAR];$/;"	v	typeref:struct:envpair
erase_chip	include/pflash.h	/^	int	(*erase_chip)		\/* Erase Chip *\/$/;"	m	struct:fl_functions
erase_sector	include/pflash.h	/^	int	(*erase_sector)		\/* Erase Sector *\/$/;"	m	struct:fl_functions
erase_suspend	include/pflash.h	/^	int	(*erase_suspend)		\/* Erase Suspend *\/$/;"	m	struct:fl_functions
eret_op	include/ri.h	/^	rfe_op        = 0x10, eret_op       = 0x18$/;"	e	enum:cop0_coi_func
esc_code	dev/kbd.c	/^unsigned int esc_code;$/;"	v
esc_seq	dev/kbd.c	/^unsigned int esc_seq;$/;"	v
execname	include/exec.h	/^	char *execname;$/;"	m	struct:ExecType
expand	cmdparser.c	/^static char *expand (cmdline)$/;"	f	file:
ext	dev/kbd.c	/^int ext;$/;"	v
extent_mem	dev/pcibrvar.h	/^	struct extent *extent_mem;$/;"	m	struct:pcibr_softc	typeref:struct:pcibr_softc::extent
extent_port	dev/pcibrvar.h	/^	struct extent *extent_port;$/;"	m	struct:pcibr_softc	typeref:struct:pcibr_softc::extent
f_register_t	include/types.h	/^typedef int32_t		     f_register_t;$/;"	t
f_register_t	include/types.h	/^typedef int64_t		     f_register_t;$/;"	t
fabs_op	include/ri.h	/^	fsqrt_op     =  0x04, fabs_op      =  0x05,$/;"	e	enum:cop1_sdw_func
fadd_op	include/ri.h	/^	fadd_op      =  0x00, fsub_op      =  0x01,$/;"	e	enum:cop1_sdw_func
fbterm	dev/vgacon.c	/^int fbterm(int op, struct DevEntry *dev, unsigned long param, int data)$/;"	f
fceil_op	include/ri.h	/^	fceil_op     =  0x0e, ffloor_op    =  0x0f,$/;"	e	enum:cop1_sdw_func
fceill_op	include/ri.h	/^	fceill_op    =  0x0a, ffloorl_op   =  0x0b,$/;"	e	enum:cop1_sdw_func
fcmp_op	include/ri.h	/^	fcmp_op      =  0x30$/;"	e	enum:cop1_sdw_func
fcvtd_op	include/ri.h	/^	fcvtd_op     =  0x21, fcvte_op     =  0x22,$/;"	e	enum:cop1_sdw_func
fcvte_op	include/ri.h	/^	fcvtd_op     =  0x21, fcvte_op     =  0x22,$/;"	e	enum:cop1_sdw_func
fcvtl_op	include/ri.h	/^	fcvtw_op     =  0x24, fcvtl_op     =  0x25,$/;"	e	enum:cop1_sdw_func
fcvts_op	include/ri.h	/^	frsqrt_op    =  0x16, fcvts_op     =  0x20,$/;"	e	enum:cop1_sdw_func
fcvtw_op	include/ri.h	/^	fcvtw_op     =  0x24, fcvtl_op     =  0x25,$/;"	e	enum:cop1_sdw_func
fd	include/ramfile.h	/^	int fd;$/;"	m	struct:Ramfile
fd	include/stdio.h	/^	int fd;$/;"	m	struct:FILE
fdiv_op	include/ri.h	/^	fmul_op      =  0x02, fdiv_op      =  0x03,$/;"	e	enum:cop1_sdw_func
ffloor_op	include/ri.h	/^	fceil_op     =  0x0e, ffloor_op    =  0x0f,$/;"	e	enum:cop1_sdw_func
ffloorl_op	include/ri.h	/^	fceill_op    =  0x0a, ffloorl_op   =  0x0b,$/;"	e	enum:cop1_sdw_func
fifo	dev/ns16550.h	51;"	d
filename	include/url.h	/^	char		filename[FILENAMESIZE];$/;"	m	struct:Url
first	include/queue.h	/^	unsigned short first;$/;"	m	struct:Queue
fixpt_t	include/types.h	/^typedef	u_int32_t	fixpt_t;	\/* fixed point number *\/$/;"	t
fl_autoselect	dev/flash.c	/^static __inline void fl_autoselect(struct fl_map *map)$/;"	f	file:
fl_cap	include/pflash.h	/^	char	fl_cap;		\/* Flash capabilites *\/$/;"	m	struct:fl_device
fl_command_int	dev/flash_int.c	/^static __inline void fl_command_int(map, command, offset)$/;"	f	file:
fl_device	include/pflash.h	/^struct fl_device {$/;"	s
fl_devident	dev/flash.c	/^struct fl_device *fl_devident(void *base, struct fl_map **m)$/;"	f
fl_erase_chip_amd	dev/flash_amd.c	/^int fl_erase_chip_amd(map, dev)$/;"	f
fl_erase_chip_int	dev/flash_int.c	/^int fl_erase_chip_int(map, dev)$/;"	f
fl_erase_chip_sst	dev/flash_sst.c	/^int fl_erase_chip_sst(map, dev)$/;"	f
fl_erase_chip_st	dev/flash_st.c	/^fl_erase_chip_st(map, dev)$/;"	f
fl_erase_chip_winbond	dev/flash_winbond.c	/^int fl_erase_chip_winbond(map, dev)$/;"	f
fl_erase_device	dev/flash.c	/^int fl_erase_device(void *base, int size, int verbose)$/;"	f
fl_erase_resume_amd	dev/flash_amd.c	/^int fl_erase_resume_amd(map, dev)$/;"	f
fl_erase_resume_int	dev/flash_int.c	/^int fl_erase_resume_int(map, dev)$/;"	f
fl_erase_sector_amd	dev/flash_amd.c	/^int fl_erase_sector_amd(map, dev, offset)$/;"	f
fl_erase_sector_int	dev/flash_int.c	/^int fl_erase_sector_int(map, dev, offset)$/;"	f
fl_erase_sector_sst	dev/flash_sst.c	/^int fl_erase_sector_sst(map, dev, offset)$/;"	f
fl_erase_sector_st	dev/flash_st.c	/^fl_erase_sector_st(map, dev, offset)$/;"	f
fl_erase_sector_winbond	dev/flash_winbond.c	/^int fl_erase_sector_winbond(map, dev, offset)$/;"	f
fl_erase_suspend_amd	dev/flash_amd.c	/^int fl_erase_suspend_amd(map, dev)$/;"	f
fl_erase_suspend_int	dev/flash_int.c	/^int fl_erase_suspend_int(map, dev)$/;"	f
fl_erase_suspend_sst	dev/flash_sst.c	/^int fl_erase_suspend_sst(map, dev)$/;"	f
fl_erase_suspend_st	dev/flash_st.c	/^fl_erase_suspend_st(map, dev)$/;"	f
fl_erase_suspend_winbond	dev/flash_winbond.c	/^int fl_erase_suspend_winbond(map, dev)$/;"	f
fl_find_map	dev/flash.c	/^struct fl_map *fl_find_map(void *base)$/;"	f
fl_func_amd	dev/flash_amd.c	/^struct fl_functions fl_func_amd = { fl_erase_chip_amd,$/;"	v	typeref:struct:fl_functions
fl_func_int	dev/flash_int.c	/^struct fl_functions fl_func_int = { fl_erase_chip_int,$/;"	v	typeref:struct:fl_functions
fl_func_sst	dev/flash_sst.c	/^struct fl_functions fl_func_sst = { fl_erase_chip_sst,$/;"	v	typeref:struct:fl_functions
fl_func_st	dev/flash_st.c	/^struct fl_functions fl_func_st = {fl_erase_chip_st,$/;"	v	typeref:struct:fl_functions
fl_func_winbond	dev/flash_winbond.c	/^struct fl_functions fl_func_winbond = { fl_erase_chip_winbond,$/;"	v	typeref:struct:fl_functions
fl_functions	include/pflash.h	/^struct fl_functions {$/;"	s
fl_id	include/pflash.h	/^	char	fl_id;		\/* Device id code *\/$/;"	m	struct:fl_device
fl_isbusy_amd	dev/flash_amd.c	/^int fl_isbusy_amd(map, dev, what, offset, erase)$/;"	f
fl_isbusy_int	dev/flash_int.c	/^int fl_isbusy_int(map, dev, what, offset, erase)$/;"	f
fl_isbusy_sst	dev/flash_sst.c	/^int fl_isbusy_sst(map, dev, what, offset, erase)$/;"	f
fl_isbusy_st	dev/flash_st.c	/^fl_isbusy_st(map, dev, what, offset, erase)$/;"	f
fl_isbusy_winbond	dev/flash_winbond.c	/^int fl_isbusy_winbond(map, dev, what, offset, erase)$/;"	f
fl_known_dev	dev/flashdev.c	/^struct fl_device fl_known_dev[] = {$/;"	v	typeref:struct:fl_device
fl_map	include/pflash.h	/^struct fl_map {$/;"	s
fl_map_base	include/pflash.h	/^	u_int32_t fl_map_base;	\/* Start of flash area in physical map *\/$/;"	m	struct:fl_map
fl_map_bus	include/pflash.h	/^	int	fl_map_bus;	\/* Bus width type, se below *\/$/;"	m	struct:fl_map
fl_map_chips	include/pflash.h	/^	int	fl_map_chips;	\/* Number of chips to operate in one cycle *\/$/;"	m	struct:fl_map
fl_map_offset	include/pflash.h	/^	int	fl_map_offset;	\/* Flash Offset mapped in memory *\/$/;"	m	struct:fl_map
fl_map_size	include/pflash.h	/^	u_int32_t fl_map_size;	\/* Size of flash area in physical map *\/$/;"	m	struct:fl_map
fl_map_width	include/pflash.h	/^	int	fl_map_width;	\/* Number of bytes to program in one cycle *\/$/;"	m	struct:fl_map
fl_mfg	include/pflash.h	/^	char	fl_mfg;		\/* Flash manufacturer code *\/$/;"	m	struct:fl_device
fl_mydetect	dev/flash.c	/^static __inline void fl_mydetect(struct fl_map *map)$/;"	f	file:
fl_name	include/pflash.h	/^	char	*fl_name;$/;"	m	struct:fl_device
fl_program	dev/flash.c	/^int fl_program(void *fl_base, void *data_base, int data_size, int verbose)$/;"	f
fl_program_amd	dev/flash_amd.c	/^int fl_program_amd(map, dev, pa, pd)$/;"	f
fl_program_device	dev/flash.c	/^int fl_program_device(void *fl_base, void *data_base, int data_size, int verbose)$/;"	f
fl_program_int	dev/flash_int.c	/^int fl_program_int(map, dev, pa, pd)$/;"	f
fl_program_sst	dev/flash_sst.c	/^int fl_program_sst(map, dev, pa, pd)$/;"	f
fl_program_st	dev/flash_st.c	/^fl_program_st(map, dev, pa, pd)$/;"	f
fl_program_winbond	dev/flash_winbond.c	/^int fl_program_winbond(map, dev, pa, pd)$/;"	f
fl_proto	include/pflash.h	/^	char	fl_proto;	\/* Command protocol *\/$/;"	m	struct:fl_device
fl_query_info	dev/flash.c	/^void fl_query_info()$/;"	f
fl_reset	dev/flash.c	/^static __inline void fl_reset(struct fl_map *map)$/;"	f	file:
fl_reset_amd	dev/flash_amd.c	/^int fl_reset_amd(map, dev)$/;"	f
fl_reset_int	dev/flash_int.c	/^int fl_reset_int(map, dev)$/;"	f
fl_reset_sst	dev/flash_sst.c	/^int fl_reset_sst(map, dev)$/;"	f
fl_reset_st	dev/flash_st.c	/^fl_reset_st(map, dev)$/;"	f
fl_reset_winbond	dev/flash_winbond.c	/^int fl_reset_winbond(map, dev)$/;"	f
fl_secsize	include/pflash.h	/^	int	fl_secsize;	\/* Device sector-size in k-bytes *\/$/;"	m	struct:fl_device
fl_size	include/pflash.h	/^	int	fl_size;	\/* Device size in k-bytes *\/$/;"	m	struct:fl_device
fl_unlock_bypass_amd	dev/flash_amd.c	/^static __inline void fl_unlock_bypass_amd(map)$/;"	f	file:
fl_unlock_bypass_program_amd	dev/flash_amd.c	/^static __inline void fl_unlock_bypass_program_amd(map, pa, pd)$/;"	f	file:
fl_unlock_bypass_reset_amd	dev/flash_amd.c	/^static __inline void fl_unlock_bypass_reset_amd(map)$/;"	f	file:
fl_varsecsize	include/pflash.h	/^        int	*fl_varsecsize;	\/* Not NULL, if device has flexable sector size *\/$/;"	m	struct:fl_device
fl_verify_device	dev/flash.c	/^int fl_verify_device(void *fl_base, void *data_base, int data_size, int verbose)$/;"	f
flag	include/pmon.h	/^	int             flag;$/;"	m	struct:Cmd
flags	include/exec.h	/^	int flags;$/;"	m	struct:ExecType
flags	include/ramfile.h	/^	int flags;$/;"	m	struct:Ramfile
flash_type	dev/flash.c	/^static int flash_type=0;$/;"	v	file:
fmov_op	include/ri.h	/^	fmov_op      =  0x06, fneg_op      =  0x07,$/;"	e	enum:cop1_sdw_func
fmovc_op	include/ri.h	/^	fmovc_op     =  0x11, fmovz_op     =  0x12,$/;"	e	enum:cop1_sdw_func
fmovn_op	include/ri.h	/^	fmovn_op     =  0x13, frecip_op    =  0x15,$/;"	e	enum:cop1_sdw_func
fmovz_op	include/ri.h	/^	fmovc_op     =  0x11, fmovz_op     =  0x12,$/;"	e	enum:cop1_sdw_func
fmul_op	include/ri.h	/^	fmul_op      =  0x02, fdiv_op      =  0x03,$/;"	e	enum:cop1_sdw_func
fneg_op	include/ri.h	/^	fmov_op      =  0x06, fneg_op      =  0x07,$/;"	e	enum:cop1_sdw_func
formnames	include/arpa/ftp.h	/^char *formnames[] =  {"0", "Nonprint", "Telnet", "Carriage-control" };$/;"	v
fp_nquery	include/resolv.h	214;"	d
fp_query	include/resolv.h	213;"	d
fp_resstat	include/resolv.h	212;"	d
frecip_op	include/ri.h	/^	fmovn_op     =  0x13, frecip_op    =  0x15,$/;"	e	enum:cop1_sdw_func
free_func	include/linux/zlib.h	/^typedef void   (*free_func)  OF((voidpf opaque, voidpf address));$/;"	t
freq	include/termio.h	/^	unsigned long freq;$/;"	m	struct:ConfigEntry
freq	include/termio.h	/^	unsigned long freq;$/;"	m	struct:DevEntry
fround_op	include/ri.h	/^	fround_op    =  0x0c, ftrunc_op    =  0x0d,$/;"	e	enum:cop1_sdw_func
froundl_op	include/ri.h	/^	froundl_op   =  0x08, ftruncl_op   =  0x09,$/;"	e	enum:cop1_sdw_func
frsqrt_op	include/ri.h	/^	frsqrt_op    =  0x16, fcvts_op     =  0x20,$/;"	e	enum:cop1_sdw_func
fs	include/file.h	/^	FileSystem *fs;$/;"	m	struct:File
fsname	include/diskfs.h	/^	char *fsname;$/;"	m	struct:DiskFileSystem
fsqrt_op	include/ri.h	/^	fsqrt_op     =  0x04, fabs_op      =  0x05,$/;"	e	enum:cop1_sdw_func
fstype	include/file.h	/^	int	fstype;$/;"	m	struct:FileSystem
fsub_op	include/ri.h	/^	fadd_op      =  0x00, fsub_op      =  0x01,$/;"	e	enum:cop1_sdw_func
ftrunc_op	include/ri.h	/^	fround_op    =  0x0c, ftrunc_op    =  0x0d,$/;"	e	enum:cop1_sdw_func
ftruncl_op	include/ri.h	/^	froundl_op   =  0x08, ftruncl_op   =  0x09,$/;"	e	enum:cop1_sdw_func
func	dev/generic_poll.c	/^	int (*func) __P((void *));$/;"	m	struct:poll_handle	file:
func	include/pmon.h	/^	int	       (*func) __P((int, char *[]));$/;"	m	struct:Cmd
functions	include/pflash.h	/^	struct fl_functions *functions;$/;"	m	struct:fl_device	typeref:struct:fl_device::fl_functions
get_crt_reg	dev/vgacon.c	/^unsigned char get_crt_reg(unsigned char index)$/;"	f
get_roundup	dev/flash.c	/^static void get_roundup(void **ori_base, int *ori_size)$/;"	f	file:
getenv	env.c	/^char *getenv (name)$/;"	f
getfield	include/pmon.h	381;"	d
gethex	lib.c	/^int gethex (int32_t * vp, char *p, int n)$/;"	f
getstdenv	env.c	/^static const struct stdenv *getstdenv (name)$/;"	f	file:
getword	lib.c	/^char *getword (char *dst, const char *p)$/;"	f
gid_t	include/types.h	/^typedef	u_int32_t	gid_t;		\/* group id *\/$/;"	t
h_addr	include/netdb.h	100;"	d
h_addr_list	include/netdb.h	/^	char	**h_addr_list;	\/* list of addresses from name server *\/$/;"	m	struct:hostent
h_addrtype	include/netdb.h	/^	int	h_addrtype;	\/* host address type *\/$/;"	m	struct:hostent
h_aliases	include/netdb.h	/^	char	**h_aliases;	\/* alias list *\/$/;"	m	struct:hostent
h_length	include/netdb.h	/^	int	h_length;	\/* length of address *\/$/;"	m	struct:hostent
h_name	include/netdb.h	/^	char	*h_name;	\/* official name of host *\/$/;"	m	struct:hostent
handle_kbd_event	dev/kbd.c	/^static unsigned char handle_kbd_event (void)$/;"	f	file:
handle_keyboard_event	dev/kbd.c	/^static inline void handle_keyboard_event (unsigned char scancode)$/;"	f	file:
handle_scancode	dev/kbd.c	/^void handle_scancode (unsigned char scancode, int down)$/;"	f
handler	include/termio.h	/^	int(*handler) (int, struct DevEntry *, unsigned long, int);$/;"	m	struct:ConfigEntry
handler	include/termio.h	/^	int(*handler) (int, struct DevEntry *, unsigned long, int);$/;"	m	struct:DevEntry
hi	include/ri.h	/^	unsigned long hi;$/;"	m	struct:pt_regs
hostalias	include/resolv.h	215;"	d
hostent	include/netdb.h	/^struct	hostent {$/;"	s
hostname	include/url.h	/^	char		hostname[HOSTNAMESIZE];$/;"	m	struct:Url
howmany	include/types.h	201;"	d
humanname	include/resolv.h	/^	char *	humanname;	\/* Its fun name, like "mail exchanger" *\/$/;"	m	struct:res_sym
hwethadr	tgt_env.c	/^unsigned char hwethadr[6];$/;"	v
iFunc	include/stdio.h	/^typedef int iFunc __P((void));$/;"	t
i_next	include/diskfs.h	/^	SLIST_ENTRY(DiskFileSystem)	i_next;$/;"	m	struct:DiskFileSystem
i_next	include/exec.h	/^	SLIST_ENTRY(ExecType)	i_next;$/;"	m	struct:ExecType
i_next	include/file.h	/^	SLIST_ENTRY(FileSystem)	i_next;$/;"	m	struct:FileSystem
i_next	include/ramfile.h	/^	LIST_ENTRY(Ramfile)	i_next;$/;"	m	struct:Ramfile
id	include/arpa/nameser.h	/^	unsigned	id :16;		\/* query identification number *\/$/;"	m	struct:__anon3
id	include/resolv.h	/^	u_short	id;			\/* current message id *\/$/;"	m	struct:__res_state
in16	include/tgt/pio.h	47;"	d
in16rb	include/tgt/pio.h	55;"	d
in32	include/tgt/pio.h	49;"	d
in32rb	include/tgt/pio.h	56;"	d
in8	include/tgt/pio.h	45;"	d
in8rb	include/tgt/pio.h	54;"	d
in_addr_t	include/types.h	/^typedef u_int32_t	in_addr_t;	\/* base type for internet address *\/$/;"	t
in_port_t	include/types.h	/^typedef u_int16_t	in_port_t;	\/* IP port type *\/$/;"	t
inb	include/tgt/pio.h	44;"	d
incmod	include/pmon.h	389;"	d
index_cursor_pos_hi	dev/vgacon.c	8;"	d	file:
index_cursor_pos_lo	dev/vgacon.c	9;"	d	file:
init	env.c	/^	char *init;$/;"	m	struct:stdenv	file:
init_cmd	cmd_env.c	/^static void init_cmd ()$/;"	f	file:
init_cmd	help.c	/^static void init_cmd ()$/;"	f	file:
init_cmd	main.c	/^static void init_cmd ()$/;"	f	file:
init_cmd	program.c	/^static void init_cmd ()$/;"	f	file:
inited	include/pflash.h	/^	int inited;$/;"	m	struct:fl_map
inl	include/tgt/pio.h	48;"	d
inline	include/cdefs.h	106;"	d
inline	include/types.h	81;"	d
inputbuf	dev/kbd.c	/^char inputbuf[300];$/;"	v
int16_t	include/types.h	/^typedef	short			  int16_t;$/;"	t
int32_t	include/types.h	/^typedef	int			  int32_t;$/;"	t
int64_t	include/types.h	/^typedef	long long		  int64_t;$/;"	t
int8_t	include/types.h	/^typedef	__signed char		   int8_t;$/;"	t
internal_state	include/linux/zlib.h	/^    struct internal_state {int dummy;}; \/* hack for buggy compilers *\/$/;"	s
intf	include/linux/zconf.h	/^typedef int   FAR intf;$/;"	t
intr	include/termio.h	/^	struct jmp_buf *intr;$/;"	m	struct:DevEntry	typeref:struct:DevEntry::jmp_buf
intr_handler_t	include/autoconf.h	/^typedef int (*intr_handler_t) __P((void *));$/;"	t
inw	include/tgt/pio.h	46;"	d
ioctl	include/diskfs.h	/^	int (*ioctl) __P((int , unsigned long , ...));$/;"	m	struct:DiskFileSystem
ioctl	include/file.h	/^	int	(*ioctl) (int , unsigned long , ...);$/;"	m	struct:FileSystem
ioh_cf8	dev/pcibrvar.h	/^	bus_space_handle_t	ioh_cf8;$/;"	m	struct:pcibr_config
ioh_cfc	dev/pcibrvar.h	/^	bus_space_handle_t	ioh_cfc;$/;"	m	struct:pcibr_config
isalnum	include/ctype.h	93;"	d
isalpha	include/ctype.h	91;"	d
isascii	include/ctype.h	104;"	d
isblank	include/ctype.h	102;"	d
isbusy	include/pflash.h	/^	int	(*isbusy)		\/* Check if device is Busy *\/$/;"	m	struct:fl_functions
iscntrl	include/ctype.h	96;"	d
isdigit	include/ctype.h	86;"	d
isgraph	include/ctype.h	95;"	d
islower	include/ctype.h	87;"	d
isprint	include/ctype.h	94;"	d
ispunct	include/ctype.h	89;"	d
isspace	include/ctype.h	88;"	d
isupper	include/ctype.h	90;"	d
isxdigit	include/ctype.h	92;"	d
j_op	include/ri.h	/^	spec_op, bcond_op, j_op, jal_op,$/;"	e	enum:major_op
jal_op	include/ri.h	/^	spec_op, bcond_op, j_op, jal_op,$/;"	e	enum:major_op
jalr_op	include/ri.h	/^	jr_op, jalr_op, movz_op, movn_op,$/;"	e	enum:spec_op
jalx_op	include/ri.h	/^	major_1c_op, jalx_op, major_1e_op, major_1f_op,$/;"	e	enum:major_op
jmp_buf	include/setjmp.h	/^typedef long jmp_buf[_JBLEN];$/;"	t
jr_op	include/ri.h	/^	jr_op, jalr_op, movz_op, movn_op,$/;"	e	enum:spec_op
k_hand	dev/kbd.c	/^typedef void (*k_hand) (unsigned char value, char up_flag);$/;"	t	file:
k_handfn	dev/kbd.c	/^typedef void (k_handfn) (unsigned char value, char up_flag);$/;"	t	file:
kbd_clear_input	dev/kbd.c	/^static void kbd_clear_input (void)$/;"	f	file:
kbd_code	dev/kbd.c	/^unsigned char kbd_code;$/;"	v
kbd_error_msgs	dev/kbd.c	/^const char *kbd_error_msgs[] = {$/;"	v
kbd_initialize	dev/kbd.c	/^int kbd_initialize (void)$/;"	f
kbd_poll	dev/kbd.c	/^void kbd_poll ()$/;"	f
kbd_read_data	dev/kbd.c	/^static int kbd_read_data (void)$/;"	f	file:
kbd_read_input	dev/kbd.h	15;"	d
kbd_read_status	dev/kbd.h	16;"	d
kbd_translate	dev/kbd.c	/^int kbd_translate (unsigned char scancode, unsigned char *keycode)$/;"	f
kbd_wait	dev/kbd.c	/^static void kbd_wait (void)$/;"	f	file:
kbd_wait_for_input	dev/kbd.c	/^static int kbd_wait_for_input (void)$/;"	f	file:
kbd_write_command	dev/kbd.h	18;"	d
kbd_write_command_w	dev/kbd.c	/^static void kbd_write_command_w (int data)$/;"	f	file:
kbd_write_command_w_and_wait	dev/kbd.c	/^static int kbd_write_command_w_and_wait (int data)$/;"	f	file:
kbd_write_output	dev/kbd.h	17;"	d
kbd_write_output_w	dev/kbd.c	/^static void kbd_write_output_w (int data)$/;"	f	file:
kbd_write_output_w_and_wait	dev/kbd.c	/^static int kbd_write_output_w_and_wait (int data)$/;"	f	file:
kbdin	include/stdio.h	81;"	d
key_handler	dev/kbd.c	/^static k_hand key_handler[16] = {$/;"	v	file:
key_maps	dev/kbd.h	/^ushort *key_maps[MAX_NR_KEYMAPS] = {$/;"	v
keymap_count	dev/kbd.h	/^unsigned int keymap_count = 3;$/;"	v
l_fmt	include/ri.h	/^	w_fmt, l_fmt$/;"	e	enum:cop1_fmt
label_t	include/types.h	/^typedef struct label_t {$/;"	s
label_t	include/types.h	/^} label_t;$/;"	t	typeref:struct:label_t
lb_op	include/ri.h	/^	lb_op, lh_op, lwl_op, lw_op,$/;"	e	enum:major_op
lbu_op	include/ri.h	/^	lbu_op, lhu_op, lwr_op, lwu_op,$/;"	e	enum:major_op
lc_iot	dev/pcibrvar.h	/^	bus_space_tag_t lc_iot;$/;"	m	struct:pcibr_config
lc_memt	dev/pcibrvar.h	/^	bus_space_tag_t lc_memt;$/;"	m	struct:pcibr_config
ld_op	include/ri.h	/^	lld_op, ldc1_op, ldc2_op, ld_op,$/;"	e	enum:major_op
ldc1_op	include/ri.h	/^	lld_op, ldc1_op, ldc2_op, ld_op,$/;"	e	enum:major_op
ldc2_op	include/ri.h	/^	lld_op, ldc1_op, ldc2_op, ld_op,$/;"	e	enum:major_op
ldiv_t	include/stdlib.h	/^} ldiv_t;$/;"	t	typeref:struct:__anon7
ldl_op	include/ri.h	/^	daddi_op, daddiu_op, ldl_op, ldr_op,$/;"	e	enum:major_op
ldr_op	include/ri.h	/^	daddi_op, daddiu_op, ldl_op, ldr_op,$/;"	e	enum:major_op
ldxc1_op	include/ri.h	/^	lwxc1_op     =  0x00, ldxc1_op     =  0x01,$/;"	e	enum:cop1x_func
led_status	dev/kbd.c	/^unsigned char led_status = 0;$/;"	v
level	dev/generic_poll.c	/^	int level;$/;"	m	struct:poll_handle	file:
lh_op	include/ri.h	/^	lb_op, lh_op, lwl_op, lw_op,$/;"	e	enum:major_op
lhu_op	include/ri.h	/^	lbu_op, lhu_op, lwr_op, lwu_op,$/;"	e	enum:major_op
limit	include/queue.h	/^	unsigned short limit;$/;"	m	struct:Queue
linux_inb	include/tgt/io.h	/^static inline unsigned char linux_inb(unsigned long port)$/;"	f
linux_inb_p	include/tgt/io.h	/^static inline unsigned char linux_inb_p(unsigned long port)$/;"	f
linux_inl	include/tgt/io.h	/^static inline unsigned int linux_inl(unsigned long port)$/;"	f
linux_inw	include/tgt/io.h	/^static inline unsigned short linux_inw(unsigned long port)$/;"	f
linux_outb	include/tgt/io.h	28;"	d
linux_outb_p	include/tgt/io.h	43;"	d
linux_outl	include/tgt/io.h	38;"	d
linux_outw	include/tgt/io.h	33;"	d
ll_op	include/ri.h	/^	ll_op, lwc1_op, lwc2_op, pref_op,$/;"	e	enum:major_op
lld_op	include/ri.h	/^	lld_op, ldc1_op, ldc2_op, ld_op,$/;"	e	enum:major_op
lo	include/ri.h	/^	unsigned long lo;$/;"	m	struct:pt_regs
load_byte	include/pmon.h	382;"	d
load_dword	include/pmon.h	385;"	d
load_half	include/pmon.h	383;"	d
load_reg	include/pmon.h	386;"	d
load_word	include/pmon.h	384;"	d
loader	include/exec.h	/^	long (*loader) __P((int , char *, int *, int ));$/;"	m	struct:ExecType
loc_aton	include/resolv.h	210;"	d
loc_ntoa	include/resolv.h	209;"	d
local	include/linux/zutil.h	22;"	d
lookups	include/resolv.h	/^	char    lookups[MAXDNSLUS];$/;"	m	struct:__res_state
lseek	include/diskfs.h	/^	off_t (*lseek) __P((int , off_t, int));$/;"	m	struct:DiskFileSystem
lseek	include/file.h	/^	off_t	(*lseek) (int , off_t, int);$/;"	m	struct:FileSystem
lui_op	include/ri.h	/^	andi_op, ori_op, xori_op, lui_op,$/;"	e	enum:major_op
lw_op	include/ri.h	/^	lb_op, lh_op, lwl_op, lw_op,$/;"	e	enum:major_op
lwc1_op	include/ri.h	/^	ll_op, lwc1_op, lwc2_op, pref_op,$/;"	e	enum:major_op
lwc2_op	include/ri.h	/^	ll_op, lwc1_op, lwc2_op, pref_op,$/;"	e	enum:major_op
lwl_op	include/ri.h	/^	lb_op, lh_op, lwl_op, lw_op,$/;"	e	enum:major_op
lwr_op	include/ri.h	/^	lbu_op, lhu_op, lwr_op, lwu_op,$/;"	e	enum:major_op
lwu_op	include/ri.h	/^	lbu_op, lhu_op, lwr_op, lwu_op,$/;"	e	enum:major_op
lwxc1_op	include/ri.h	/^	lwxc1_op     =  0x00, ldxc1_op     =  0x01,$/;"	e	enum:cop1x_func
mad_func	include/ri.h	/^enum mad_func {$/;"	g
madd_d_op	include/ri.h	/^	madd_d_op    =  0x21, madd_e_op    =  0x22,$/;"	e	enum:cop1x_func
madd_e_op	include/ri.h	/^	madd_d_op    =  0x21, madd_e_op    =  0x22,$/;"	e	enum:cop1x_func
madd_op	include/ri.h	/^	madd_op      = 0x08, msub_op      = 0x0a,$/;"	e	enum:mad_func
madd_s_op	include/ri.h	/^	sdxc1_op     =  0x09, madd_s_op    =  0x20,$/;"	e	enum:cop1x_func
main	main.c	/^int main (int argc, char *argv[])$/;"	f
mainbus_attach	dev/mainbus.c	/^static void mainbus_attach(parent, self, aux)$/;"	f	file:
mainbus_ca	dev/mainbus.c	/^struct cfattach mainbus_ca = {$/;"	v	typeref:struct:cfattach
mainbus_cd	dev/mainbus.c	/^struct cfdriver mainbus_cd = {$/;"	v	typeref:struct:cfdriver
mainbus_match	dev/mainbus.c	/^static int mainbus_match(parent, match, aux)$/;"	f	file:
mainbus_softc	dev/mainbus.c	/^struct mainbus_softc {$/;"	s	file:
maincpu	include/pmon.h	394;"	d
major_1c_op	include/ri.h	/^	major_1c_op, jalx_op, major_1e_op, major_1f_op,$/;"	e	enum:major_op
major_1e_op	include/ri.h	/^	major_1c_op, jalx_op, major_1e_op, major_1f_op,$/;"	e	enum:major_op
major_1f_op	include/ri.h	/^	major_1c_op, jalx_op, major_1e_op, major_1f_op,$/;"	e	enum:major_op
major_3b_op	include/ri.h	/^	sc_op, swc1_op, swc2_op, major_3b_op, \/* Opcode 0x3b is unused *\/$/;"	e	enum:major_op
major_op	include/ri.h	/^enum major_op {$/;"	g
mapenv	env.c	/^void mapenv (pfunc)$/;"	f
mask	include/resolv.h	/^		u_int32_t	mask;$/;"	m	struct:__res_state::__anon4
matchenv	env.c	/^int matchenv (name)$/;"	f
maxac	include/pmon.h	/^	int             maxac;$/;"	m	struct:Cmd
mb_matchname	dev/mainbus.c	/^static int mb_matchname(ca, name)$/;"	f	file:
mbprint	dev/mainbus.c	/^static int mbprint(aux, pnp)$/;"	f	file:
mdelay	dev/kbd.c	895;"	d	file:
mem_alloc_start	dev/pcibrvar.h	/^	u_int32_t mem_alloc_start;$/;"	m	struct:pcibr_softc
membase	main.c	/^unsigned int mips_io_port_base, membase;$/;"	v
mfc_op	include/ri.h	/^	mfc_op        = 0x00, dmfc_op       = 0x01,$/;"	e	enum:cop_op
mfhi_op	include/ri.h	/^	mfhi_op, mthi_op, mflo_op, mtlo_op,$/;"	e	enum:spec_op
mflo_op	include/ri.h	/^	mfhi_op, mthi_op, mflo_op, mtlo_op,$/;"	e	enum:spec_op
minac	include/pmon.h	/^	int             minac;$/;"	m	struct:Cmd
mips_instruction	include/ri.h	/^typedef unsigned int mips_instruction;$/;"	t
mips_io_port_base	main.c	/^unsigned int mips_io_port_base, membase;$/;"	v
modenames	include/arpa/ftp.h	/^char *modenames[] =  {"0", "Stream", "Block", "Compressed" };$/;"	v
more	env.c	/^int more (p, cnt, size)$/;"	f
moresz	env.c	/^unsigned int moresz = 10;$/;"	v
movc_op	include/ri.h	/^	sll_op, movc_op, srl_op, sra_op,$/;"	e	enum:spec_op
movequad	include/tgt/pio.h	57;"	d
movn_op	include/ri.h	/^	jr_op, jalr_op, movz_op, movn_op,$/;"	e	enum:spec_op
movz_op	include/ri.h	/^	jr_op, jalr_op, movz_op, movn_op,$/;"	e	enum:spec_op
msg	include/linux/zlib.h	/^    char     *msg;      \/* last error message, NULL if no error *\/$/;"	m	struct:z_stream_s
msub_d_op	include/ri.h	/^	msub_s_op    =  0x28, msub_d_op    =  0x29,$/;"	e	enum:cop1x_func
msub_e_op	include/ri.h	/^	msub_e_op    =  0x2a, nmadd_s_op   =  0x30,$/;"	e	enum:cop1x_func
msub_op	include/ri.h	/^	madd_op      = 0x08, msub_op      = 0x0a,$/;"	e	enum:mad_func
msub_s_op	include/ri.h	/^	msub_s_op    =  0x28, msub_d_op    =  0x29,$/;"	e	enum:cop1x_func
mtc_op	include/ri.h	/^	cfc_op        = 0x02, mtc_op        = 0x04,$/;"	e	enum:cop_op
mthi_op	include/ri.h	/^	mfhi_op, mthi_op, mflo_op, mtlo_op,$/;"	e	enum:spec_op
mtlo_op	include/ri.h	/^	mfhi_op, mthi_op, mflo_op, mtlo_op,$/;"	e	enum:spec_op
mult_op	include/ri.h	/^	mult_op, multu_op, div_op, divu_op,$/;"	e	enum:spec_op
multu_op	include/ri.h	/^	mult_op, multu_op, div_op, divu_op,$/;"	e	enum:spec_op
n_addrtype	include/netdb.h	/^	int		n_addrtype;	\/* net address type *\/$/;"	m	struct:netent
n_aliases	include/netdb.h	/^	char		**n_aliases;	\/* alias list *\/$/;"	m	struct:netent
n_name	include/netdb.h	/^	char		*n_name;	\/* official name of net *\/$/;"	m	struct:netent
n_net	include/netdb.h	/^	in_addr_t	n_net;		\/* network # *\/$/;"	m	struct:netent
name	dev/pcibrvar.h	/^	char *name;$/;"	m	struct:pci_reserve_mem
name	env.c	/^	char *name;$/;"	m	struct:stdenv	file:
name	include/pmon.h	/^	const char     *name;$/;"	m	struct:Cmd
name	include/pmon.h	/^    char            name[10];$/;"	m	struct:Stopentry
name	include/pmon.h	/^    const char     *name;$/;"	m	struct:Demo
name	include/pmon.h	/^    const char     *name;$/;"	m	struct:Optdesc
name	include/pmonenv.h	/^    char	*name;$/;"	m	struct:envpair
name	include/ramfile.h	/^	char name[26];$/;"	m	struct:Ramfile
name	include/resolv.h	/^	char *	name;		\/* Its symbolic name, like "MX" *\/$/;"	m	struct:res_sym
nbogus	dev/pcibrvar.h	/^	int nbogus;$/;"	m	struct:pcibr_softc
ndots	include/resolv.h	/^	unsigned ndots:4;		\/* threshold for initial abs. query *\/$/;"	m	struct:__res_state
netent	include/netdb.h	/^struct	netent {$/;"	s
next	dev/generic_poll.c	/^	struct poll_handle *next;$/;"	m	struct:poll_handle	typeref:struct:poll_handle::poll_handle	file:
next_in	include/linux/zlib.h	/^    Bytef    *next_in;  \/* next input byte *\/$/;"	m	struct:z_stream_s
next_out	include/linux/zlib.h	/^    Bytef    *next_out; \/* next output byte should be put there *\/$/;"	m	struct:z_stream_s
nmadd_d_op	include/ri.h	/^	nmadd_d_op   =  0x31, nmadd_e_op   =  0x32,$/;"	e	enum:cop1x_func
nmadd_e_op	include/ri.h	/^	nmadd_d_op   =  0x31, nmadd_e_op   =  0x32,$/;"	e	enum:cop1x_func
nmadd_op	include/ri.h	/^	nmadd_op     = 0x0c, nmsub_op     = 0x0e$/;"	e	enum:mad_func
nmadd_s_op	include/ri.h	/^	msub_e_op    =  0x2a, nmadd_s_op   =  0x30,$/;"	e	enum:cop1x_func
nmsub_d_op	include/ri.h	/^	nmsub_s_op   =  0x38, nmsub_d_op   =  0x39,$/;"	e	enum:cop1x_func
nmsub_e_op	include/ri.h	/^	nmsub_e_op   =  0x3a$/;"	e	enum:cop1x_func
nmsub_op	include/ri.h	/^	nmadd_op     = 0x0c, nmsub_op     = 0x0e$/;"	e	enum:mad_func
nmsub_s_op	include/ri.h	/^	nmsub_s_op   =  0x38, nmsub_d_op   =  0x39,$/;"	e	enum:cop1x_func
node	dev/pcibrvar.h	/^	int     node;$/;"	m	struct:pcibr_config
nopen	include/termio.h	/^	int nopen;$/;"	m	struct:DevEntry
nor_op	include/ri.h	/^	and_op, or_op, xor_op, nor_op,$/;"	e	enum:spec_op
ns16550	dev/ns16550.c	/^int ns16550(int op, struct DevEntry *dev, unsigned long param, int data)$/;"	f
ns16550dev	dev/ns16550.h	/^} ns16550dev;$/;"	t	typeref:struct:__anon1
nsaddr	include/resolv.h	115;"	d
nsaddr_list	include/resolv.h	/^		nsaddr_list[MAXNS];	\/* address of name server *\/$/;"	m	struct:__res_state	typeref:struct:__res_state::sockaddr_in
nscount	include/arpa/nameser.h	/^	unsigned	nscount :16;	\/* number of authority entries *\/$/;"	m	struct:__anon3
nscount	include/resolv.h	/^	int	nscount;		\/* number of name servers *\/$/;"	m	struct:__res_state
nsinit	dev/ns16550.c	/^static int nsinit(volatile ns16550dev * dp)$/;"	f	file:
nsort	include/resolv.h	/^	unsigned nsort:4;		\/* number of elements in sort_list[] *\/$/;"	m	struct:__res_state
nsprogram	dev/ns16550.c	/^static int nsprogram(volatile ns16550dev * dp, unsigned long freq, int baudrate)$/;"	f	file:
nsreg	dev/ns16550.h	44;"	d
num_lock_status	dev/kbd.c	/^unsigned char num_lock_status = 0;$/;"	v
number	include/resolv.h	/^	int	number;		\/* Identifying number, like T_MX *\/$/;"	m	struct:res_sym
nvram_disable	dev/fl_nvram.c	/^static void nvram_disable()$/;"	f	file:
nvram_enable	dev/fl_nvram.c	/^static void nvram_enable()$/;"	f	file:
nvram_get	tgt_env.c	/^void nvram_get (char *buffer)$/;"	f
nvram_invalid	dev/fl_nvram.c	/^static int nvram_invalid = 0;$/;"	v	file:
nvram_invalid	tgt_env.c	/^static int nvram_invalid = 0;$/;"	v	file:
nvram_put	tgt_env.c	/^void nvram_put (char *buffer)$/;"	f
offsetof	include/stddef.h	60;"	d
opcode	include/arpa/nameser.h	/^	unsigned	opcode :4;	\/* purpose of message *\/$/;"	m	struct:__anon3
opcode	include/arpa/nameser.h	/^	unsigned	opcode: 4;	\/* purpose of message *\/$/;"	m	struct:__anon3
open	include/diskfs.h	/^	int (*open) __P((int, const char *, int, int));$/;"	m	struct:DiskFileSystem
open	include/file.h	/^	int	(*open) (int, const char *, int, int);$/;"	m	struct:FileSystem
optdesc	include/pmon.h	/^	const Optdesc  *optdesc;$/;"	m	struct:Cmd
options	include/resolv.h	/^	u_long	options;		\/* option flags - see below. *\/$/;"	m	struct:__res_state
opts	include/pmon.h	/^	const char     *opts;$/;"	m	struct:Cmd
or_op	include/ri.h	/^	and_op, or_op, xor_op, nor_op,$/;"	e	enum:spec_op
ori_op	include/ri.h	/^	andi_op, ori_op, xori_op, lui_op,$/;"	e	enum:major_op
out16	include/tgt/pio.h	41;"	d
out16rb	include/tgt/pio.h	52;"	d
out32	include/tgt/pio.h	43;"	d
out32rb	include/tgt/pio.h	53;"	d
out8	include/tgt/pio.h	39;"	d
out8rb	include/tgt/pio.h	51;"	d
outb	include/tgt/pio.h	38;"	d
outl	include/tgt/pio.h	42;"	d
outw	include/tgt/pio.h	40;"	d
p_aliases	include/netdb.h	/^	char	**p_aliases;	\/* alias list *\/$/;"	m	struct:protoent
p_cdname	include/resolv.h	223;"	d
p_cdnname	include/resolv.h	222;"	d
p_class	include/resolv.h	218;"	d
p_fqname	include/resolv.h	225;"	d
p_fqnname	include/resolv.h	224;"	d
p_name	include/netdb.h	/^	char	*p_name;	\/* official protocol name *\/$/;"	m	struct:protoent
p_option	include/resolv.h	227;"	d
p_proto	include/netdb.h	/^	int	p_proto;	\/* protocol # *\/$/;"	m	struct:protoent
p_query	include/resolv.h	221;"	d
p_rr	include/resolv.h	226;"	d
p_secstodate	include/resolv.h	228;"	d
p_time	include/resolv.h	219;"	d
p_type	include/resolv.h	220;"	d
pad	include/resolv.h	/^	char	pad[68];		\/* on an i386 this means 512b total *\/$/;"	m	struct:__res_state
pad0	include/ri.h	/^	unsigned long pad0[6];$/;"	m	struct:pt_regs
paddr_t	include/types.h	/^typedef unsigned long	paddr_t;$/;"	t
password	include/url.h	/^	char		password[PASSWORDSIZE];$/;"	m	struct:Url
pci_init_done	dev/pcibrvar.h	/^	int	pci_init_done;$/;"	m	struct:pcibr_config
pci_reserve_mem	dev/pcibrvar.h	/^struct pci_reserve_mem {$/;"	s
pcibr_ca	dev/pcibr.c	/^struct cfattach pcibr_ca = {$/;"	v	typeref:struct:cfattach
pcibr_cd	dev/pcibr.c	/^struct cfdriver pcibr_cd = {$/;"	v	typeref:struct:cfdriver
pcibr_config	dev/pcibrvar.h	/^	struct pcibr_config	pcibr_config;$/;"	m	struct:pcibr_softc	typeref:struct:pcibr_softc::pcibr_config
pcibr_config	dev/pcibrvar.h	/^struct pcibr_config {$/;"	s
pcibr_softc	dev/pcibrvar.h	/^struct pcibr_softc {$/;"	s
pcibrattach	dev/pcibr.c	/^void pcibrattach(parent, self, aux)$/;"	f
pcibrmatch	dev/pcibr.c	/^int pcibrmatch(parent, match, aux)$/;"	f
pcibrprint	dev/pcibr.c	/^static int pcibrprint(aux, pnp)$/;"	f	file:
pckbd_leds	dev/kbd.c	/^void pckbd_leds (unsigned char leds)$/;"	f
pfcode	include/resolv.h	/^	u_long	pfcode;			\/* RES_PRF_ flags - see below. *\/$/;"	m	struct:__res_state
pfetch_op	include/ri.h	/^	pfetch_op    =  0x07, swxc1_op     =  0x08,$/;"	e	enum:cop1x_func
physadr	include/types.h	/^} *physadr;$/;"	t	typeref:struct:_physadr
pid_t	include/types.h	/^typedef	int32_t		pid_t;		\/* process id *\/$/;"	t
plain_map	dev/kbd.h	/^u_short plain_map[NR_KEYS] = {$/;"	v
poll_handle	dev/generic_poll.c	/^struct poll_handle {$/;"	s	file:
poll_list	dev/generic_poll.c	/^struct poll_handle *poll_list;$/;"	v	typeref:struct:poll_handle
port_alloc_start	dev/pcibrvar.h	/^	u_int32_t port_alloc_start;$/;"	m	struct:pcibr_softc
posn	include/file.h	/^	unsigned long posn;$/;"	m	struct:File
pref_op	include/ri.h	/^	ll_op, lwc1_op, lwc2_op, pref_op,$/;"	e	enum:major_op
prhelp	help.c	/^prhelp (const Cmd * cmd, int *lnp, int siz, int namemax, int optsmax)$/;"	f	file:
printvar	env.c	/^int printvar (name, value, cntp)$/;"	f
program	include/pflash.h	/^	int	(*program)		\/* Program Device *\/$/;"	m	struct:fl_functions
protocol	include/url.h	/^	char		protocol[PROTOCOLSIZE];$/;"	m	struct:Url
protoent	include/netdb.h	/^struct	protoent {$/;"	s
psize_t	include/types.h	/^typedef unsigned long	psize_t;$/;"	t
pt_regs	include/ri.h	/^struct pt_regs {$/;"	s
ptrdiff_t	include/stddef.h	/^typedef	_BSD_PTRDIFF_T_	ptrdiff_t;$/;"	t
putlong	include/resolv.h	216;"	d
putshort	include/resolv.h	217;"	d
q_fmt	include/ri.h	/^	s_fmt, d_fmt, e_fmt, q_fmt,$/;"	e	enum:cop1_fmt
qaddr_t	include/types.h	/^typedef	quad_t *	qaddr_t;$/;"	t
qdcount	include/arpa/nameser.h	/^	unsigned	qdcount :16;	\/* number of question entries *\/$/;"	m	struct:__anon3
qdiv_t	include/stdlib.h	/^} qdiv_t;$/;"	t	typeref:struct:__anon8
qr	include/arpa/nameser.h	/^	unsigned	qr :1;		\/* response flag *\/$/;"	m	struct:__anon3
qr	include/arpa/nameser.h	/^	unsigned	qr: 1;		\/* response flag *\/$/;"	m	struct:__anon3
qsize	include/termio.h	/^	int qsize;$/;"	m	struct:DevEntry
quad_t	include/types.h	/^typedef	int64_t		quad_t;$/;"	t
quitnow	main.c	/^static int quitnow = 0;$/;"	v	file:
quot	include/stdlib.h	/^	int quot;		\/* quotient *\/$/;"	m	struct:__anon6
quot	include/stdlib.h	/^	long quot;		\/* quotient *\/$/;"	m	struct:__anon7
quot	include/stdlib.h	/^	quad_t quot;		\/* quotient *\/$/;"	m	struct:__anon8
r	include/types.h	/^	int r[1];$/;"	m	struct:_physadr
ra	include/arpa/nameser.h	/^	unsigned	ra :1;		\/* recursion available *\/$/;"	m	struct:__anon3
ra	include/arpa/nameser.h	/^	unsigned	ra: 1;		\/* recursion available *\/$/;"	m	struct:__anon3
rcode	include/arpa/nameser.h	/^	unsigned	rcode :4;	\/* response code *\/$/;"	m	struct:__anon3
rd	include/arpa/nameser.h	/^	unsigned	rd :1;		\/* recursion desired *\/$/;"	m	struct:__anon3
rd	include/arpa/nameser.h	/^	unsigned	rd: 1;		\/* recursion desired *\/$/;"	m	struct:__anon3
read	include/diskfs.h	/^	int (*read) __P((int , void *, size_t));$/;"	m	struct:DiskFileSystem
read	include/file.h	/^	int	(*read) (int , void *, size_t);$/;"	m	struct:FileSystem
readb	include/tgt/io.h	62;"	d
readl	include/tgt/io.h	64;"	d
readw	include/tgt/io.h	63;"	d
refs	include/ramfile.h	/^	int refs;$/;"	m	struct:Ramfile
reg	dev/mpc106reg.h	/^	u_int32_t reg;$/;"	v
register_t	include/types.h	/^typedef int32_t		       register_t;$/;"	t
register_t	include/types.h	/^typedef int64_t		       register_t;$/;"	t
regs	include/ri.h	/^	unsigned long regs[32];$/;"	m	struct:pt_regs
rem	include/stdlib.h	/^	int rem;		\/* remainder *\/$/;"	m	struct:__anon6
rem	include/stdlib.h	/^	long rem;		\/* remainder *\/$/;"	m	struct:__anon7
rem	include/stdlib.h	/^	quad_t rem;		\/* remainder *\/$/;"	m	struct:__anon8
repeating_cmd	cmdparser.c	/^int repeating_cmd;$/;"	v
reply_expected	dev/kbd.c	/^static volatile unsigned char reply_expected;$/;"	v	file:
res_close	include/resolv.h	236;"	d
res_dnok	include/resolv.h	203;"	d
res_done	include/resolv.h	/^typedef enum { res_goahead, res_nextns, res_modified, res_done, res_error }$/;"	e	enum:__anon5
res_error	include/resolv.h	/^typedef enum { res_goahead, res_nextns, res_modified, res_done, res_error }$/;"	e	enum:__anon5
res_goahead	include/resolv.h	/^typedef enum { res_goahead, res_nextns, res_modified, res_done, res_error }$/;"	e	enum:__anon5
res_hnok	include/resolv.h	200;"	d
res_init	include/resolv.h	240;"	d
res_isourserver	include/resolv.h	233;"	d
res_mailok	include/resolv.h	202;"	d
res_mkquery	include/resolv.h	244;"	d
res_modified	include/resolv.h	/^typedef enum { res_goahead, res_nextns, res_modified, res_done, res_error }$/;"	e	enum:__anon5
res_nameinquery	include/resolv.h	234;"	d
res_nextns	include/resolv.h	/^typedef enum { res_goahead, res_nextns, res_modified, res_done, res_error }$/;"	e	enum:__anon5
res_ownok	include/resolv.h	201;"	d
res_queriesmatch	include/resolv.h	235;"	d
res_query	include/resolv.h	241;"	d
res_querydomain	include/resolv.h	243;"	d
res_randomid	include/resolv.h	231;"	d
res_search	include/resolv.h	242;"	d
res_send	include/resolv.h	232;"	d
res_send_qhook	include/resolv.h	/^typedef res_sendhookact (*res_send_qhook)__P((struct sockaddr_in * const *ns,$/;"	t
res_send_rhook	include/resolv.h	/^typedef res_sendhookact (*res_send_rhook)__P((const struct sockaddr_in *ns,$/;"	t
res_sendhookact	include/resolv.h	/^	res_sendhookact;$/;"	t	typeref:enum:__anon5
res_sym	include/resolv.h	/^struct res_sym {$/;"	s
resend	dev/kbd.c	/^static volatile unsigned char resend;$/;"	v	file:
reserved	include/linux/zlib.h	/^    uLong   reserved;   \/* reserved for future use *\/$/;"	m	struct:z_stream_s
reset	include/pflash.h	/^	int	(*reset)		\/* Reset Chip *\/$/;"	m	struct:fl_functions
retrans	include/resolv.h	/^	int	retrans;	 	\/* retransmition time interval *\/$/;"	m	struct:__res_state
retry	include/resolv.h	/^	int	retry;			\/* number of times to retransmit *\/$/;"	m	struct:__res_state
rfe_op	include/ri.h	/^	rfe_op        = 0x10, eret_op       = 0x18$/;"	e	enum:cop0_coi_func
rlim_t	include/types.h	/^typedef quad_t		rlim_t;		\/* resource limit *\/$/;"	t
rowcount	dev/vgacon.c	/^int rowcount = 25;$/;"	v
rt_op	include/ri.h	/^enum rt_op {$/;"	g
rxoff	include/termio.h	/^	int rxoff;$/;"	m	struct:DevEntry
rxq	include/termio.h	/^	Queue *rxq;$/;"	m	struct:DevEntry
rxqsize	include/termio.h	/^	int rxqsize;$/;"	m	struct:ConfigEntry
s_aliases	include/netdb.h	/^	char	**s_aliases;	\/* alias list *\/$/;"	m	struct:servent
s_fmt	include/ri.h	/^	s_fmt, d_fmt, e_fmt, q_fmt,$/;"	e	enum:cop1_fmt
s_name	include/netdb.h	/^	char	*s_name;	\/* official service name *\/$/;"	m	struct:servent
s_port	include/netdb.h	/^	int	s_port;		\/* port # *\/$/;"	m	struct:servent
s_proto	include/netdb.h	/^	char	*s_proto;	\/* protocol to use *\/$/;"	m	struct:servent
sa_family_t	include/types.h	/^typedef u_int8_t	sa_family_t;	\/* sockaddr address family type *\/$/;"	t
sb_op	include/ri.h	/^	sb_op, sh_op, swl_op, sw_op,$/;"	e	enum:major_op
sc_bus	dev/mainbus.c	/^	struct bushook sc_bus;$/;"	m	struct:mainbus_softc	typeref:struct:mainbus_softc::bushook	file:
sc_dev	dev/pcibrvar.h	/^	struct device	sc_dev;$/;"	m	struct:pcibr_softc	typeref:struct:pcibr_softc::device
sc_dmatag	dev/pcibrvar.h	/^	struct tgt_bus_dma_tag sc_dmatag;$/;"	m	struct:pcibr_softc	typeref:struct:pcibr_softc::tgt_bus_dma_tag
sc_dv	dev/mainbus.c	/^	struct device sc_dv;$/;"	m	struct:mainbus_softc	typeref:struct:mainbus_softc::device	file:
sc_iobus_space	dev/pcibrvar.h	/^	struct tgt_bus_space sc_iobus_space;$/;"	m	struct:pcibr_softc	typeref:struct:pcibr_softc::tgt_bus_space
sc_membus_space	dev/pcibrvar.h	/^	struct tgt_bus_space sc_membus_space;$/;"	m	struct:pcibr_softc	typeref:struct:pcibr_softc::tgt_bus_space
sc_op	include/ri.h	/^	sc_op, swc1_op, swc2_op, major_3b_op, \/* Opcode 0x3b is unused *\/$/;"	e	enum:major_op
sc_pcibr	dev/pcibrvar.h	/^	struct pcibr_config *sc_pcibr;$/;"	m	struct:pcibr_softc	typeref:struct:pcibr_softc::pcibr_config
scd_op	include/ri.h	/^	scd_op, sdc1_op, sdc2_op, sd_op$/;"	e	enum:major_op
sd_op	include/ri.h	/^	scd_op, sdc1_op, sdc2_op, sd_op$/;"	e	enum:major_op
sdc1_op	include/ri.h	/^	scd_op, sdc1_op, sdc2_op, sd_op$/;"	e	enum:major_op
sdc2_op	include/ri.h	/^	scd_op, sdc1_op, sdc2_op, sd_op$/;"	e	enum:major_op
sdl_op	include/ri.h	/^	sdl_op, sdr_op, swr_op, cache_op,$/;"	e	enum:major_op
sdr_op	include/ri.h	/^	sdl_op, sdr_op, swr_op, cache_op,$/;"	e	enum:major_op
sdxc1_op	include/ri.h	/^	sdxc1_op     =  0x09, madd_s_op    =  0x20,$/;"	e	enum:cop1x_func
secsize_M29W640F16bt	dev/flashdev.c	/^   static const int secsize_M29W640F16bt[] = {$/;"	v	file:
secsize_am29LV008bb	dev/flashdev.c	/^int secsize_am29LV008bb[] =$/;"	v
secsize_am29LV008bt	dev/flashdev.c	/^int secsize_am29LV008bt[] =$/;"	v
segsz_t	include/types.h	/^typedef	int32_t		segsz_t;	\/* segment size *\/$/;"	t
send_data	dev/kbd.c	/^static int send_data (unsigned char data)$/;"	f	file:
sense	include/pmon.h	/^    char            sense;$/;"	m	struct:Stopentry
serialin	include/stdio.h	83;"	d
serialout	include/stdio.h	84;"	d
servent	include/netdb.h	/^struct	servent {$/;"	s
set_crt_reg	dev/vgacon.c	/^void set_crt_reg(unsigned char index, unsigned char data)$/;"	f
set_cursor	dev/vgacon.c	/^void set_cursor(unsigned char x, unsigned char y)$/;"	f
setenv	env.c	/^int setenv (name, value)$/;"	f
sh_op	include/ri.h	/^	sb_op, sh_op, swl_op, sw_op,$/;"	e	enum:major_op
shift_map	dev/kbd.h	/^u_short shift_map[NR_KEYS] = {$/;"	v
shift_state	dev/kbd.c	/^int shift_state = 0;$/;"	v
sigaddset	include/signal.h	/^extern __inline int sigaddset(sigset_t *set, int signo) {$/;"	f
sigdelset	include/signal.h	/^extern __inline int sigdelset(sigset_t *set, int signo) {$/;"	f
sigemptyset	include/signal.h	102;"	d
sigfillset	include/signal.h	103;"	d
sigismember	include/signal.h	/^extern __inline int sigismember(const sigset_t *set, int signo) {$/;"	f
sigjmp_buf	include/setjmp.h	/^typedef long sigjmp_buf[_JBLEN + 1];$/;"	t
signed	include/cdefs.h	107;"	d
signed	include/types.h	82;"	d
sio	include/termio.h	/^	char *sio;$/;"	m	struct:DevEntry
size	dev/pcibrvar.h	/^	bus_size_t size;$/;"	m	struct:pci_reserve_mem
size	include/ramfile.h	/^	unsigned long size;$/;"	m	struct:Ramfile
size_t	include/stddef.h	/^typedef	_BSD_SIZE_T_	size_t;$/;"	t
size_t	include/stdio.h	/^typedef _BSD_SIZE_T_    size_t;$/;"	t
size_t	include/stdlib.h	/^typedef	_BSD_SIZE_T_	size_t;$/;"	t
size_t	include/string.h	/^typedef _BSD_SIZE_T_    size_t;$/;"	t
size_t	include/time.h	/^typedef	_BSD_SIZE_T_	size_t;$/;"	t
slc_names	include/arpa/telnet.h	/^char *slc_names[] = {$/;"	v
sll_op	include/ri.h	/^	sll_op, movc_op, srl_op, sra_op,$/;"	e	enum:spec_op
sllv_op	include/ri.h	/^	sllv_op, srlv_op, srav_op, spec1_unused_op, \/* Opcode 0x07 is unused *\/$/;"	e	enum:spec_op
slt_op	include/ri.h	/^	spec3_unused_op, spec4_unused_op, slt_op, sltu_op,$/;"	e	enum:spec_op
slti_op	include/ri.h	/^	addi_op, addiu_op, slti_op, sltiu_op,$/;"	e	enum:major_op
sltiu_op	include/ri.h	/^	addi_op, addiu_op, slti_op, sltiu_op,$/;"	e	enum:major_op
sltu_op	include/ri.h	/^	spec3_unused_op, spec4_unused_op, slt_op, sltu_op,$/;"	e	enum:spec_op
socklen_t	include/types.h	/^typedef u_int32_t	socklen_t;	\/* length type for network syscalls *\/$/;"	t
sort_list	include/resolv.h	/^	} sort_list[MAXRESOLVSORT];$/;"	m	struct:__res_state	typeref:struct:__res_state::__anon4
spec1_unused_op	include/ri.h	/^	sllv_op, srlv_op, srav_op, spec1_unused_op, \/* Opcode 0x07 is unused *\/$/;"	e	enum:spec_op
spec2_unused_op	include/ri.h	/^	dsllv_op, spec2_unused_op, dsrlv_op, dsrav_op,$/;"	e	enum:spec_op
spec3_unused_op	include/ri.h	/^	spec3_unused_op, spec4_unused_op, slt_op, sltu_op,$/;"	e	enum:spec_op
spec4_unused_op	include/ri.h	/^	spec3_unused_op, spec4_unused_op, slt_op, sltu_op,$/;"	e	enum:spec_op
spec5_unused_op	include/ri.h	/^	teq_op, spec5_unused_op, tne_op, spec6_unused_op,$/;"	e	enum:spec_op
spec6_unused_op	include/ri.h	/^	teq_op, spec5_unused_op, tne_op, spec6_unused_op,$/;"	e	enum:spec_op
spec7_unused_op	include/ri.h	/^	dsll_op, spec7_unused_op, dsrl_op, dsra_op,$/;"	e	enum:spec_op
spec8_unused_op	include/ri.h	/^	dsll32_op, spec8_unused_op, dsrl32_op, dsra32_op$/;"	e	enum:spec_op
spec_fn_table	dev/kbd.c	/^static void_fnp spec_fn_table[16] = {$/;"	v	file:
spec_op	include/ri.h	/^	spec_op, bcond_op, j_op, jal_op,$/;"	e	enum:major_op
spec_op	include/ri.h	/^enum spec_op {$/;"	g
spim_op	include/ri.h	/^	syscall_op, break_op, spim_op, sync_op,$/;"	e	enum:spec_op
spimi_op	include/ri.h	/^	spimi_op, unused_rt_op_0x05, unused_rt_op_0x06, unused_rt_op_0x07,$/;"	e	enum:rt_op
spl	dev/generic_poll.c	/^volatile int spl;$/;"	v
sra_op	include/ri.h	/^	sll_op, movc_op, srl_op, sra_op,$/;"	e	enum:spec_op
srav_op	include/ri.h	/^	sllv_op, srlv_op, srav_op, spec1_unused_op, \/* Opcode 0x07 is unused *\/$/;"	e	enum:spec_op
srl_op	include/ri.h	/^	sll_op, movc_op, srl_op, sra_op,$/;"	e	enum:spec_op
srlv_op	include/ri.h	/^	sllv_op, srlv_op, srav_op, spec1_unused_op, \/* Opcode 0x07 is unused *\/$/;"	e	enum:spec_op
start	dev/pcibrvar.h	/^	bus_addr_t start;$/;"	m	struct:pci_reserve_mem
state	include/linux/zlib.h	/^    struct internal_state FAR *state; \/* not visible by applications *\/$/;"	m	struct:z_stream_s	typeref:struct:z_stream_s::FAR
stdenv	env.c	/^static struct stdenv$/;"	s	file:
stdenvtab	env.c	/^} stdenvtab[] =$/;"	v	typeref:struct:stdenv	file:
stderr	include/stdio.h	80;"	d
stdin	include/stdio.h	74;"	d
stdin	include/stdio.h	76;"	d
stdout	include/stdio.h	79;"	d
strempty	lib.c	/^int strempty (const char *p)$/;"	f
strequ	include/string.h	90;"	d
striequ	env.c	/^int striequ (const char *s1, const char *s2)$/;"	f
strpat	lib.c	/^int strpat (const char *s1, const char *s2)$/;"	f
strposn	lib.c	/^char *strposn (const char *p, const char *q)$/;"	f
strunames	include/arpa/ftp.h	/^char *strunames[] =  {"0", "File", "Record", "Page" };$/;"	v
sub_op	include/ri.h	/^	add_op, addu_op, sub_op, subu_op,$/;"	e	enum:spec_op
subu_op	include/ri.h	/^	add_op, addu_op, sub_op, subu_op,$/;"	e	enum:spec_op
sw_op	include/ri.h	/^	sb_op, sh_op, swl_op, sw_op,$/;"	e	enum:major_op
swblk_t	include/types.h	/^typedef	int32_t		swblk_t;	\/* swap offset *\/$/;"	t
swc1_op	include/ri.h	/^	sc_op, swc1_op, swc2_op, major_3b_op, \/* Opcode 0x3b is unused *\/$/;"	e	enum:major_op
swc2_op	include/ri.h	/^	sc_op, swc1_op, swc2_op, major_3b_op, \/* Opcode 0x3b is unused *\/$/;"	e	enum:major_op
swl_op	include/ri.h	/^	sb_op, sh_op, swl_op, sw_op,$/;"	e	enum:major_op
swr_op	include/ri.h	/^	sdl_op, sdr_op, swr_op, cache_op,$/;"	e	enum:major_op
swxc1_op	include/ri.h	/^	pfetch_op    =  0x07, swxc1_op     =  0x08,$/;"	e	enum:cop1x_func
sym_ntop	include/resolv.h	206;"	d
sym_ntos	include/resolv.h	205;"	d
sym_ston	include/resolv.h	204;"	d
sync_op	include/ri.h	/^	syscall_op, break_op, spim_op, sync_op,$/;"	e	enum:spec_op
syscall_op	include/ri.h	/^	syscall_op, break_op, spim_op, sync_op,$/;"	e	enum:spec_op
t	include/termio.h	/^	struct termio t;$/;"	m	struct:DevEntry	typeref:struct:DevEntry::termio
tc	include/arpa/nameser.h	/^	unsigned	tc :1;		\/* truncated message *\/$/;"	m	struct:__anon3
tc	include/arpa/nameser.h	/^	unsigned	tc: 1;		\/* truncated message *\/$/;"	m	struct:__anon3
telcmds	include/arpa/telnet.h	/^char *telcmds[] = {$/;"	v
telopts	include/arpa/telnet.h	/^char *telopts[NTELOPTS+1] = {$/;"	v
teq_op	include/ri.h	/^	teq_op, spec5_unused_op, tne_op, spec6_unused_op,$/;"	e	enum:spec_op
teqi_op	include/ri.h	/^	teqi_op, unused_0x0d_rt_op, tnei_op, unused_0x0f_rt_op,$/;"	e	enum:rt_op
termio	include/termio.h	/^struct termio {$/;"	s
tftphdr	include/arpa/tftp.h	/^struct	tftphdr {$/;"	s
tfunc	include/termio.h	/^	int(*tfunc) (int, int, int, int);$/;"	m	struct:DevEntry
tge_op	include/ri.h	/^	tge_op, tgeu_op, tlt_op, tltu_op,$/;"	e	enum:spec_op
tgei_op	include/ri.h	/^	tgei_op, tgeiu_op, tlti_op, tltiu_op,$/;"	e	enum:rt_op
tgeiu_op	include/ri.h	/^	tgei_op, tgeiu_op, tlti_op, tltiu_op,$/;"	e	enum:rt_op
tgeu_op	include/ri.h	/^	tge_op, tgeu_op, tlt_op, tltu_op,$/;"	e	enum:spec_op
tgt_clockram_read	dev/mc146818.c	/^int tgt_clockram_read(char *data, int offset, int nbytes)$/;"	f
tgt_clockram_write	dev/mc146818.c	/^int tgt_clockram_write(char *data, int offset, int nbytes)$/;"	f
tgt_fl_map_boot8	tgt_flash.c	/^struct fl_map tgt_fl_map_boot8[] = {$/;"	v	typeref:struct:fl_map
tgt_flashinfo	tgt_flash.c	/^void tgt_flashinfo (void *p, size_t * t)$/;"	f
tgt_flashmap	tgt_flash.c	/^struct fl_map *tgt_flashmap ()$/;"	f
tgt_flashprogram	tgt_flash.c	/^void tgt_flashprogram (void *p, int size, void *s, int endian)$/;"	f
tgt_flashwrite_disable	tgt_flash.c	/^void tgt_flashwrite_disable ()$/;"	f
tgt_flashwrite_enable	tgt_flash.c	/^int tgt_flashwrite_enable ()$/;"	f
tgt_gettime	dev/mc146818.c	/^time_t tgt_gettime()$/;"	f
tgt_mapenv	dev/fl_nvram.c	/^void tgt_mapenv(int (*func) __P((char *, char *)))$/;"	f
tgt_mapenv	tgt_env.c	/^void tgt_mapenv (int (*func) __P ((char *, char *)))$/;"	f
tgt_onesecond	dev/mc146818.c	/^int tgt_onesecond(int timeout)$/;"	f
tgt_poll	dev/generic_poll.c	/^void tgt_poll()$/;"	f
tgt_poll_register	dev/generic_poll.c	/^void *tgt_poll_register(level, func, arg)$/;"	f
tgt_rtinit	dev/mc146818.c	/^void tgt_rtinit()$/;"	f
tgt_setenv	dev/fl_nvram.c	/^int tgt_setenv(char *name, char *value)$/;"	f
tgt_setenv	tgt_env.c	/^int tgt_setenv (char *name, char *value)$/;"	f
tgt_settime	dev/mc146818.c	/^void tgt_settime(time_t t)$/;"	f
tgt_smplock	include/pmon.h	370;"	d
tgt_smpunlock	include/pmon.h	371;"	d
tgt_unsetenv	dev/fl_nvram.c	/^int tgt_unsetenv(char *name)$/;"	f
tgt_unsetenv	tgt_env.c	/^int tgt_unsetenv (char *name)$/;"	f
th_block	include/arpa/tftp.h	66;"	d
th_code	include/arpa/tftp.h	67;"	d
th_data	include/arpa/tftp.h	/^	char	th_data[1];		\/* data or error string *\/$/;"	m	struct:tftphdr
th_msg	include/arpa/tftp.h	69;"	d
th_opcode	include/arpa/tftp.h	/^	u_int16_t th_opcode;		\/* packet type *\/$/;"	m	struct:tftphdr
th_stuff	include/arpa/tftp.h	68;"	d
th_u	include/arpa/tftp.h	/^	} th_u;$/;"	m	struct:tftphdr	typeref:union:tftphdr::__anon2
time_t	include/time.h	/^typedef	_BSD_TIME_T_	time_t;$/;"	t
tlbp1_op	include/ri.h	/^	tlbp1_op      = 0x08, dctr_op       = 0x09,$/;"	e	enum:cop0_com_func
tlbp_op	include/ri.h	/^	tlbwr_op      = 0x06, tlbp_op       = 0x08,$/;"	e	enum:cop0_coi_func
tlbr1_op	include/ri.h	/^	tlbr1_op      = 0x01, tlbw_op       = 0x02,$/;"	e	enum:cop0_com_func
tlbr_op	include/ri.h	/^	tlbr_op       = 0x01, tlbwi_op      = 0x02,$/;"	e	enum:cop0_coi_func
tlbw_op	include/ri.h	/^	tlbr1_op      = 0x01, tlbw_op       = 0x02,$/;"	e	enum:cop0_com_func
tlbwi_op	include/ri.h	/^	tlbr_op       = 0x01, tlbwi_op      = 0x02,$/;"	e	enum:cop0_coi_func
tlbwr_op	include/ri.h	/^	tlbwr_op      = 0x06, tlbp_op       = 0x08,$/;"	e	enum:cop0_coi_func
tlt_op	include/ri.h	/^	tge_op, tgeu_op, tlt_op, tltu_op,$/;"	e	enum:spec_op
tlti_op	include/ri.h	/^	tgei_op, tgeiu_op, tlti_op, tltiu_op,$/;"	e	enum:rt_op
tltiu_op	include/ri.h	/^	tgei_op, tgeiu_op, tlti_op, tltiu_op,$/;"	e	enum:rt_op
tltu_op	include/ri.h	/^	tge_op, tgeu_op, tlt_op, tltu_op,$/;"	e	enum:spec_op
tm	include/time.h	/^struct tm {$/;"	s
tm_gmtoff	include/time.h	/^	long	tm_gmtoff;	\/* offset from CUT in seconds *\/$/;"	m	struct:tm
tm_hour	include/time.h	/^	int	tm_hour;	\/* hours since midnight [0-23] *\/$/;"	m	struct:tm
tm_isdst	include/time.h	/^	int	tm_isdst;	\/* Daylight Savings Time flag *\/$/;"	m	struct:tm
tm_mday	include/time.h	/^	int	tm_mday;	\/* day of the month [1-31] *\/$/;"	m	struct:tm
tm_min	include/time.h	/^	int	tm_min;		\/* minutes after the hour [0-59] *\/$/;"	m	struct:tm
tm_mon	include/time.h	/^	int	tm_mon;		\/* months since January [0-11] *\/$/;"	m	struct:tm
tm_sec	include/time.h	/^	int	tm_sec;		\/* seconds after the minute [0-60] *\/$/;"	m	struct:tm
tm_wday	include/time.h	/^	int	tm_wday;	\/* days since Sunday [0-6] *\/$/;"	m	struct:tm
tm_yday	include/time.h	/^	int	tm_yday;	\/* days since January 1 [0-365] *\/$/;"	m	struct:tm
tm_year	include/time.h	/^	int	tm_year;	\/* years since 1900 *\/$/;"	m	struct:tm
tm_zone	include/time.h	/^	char	*tm_zone;	\/* timezone abbreviation *\/$/;"	m	struct:tm
tname	include/termio.h	/^	char *tname;$/;"	m	struct:DevEntry
tne_op	include/ri.h	/^	teq_op, spec5_unused_op, tne_op, spec6_unused_op,$/;"	e	enum:spec_op
tnei_op	include/ri.h	/^	teqi_op, unused_0x0d_rt_op, tnei_op, unused_0x0f_rt_op,$/;"	e	enum:rt_op
toascii	include/ctype.h	105;"	d
tolower	include/ctype.h	97;"	d
total_in	include/linux/zlib.h	/^    uLong    total_in;  \/* total nb of input bytes read so far *\/$/;"	m	struct:z_stream_s
total_out	include/linux/zlib.h	/^    uLong    total_out; \/* total nb of bytes output so far *\/$/;"	m	struct:z_stream_s
toupper	include/ctype.h	98;"	d
tu_block	include/arpa/tftp.h	/^		u_int16_t tu_block;	\/* block # *\/$/;"	m	union:tftphdr::__anon2
tu_code	include/arpa/tftp.h	/^		u_int16_t tu_code;	\/* error code *\/$/;"	m	union:tftphdr::__anon2
tu_stuff	include/arpa/tftp.h	/^		char	tu_stuff[1];	\/* request packet stuff *\/$/;"	m	union:tftphdr::__anon2
txoff	include/termio.h	/^	int txoff;$/;"	m	struct:DevEntry
txq	include/termio.h	/^	Queue *txq;$/;"	m	struct:DevEntry
typenames	include/arpa/ftp.h	/^char *typenames[] =  {"0", "ASCII", "EBCDIC", "Image", "Local" };$/;"	v
uInt	include/linux/zconf.h	/^typedef unsigned int   uInt;  \/* 16 bits or more *\/$/;"	t
uIntf	include/linux/zconf.h	/^typedef uInt  FAR uIntf;$/;"	t
uLong	include/linux/zconf.h	/^typedef unsigned long  uLong; \/* 32 bits or more *\/$/;"	t
uLongf	include/linux/zconf.h	/^typedef uLong FAR uLongf;$/;"	t
u_char	include/types.h	/^typedef	unsigned char	u_char;$/;"	t
u_int	include/types.h	/^typedef	unsigned int	u_int;$/;"	t
u_int16_t	include/types.h	/^typedef	unsigned short		u_int16_t;$/;"	t
u_int32_t	include/types.h	/^typedef	unsigned int		u_int32_t;$/;"	t
u_int64_t	include/types.h	/^typedef	unsigned long long	u_int64_t;$/;"	t
u_int8_t	include/types.h	/^typedef	unsigned char		 u_int8_t;$/;"	t
u_long	include/types.h	/^typedef	unsigned long	u_long;$/;"	t
u_quad_t	include/types.h	/^typedef	u_int64_t	u_quad_t;	\/* quads *\/$/;"	t
u_short	include/types.h	/^typedef	unsigned short	u_short;$/;"	t
uch	include/linux/zutil.h	/^typedef unsigned char  uch;$/;"	t
uchf	include/linux/zutil.h	/^typedef uch FAR uchf;$/;"	t
uid_t	include/types.h	/^typedef	u_int32_t	uid_t;		\/* user id *\/$/;"	t
uint	include/types.h	/^typedef	unsigned int	uint;		\/* Sys V compatibility *\/$/;"	t
uint16_t	include/types.h	/^typedef	unsigned short		 uint16_t;$/;"	t
uint32_t	include/types.h	/^typedef	unsigned int		 uint32_t;$/;"	t
uint64_t	include/types.h	/^typedef	unsigned long long	 uint64_t;$/;"	t
uint8_t	include/types.h	/^typedef	unsigned char		  uint8_t;$/;"	t
ulg	include/linux/zutil.h	/^typedef unsigned long  ulg;$/;"	t
ulong	include/types.h	/^typedef unsigned long	ulong;		\/* Sys V compatibility *\/$/;"	t
unchar	include/types.h	/^typedef unsigned char	unchar;		\/* Sys V compatibility *\/$/;"	t
ungetcflag	include/stdio.h	/^	int ungetcflag;$/;"	m	struct:FILE
ungetchar	include/stdio.h	/^	int ungetchar;$/;"	m	struct:FILE
unsetenv	env.c	/^void unsetenv (pat)$/;"	f
unused	include/arpa/nameser.h	/^	unsigned	unused :1;	\/* unused bits (MBZ as of 4.9.3a3) *\/$/;"	m	struct:__anon3
unused	include/resolv.h	/^	char	unused[3];$/;"	m	struct:__res_state
unused_0x0d_rt_op	include/ri.h	/^	teqi_op, unused_0x0d_rt_op, tnei_op, unused_0x0f_rt_op,$/;"	e	enum:rt_op
unused_0x0f_rt_op	include/ri.h	/^	teqi_op, unused_0x0d_rt_op, tnei_op, unused_0x0f_rt_op,$/;"	e	enum:rt_op
unused_rt_op_0x05	include/ri.h	/^	spimi_op, unused_rt_op_0x05, unused_rt_op_0x06, unused_rt_op_0x07,$/;"	e	enum:rt_op
unused_rt_op_0x06	include/ri.h	/^	spimi_op, unused_rt_op_0x05, unused_rt_op_0x06, unused_rt_op_0x07,$/;"	e	enum:rt_op
unused_rt_op_0x07	include/ri.h	/^	spimi_op, unused_rt_op_0x05, unused_rt_op_0x06, unused_rt_op_0x07,$/;"	e	enum:rt_op
useconds_t	include/types.h	/^typedef	u_int32_t	useconds_t;	\/* microseconds *\/$/;"	t
user_mode	include/ri.h	254;"	d
username	include/url.h	/^	char		username[USERNAMESIZE];$/;"	m	struct:Url
ush	include/linux/zutil.h	/^typedef unsigned short ush;$/;"	t
ushf	include/linux/zutil.h	/^typedef ush FAR ushf;$/;"	t
ushort	include/types.h	/^typedef	unsigned short	ushort;		\/* Sys V compatibility *\/$/;"	t
v	include/tgt/pio.h	/^	u_int32_t v;$/;"	v
v	include/tgt/pio.h	/^        u_int16_t v;$/;"	v
vaddr_t	include/types.h	/^typedef unsigned long	vaddr_t;$/;"	t
vaddr_t_l	include/ri.h	/^typedef void * vaddr_t_l;$/;"	t
val	dev/mpc106reg.h	/^	u_int16_t val;$/;"	v
val	dev/mpc106reg.h	/^	u_int32_t val;$/;"	v
val	dev/mpc106reg.h	/^	u_int8_t val;$/;"	v
val	include/types.h	/^	register_t val[12];$/;"	m	struct:label_t
valid	include/file.h	/^	short valid;$/;"	m	struct:File
valid	include/stdio.h	/^	int valid;$/;"	m	struct:FILE
value	include/pmon.h	/^    unsigned long   value;$/;"	m	struct:Bps
value	include/pmon.h	/^    unsigned long   value;$/;"	m	struct:Stopentry
value	include/pmonenv.h	/^    char	*value;$/;"	m	struct:envpair
values	env.c	/^	char *values;$/;"	m	struct:stdenv	file:
vga_roll	dev/vgacon.c	/^void vga_roll()$/;"	f
vga_set_enter	dev/vgacon.c	/^void vga_set_enter()$/;"	f
vgabh	dev/vgacon.c	/^unsigned char *vgabh = (unsigned char *)(VGA_BASE + 0xb8000);$/;"	v
vgaout	include/stdio.h	82;"	d
vgaterm	dev/vgacon.c	/^int vgaterm(int op, struct DevEntry *dev, unsigned long param, int data)$/;"	f
vm_offset_t	include/types.h	/^typedef	unsigned long	vm_offset_t;$/;"	t
vm_size_t	include/types.h	/^typedef	unsigned long	vm_size_t;$/;"	t
void_fn	dev/kbd.c	/^typedef void (void_fn) (void);$/;"	t	file:
void_fnp	dev/kbd.c	/^typedef void (*void_fnp) (void);$/;"	t	file:
voidp	include/linux/zconf.h	/^typedef void     *voidp;$/;"	t
voidpf	include/linux/zconf.h	/^typedef void FAR *voidpf;$/;"	t
volatile	include/cdefs.h	108;"	d
volatile	include/types.h	83;"	d
vsize_t	include/types.h	/^typedef unsigned long	vsize_t;$/;"	t
w_fmt	include/ri.h	/^	w_fmt, l_fmt$/;"	e	enum:cop1_fmt
whatcpu	include/pmon.h	/^int		whatcpu;		\/* Cpu selected for debug *\/$/;"	v
whatcpu	include/pmon.h	369;"	d
widedata	dev/flash.c	/^static quad_t widedata;$/;"	v	file:
widedata	dev/flash_amd.c	/^static quad_t widedata;$/;"	v	file:
widedata	dev/flash_int.c	/^static quad_t widedata;$/;"	v	file:
widedata	dev/flash_sst.c	/^static quad_t widedata;$/;"	v	file:
widedata	dev/flash_st.c	/^static quad_t widedata;$/;"	v	file:
widedata	dev/flash_winbond.c	/^static quad_t widedata;$/;"	v	file:
wordsz	lib.c	/^int wordsz (const char *p)$/;"	f
workspace	include/linux/zlib.h	/^    void     *workspace; \/* memory allocated for this stream *\/$/;"	m	struct:z_stream_s
write	include/diskfs.h	/^	int (*write) __P((int , const void *, size_t));$/;"	m	struct:DiskFileSystem
write	include/file.h	/^	int	(*write) (int , const void *, size_t);$/;"	m	struct:FileSystem
write_at_cursor	dev/vgacon.c	/^int write_at_cursor(char val)$/;"	f
xEOF	include/arpa/telnet.h	64;"	d
xor_op	include/ri.h	/^	and_op, or_op, xor_op, nor_op,$/;"	e	enum:spec_op
xori_op	include/ri.h	/^	andi_op, ori_op, xori_op, lui_op,$/;"	e	enum:major_op
z_off_t	include/linux/zconf.h	88;"	d
z_stream	include/linux/zlib.h	/^} z_stream;$/;"	t	typeref:struct:z_stream_s
z_stream_s	include/linux/zlib.h	/^typedef struct z_stream_s {$/;"	s
z_streamp	include/linux/zlib.h	/^typedef z_stream FAR *z_streamp;$/;"	t
zlib_adler32	include/linux/zutil.h	/^static inline uLong zlib_adler32(uLong adler,$/;"	f
zlib_deflateInit	include/linux/zlib.h	636;"	d
zlib_deflateInit2	include/linux/zlib.h	640;"	d
zlib_inflateInit	include/linux/zlib.h	638;"	d
zlib_inflateInit2	include/linux/zlib.h	643;"	d
